ADP3209DJCPZ-RL [ONSEMI]
Synchronous Buck Controller, 5-Bit, Programmable, Single-Phase;
| 型号： | ADP3209DJCPZ-RL |
| 厂家： | 
ONSEMI |
| 描述： | Synchronous Buck Controller, 5-Bit, Programmable, Single-Phase 开关 |
| 文件： | 总32页 (文件大小：752K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5-Bit, Programmable, Single-Phase,
Synchronous Buck Controller
ADP3209
FEATURES
GENERAL DESCRIPTION
Single-chip solution
Fully compatible with the Intel® GMCH chipset voltage
regulator specifications
Integrated MOSFET drivers
8 mꢀ worst-case differentially sensed core voltage error
over temperature
Automatic power-saving modes maximize efficiency during
light load operation
Soft transient control reduces inrush current and audio noise
Independent current limit and load line setting inputs for
additional design flexibility
The ADP3209 is a highly efficient, single-phase, synchronous
buck switching regulator controller. With its integrated drivers,
the ADP3209 is optimized for converting the notebook battery
voltage to render the supply voltage required by high performance
Intel chipsets. An internal 5-bit DAC is used to read a VID code
directly from the chipset and to set the GMCH core voltage to a
value within the range of 0.4 V to 1.25 V.
The ADP3209 uses a multimode architecture. It provides program-
mable switching frequency that can be optimized for efficiency
depending on the output current requirement. In addition, the
ADP3209 includes a programmable load line slope function to
adjust the output voltage as a function of the load current so that
the core voltage is always optimally positioned for a load transient.
The ADP3209 also provides accurate and reliable current overload
protection and a delayed power-good output. The IC supports
on-the-fly output voltage changes requested by the chipset.
Built-in power-good masking supports
voltage identification (ꢀID) on-the-fly transients
5-bit, digitally programmable DAC with 0.4 ꢀ to 1.25 ꢀ output
Short-circuit protection with programmable latch-off delay
Output power or current monitor options
32-lead LFCSP
APPLICATIONS
Notebook power supplies for next-generation Intel chipsets
The ADP3209 is specified over the extended commercial tempera-
ture range of 0°C to 100°C and is available in a 32-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
RAMP VRPM RPM
RT
BST
OSCILLATOR
DRV
IN
ODB
ODA
DRVH
SW
PVCC
DRVL
PWM
RAMP
PWM
LATCH
GENER-
CMPS
PHASE
CONTROL
ATOR
PGND
+
–
–
+
SWITCH
AMPS
VREF
COMP
VID4
VID3
VID2
VID1
VID0
ERR AMP
VDAC
–
VID
DAC
FB
REFERENCE
SELECT
+
SS
+
–
LLINE
–
FBRTN
CSAMP
CSFB
ST
+
CSREF
CSCOMP
CLIM
CMP
VARFREQ
SS
CLREF
CLTHSEL
HOUSE-
KEEPING
–
+
+
+
–
–
PWRGD
CLIM
REFTH
REF
BIAS
BIAS
EN
VCC
GND
UVLO
CSAVG
–
VREF
PMON
PWM
+
ADP3209
FBRTN
PMON PMONFS
Figure 1.
©2008 SCILLC. All rights reserved.
January 2008 – Rev. 2
Publication Order Number:
ADP3209/D
ADP3209
TABLE OF CONTENTS
Features...............................................................................................1
Reverse Voltage Protection........................................................18
Output Enable and UVLO.........................................................19
Power Monitor Function ...........................................................19
Application Information ................................................................22
Setting the Clock Frequency for PWM....................................22
Setting the Switching Frequency for RPM Operation ...........22
Soft Start and Current Limit Latch-Off Delay Times ............22
Inductor Selection.......................................................................23
COUT Selection..............................................................................25
Power MOSFETs .........................................................................26
Ramp Resistor Selection ............................................................27
COMP Pin Ramp........................................................................27
Current Limit Setpoint...............................................................27
Power Monitor ............................................................................27
Feedback Loop Compensation Design....................................27
CIN Selection and Input Current di/dt Reduction ..................29
Soft Transient Setting .................................................................29
Tuning Procedure for ADP3209 ...............................................29
Layout and Component Placement..........................................30
Outline Dimension .........................................................................32
Ordering Guide...........................................................................32
Applications .......................................................................................1
General Description..........................................................................1
Functional Block Diagram...............................................................1
Revision History................................................................................2
Specifications .....................................................................................3
Timing Diagram................................................................................6
Absolute Maximum Ratings ............................................................7
ESD Caution ..................................................................................7
Pin Configuration and Function Descriptions .............................8
Typical Performance Characteristics............................................10
Theory of Operation.......................................................................13
Operation Modes ........................................................................13
Differential Sensing of Output Voltage....................................15
Output Current Sensing.............................................................15
Active Impedance Control Mode .............................................15
Voltage Control Mode ................................................................16
Power-Good Monitoring ...........................................................16
Power-Up Sequence and Soft Start...........................................16
VID Change and Soft Transient................................................16
Current Limit, Short-Circuit, and Latch-Off Protection.......17
Output Crowbar..........................................................................18
REꢀISION HISTORY
01/08 - Rev 2: Conversion to ON Semiconductor
9/07—Rev. Sp0 to Rev. SpA
Changes to Absolute Maximum Ratings........................................7
Change to Table 3..............................................................................8
Change to the Setting the Clock Frequency for PWM Section.......22
Changes to Ordering Guide.....................................................................32
10/06—Revision Sp0: Initial Version
Rev. 2 | Page 2 of 32 | www.onsemi.com
ADP3209
SPECIFICATIONS
VCC = 5 V, FBRTN = GND, VARFREQ = low, VVID = 1.25 V, TA = 0°C to 100°C, unless otherwise noted.1 Current entering a pin (sunk by
the device) has a positive sign.
Table 1.
Parameter
Symbol
Conditions
Min
0.8
−8
Typ
Max
3.6
Unit
VOLTAGE ERROR AMPLIFIER
Output Voltage Range2
COMP Clamp
VCOMP
VCOMP
VFB
V
V
mV
CSREF < 0.2 V
1.6
DC Accuracy
Relative to nominal VVID, LLINE = CSREF,
VVID range = 0.4000 V to 1.25000 V
LLINE − CSREF = −80 mV
+8
Load Line Positioning Accuracy
76
80
83
mV
mV
nA
LSB
%
∆VFB
LLINE − CSREF = −200 mV
190
−80
−1
200
210
+80
+1
LLINE Input Bias Current
Differential Nonlinearity
VCC Line Regulation
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product2
Slew Rate2
ILLINE
VCC = 4.75 V to 5.25 V
0.05
∆VFB
IFB
IFBRTN
ICOMP
GBW(ERR)
−1
+1
400
µA
µA
µA
MHz
V/µs
200
500
20
FB forced to VVID − 3%
COMP = FB, CCOMP = 0 pF
CCOMP = 10 pF
25
VID DAC INPUTS
Input Low Voltage
Input High Voltage
Input Current
VIL
VIH
IIN(VID)
VID(x)
VID(x)
0.5
3
V
V
µA
ns
2.2
400
0.3
Sink current
VID code change to FB change
1
VID Transition Delay Time2
OSCILLATOR
Frequency Range2
Oscillator Frequency
fOSC
fOSC
MHz
kHz
MHz
V
= high, RT = 250 kΩ
= high, RT = 125 kΩ
= low, VVID = 1.250 V
= high (forced PWM mode)
550
1
VARFREQ
VARFREQ
VARFREQ
VARFREQ
RT Output Voltage
VRT
1.09
1.6
1.125
1.2
1.7
1
1
1.8
V
VRPM Reference Voltage
VVRPM
IVRPM = 0 µA
IVRPM = 120 µA
0.95
0.95
1.05
1.05
V
V
RPM Output Current
RPM Comparator Offset
RAMP Input Voltage
RAMP Input Current Range
RAMP Input Current in Shutdown
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product2
Slew Rate2
IRPM
VVID = 1.250 V, RT = 250 kΩ
VOS(RPM) = VCOMP − VRPM
−5
−11
1.0
µA
mV
V
µA
µA
VOS(RPM)
VRAMP
IRAMP
0.9
1
1.1
50
EN = high
EN = low or in UVLO, RAMP = 19 V
1
VOS(CSA)
IBIAS(CSFB)
GBW(CSA)
CSFB − CSREF
−1.2
−65
+1.2
+65
mV
nA
MHz
V/µs
V
V
µA
mA
6
10
CCSCOMP = 10 pF
CSFB and CSREF
Input Common-Mode Range2
Output Voltage Range
Output Current
0
0.05
400
3.5
2.7
VCSCOMP
ICSCOMP
Sink current
Source current
1000
−15
−8
Rev. 2 | Page 3 of 32 | www.onsemi.com
ADP3209
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SWITCH AMPLIFIER
Common-Mode Range2
Input Resistance
Input Current
VSW
RSW
ISW
VZCS(SW)
tOFFMASK
−400
30
+200
60
mV
kΩ
µA
mV
ns
45
SW = 0 V
−4
−6
475
Zero Current Switching Threshold
DCM Minimum Off Time Masking
CURRENT LIMIT COMPARATOR
Output Voltage Range2
Output Current
Current Limit Threshold Voltage
Current Limit Setting Ratio
SOFT START/LATCH-OFF TIMER
Output Current
SW falling
VCLIM
ICLIM
VCLTH
0.5
3
V
µA
mV
VCLIM = 1.25 V
VCSREF − VCSCOMP, RCLIM = 125 kΩ
VCL/VCLIM
−10
125
0.1
105
145
ISS
During startup, VSS < 1.7 V
In normal mode, VSS > 1.7 V
In current limit, VSS > 1.7 V
During startup
After PWRGD goes high
Current limit or PWRGD failure, SS falling
−11
−7.5
−48
2
1.7
2.9
1.7
−5
µA
µA
µA
V
V
V
1.5
1.6
2.5
1.8
Termination Threshold Voltage
Normal Mode Operating Voltage
Current Limit Latch-Off Voltage
SOFT TRANSIENT CONTROL
ST Sourcing Current
ST Sinking Current
ST Offset Voltage
Minimum Capacitance
VTH(SS)
VILO(SS)
1.6
1.8
ISOURCE(ST)
ISINK(ST)
VOS(ST)
CST
ST = VDAC − 0.3 V
ST = VDAC + 0.3 V
|ST − VVID| at the end of PWRGD masking
−7.5
2.5
µA
µA
mV
pF
−10
100
+35
Extended PWRGD Masking
Comparator Threshold
VTH(ST)
|ST − VVID|, ST falling
150
mV
SYSTEM LOGIC INPUTS
Input Low Voltage
VIL
0.7
1.0
V
VARFREQ
EN
V
Input High Voltage
Input Current
VIH
4
V
VARFREQ
EN
2.3
V
nA
µA
IIN
IIN
EN,
20
60
VARFREQ
EN = VTH, high-to-low or low-to-high
POWER GOOD
CSREF Undervoltage Threshold
CSREF Overvoltage Threshold
CSREF Crowbar (Overvoltage
Protection) Threshold
VUV(CSREF)
VOV(CSREF)
VCB(CSREF)
Relative to VVID = 0.4 V to 1.25 V
Relative to VVID = 0.4 V to 1.25 V
Relative to FBRTN
−300
200
1.7
mV
mV
V
250
1.75
1.65
CSREF Reverse Voltage Detection
Threshold
VRVP(CSREF)
Relative to FBRTN
CSREF falling
CSREF rising
ISINK(PWRGD) = 4 mA
VPWRDG = 5 V
−425
−300
−60
60
mV
mV
mV
µA
µs
PWRGD Output Low Voltage
PWRGD Output Leakage Current
PWRGD Masking Time
VOL(PWRGD)
100
3
100
POWER MONITOR
PMON Output Resistance
PMON Leakage Current
PMON Oscillator Frequency
PMONFS Voltage Range2
PMONFS Output Current
ISINK = 2 mA
PMON = 5 V
PMONFS = 2 V
15
5
320
Ω
nA
kHz
V
1.5
4
PMONFS = 2 V
−10
µA
Rev. 2 | Page 4 of 32 | www.onsemi.com
ADP3209
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
HIGH-SIDE MOSFET DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
BST − SW = 4.6 V
BST − SW = 4.6 V
BST − SW = 4.6 V, CL = 3 nF, Figure 2
BST − SW = 4.6 V, CL = 3 nF, Figure 2
BST − SW = 4.6 V, Figure 2
EN = low, shutdown
1.6
1.3
15
13
10
5
3.3
2.8
35
31
30
15
Ω
Ω
trDRVH,
tfDRVH
tpdhDRVH
ns
ns
ns
µA
µA
Dead Delay Times
BST Quiescent Current
EN = high, no switching
200
LOW-SIDE MOSFET DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
1.4
1
15
14
10
130
2.2
14
3.0
2.7
35
35
30
Ω
Ω
trDRVL,
tfDRVL
tpdhDRVL
tTO(SW)
VZC
CL = 3 nF, Figure 2
CL = 3 nF, Figure 2
CL = 3 nF, Figure 2
BST − SW = 4.6 V
ns
ns
ns
ns
V
Propagation Delay Times
SW Transition Timeout
Zero-Crossing Threshold
PVCC Quiescent Current
85
200
EN = low, shutdown
EN = high, no switching
50
µA
µA
170
SOFT STOP
CSREF Resistance to GND
EN = low or latch off
70
Ω
SUPPLY
Supply Voltage Range2
Supply Current
VCC
4.5
5.5
9
40
4.5
V
Normal mode
EN = 0 V
VCC rising
VCC falling
5
6
4.4
4.2
mA
µA
V
V
mV
VCC OK Threshold Voltage
VCC UVLO Threshold Voltage
UVLO Hysteresis2
VCCOK
VCCUVLO
4.0
150
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 Guaranteed by design or bench characterization, not production tested.
Rev. 2 | Page 5 of 32 | www.onsemi.com
ADP3209
TIMING DIAGRAM
Timing is referenced to the 90% and 10% points, unless otherwise noted.
IN
tf
tpdl
DRVL
DRVL
tpdl
DRVH
tr
DRVL
DRVL
tf
DRVH
tpdh
DRVH
tr
DRVH
V
V
TH
TH
DRVH
(WITH RESPECT
TO SW)
tpdh
DRVL
1V
SW
Figure 2. Timing Diagram
Rev. 2 | Page 6 of 32 | www.onsemi.com
ADP3209
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC
FBRTN, PGND
BST
DC
t < 200 ns
DRVH, SW
DC
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−0.3 V to +25 V
−0.3 V to +30 V
−5 V to +20 V
−10 V to +25 V
t < 200 ns
ESD CAUTION
DRVL to PGND
DC
t < 200 ns
−0.3 V to +6 V
−5 V to +6 V
RAMP (in Shutdown)
DC
t < 200 ns
−0.3 V to +20 V
−0.3 V to +25 V
−0.3 V to +6 V
−65°C to +150°C
0°C to 100°C
125°C
All Other Inputs and Outputs
Storage Temperature
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA) 2-Layer Board
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
32.6°C/W
300°C
260°C
Rev. 2 | Page 7 of 32 | www.onsemi.com
ADP3209
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FBRTN
FB
COMP
SS
ST
PMON
PMONFS
CLIM
1
2
3
4
5
6
7
8
24 VCC
23 BST
22 DRVH
PIN 1
INDICATOR
ADP3209
21 SW
TOP VIEW
20 PVCC
19 DRVL
18 PGND
17 GND
(Not to Scale)
Figure 3. LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
FBRTN
Feedback Return Input/Output. This pin remotely senses the GMCH voltage. It is also used as the
ground return for the VID DAC and the voltage error amplifier blocks.
2
3
4
FB
COMP
SS
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
Voltage Error Amplifier Output and Frequency Compensation Point.
Soft Start and Latch-Off Delay Setting Input/Output. An external capacitor from this pin to GND sets
the soft start ramp-up time and the current limit latch-off delay ramp-down time.
5
6
ST
Soft Transient Slew Rate Timing Input/Output. A capacitor from this pin to GND sets the slew rate of
the output voltage when it transitions from one VID setting to another.
Power Monitor Output. Open-drain output. A pull-up resistor from PMON to CSREF provides a duty
cycle–modulated power output signal. An external RC network can be used to convert the digital
signal stream to an averaged power analog output voltage.
PMON
7
8
9
PMONFS
CLIM
Power Monitor Full-Scale Setting Input/Output. A resistor from this pin to GND sets the full-scale
value of the PMON output signal.
Current Limit Setting Input/Output. An external resistor from this pin to GND sets the current limit
threshold of the converter.
Load Line Programming Input. The center point of a resistor divider connected between CSREF and
CSCOMP can be tied to this pin to set the load line slope.
LLINE
10
11
12
CSCOMP
CSREF
CSFB
Current Sense Amplifier Output and Frequency Compensation Point.
Current Sense Reference Input. This pin must be connected to the opposite side of the output inductor.
Noninverting Input of the Current Sense Amplifier. The combination of a resistor from the switch
node to this pin and the feedback network from this pin to the CSCOMP pin sets the gain of the
current sense amplifier.
13
RAMP
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this
pin sets the slope of the internal PWM stabilizing ramp.
14
15
VRPM
RPM
RPM Mode Reference Voltage Output.
Ramp Pulse Modulation Current Source Output. A resistor between this pin and VRPM sets the RPM
comparator upper threshold.
16
RT
PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM
oscillator frequency.
17
18
19
20
GND
Analog and Digital Signal Ground.
Low-Side Driver Power Ground. This pin should be connected close to the source of the lower MOSFET(s).
Low-Side Gate Drive Output.
PGND
DRVL
PVCC
Power Supply Input/Output of Low-Side Gate Driver.
Rev. 2 | Page 8 of 32 | www.onsemi.com
ADP3209
Pin No.
21
22
Mnemonic
SW
DRVH
BST
Description
Current Return For High-Side Gate Drive.
High-Side Gate Drive Output.
High-Side Bootstrap Supply. A capacitor from this pin to SW holds the bootstrapped voltage while
the high-side MOSFET is on.
23
24
VCC
Power Supply Input/Output of the Controller.
25 to 29
VID4 to VID0
Voltage Identification DAC Inputs. A 5-bit word (the VID code) programs the DAC output voltage, the
reference voltage of the voltage error amplifier without a load (see the VID code table, Table 4). In
normal operation mode, the VID DAC output programs the output voltage to a value within the 0 V to
1.25 V range. The input is actively pulled down.
30
31
EN
PWRGD
Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, and pulls PWRGD low.
Power-Good Output. Open-drain output. A low logic state means that the output voltage is outside
of the VID DAC defined range.
32
Variable Frequency Enable Input. Pulling this pin to ground sets the normal RPM mode of operation.
Pulling this pin to 5 V sets the fixed-frequency PWM mode of operation.
VARFREQ
Rev. 2 | Page 9 of 32 | www.onsemi.com
ADP3209
TYPICAL PERFORMANCE CHARACTERISTICS
VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted.
90
440
390
340
290
240
190
140
90
V
= 8V
IN
85
80
75
70
65
60
55
50
V
= 12V
IN
V
= 19V
IN
F
= 554.3kHz
WS
V
= 12V
IN
40
0
5
10
LOAD CURRENT (A)
15
20
0
5
10
15
20
LOAD CURRENT (A)
Figure 4. PWM Mode Efficiency vs. Load Current
Figure 7. Switching Frequency vs. Load Current in RPM Mode
95
90
85
80
75
70
65
800
700
600
500
400
300
200
100
0
V
= 8V
IN
V
= 12V
IN
V
= 19V
IN
0
5
10
LOAD CURRENT (A)
15
20
0
5
10
15
OUTPUT POWER (W)
Figure 5. RPM Mode Efficiency vs. Load Current
Figure 8. PMON Voltage vs. Output Power
100
90
80
70
60
50
40
10000
1000
100
RPM
PWM
VID = 1.5V
VID = 1.2V
VID = 0.675V
V
= 12V
IN
10
10
0
5
10
15
20
100
1000
10000
LOAD CURRENT (A)
RT RESISTANCE (k;)
Figure 6. Efficiency vs. Load Current in All Modes
Figure 9. Switching Frequency vs. RT Resistance
Rev. 2 | Page 10 of 32 | www.onsemi.com
ADP3209
1.35
1.30
1.25
1.20
1.15
4
2
MEASURED LOAD LINE
OUTPUT VOLTAGE
+2%
–2%
SWITCH NODE
SPECIFIED LOAD LINE
INDUCTOR
CURRENT
3
1
LOW-SIDE
GATE DRIVE
CH1 5.00V
CH3 5.00A
CH2 5.00V
CH4 20.0mV~
M400ns
10.00%
A
CH3
4.00A
0
5
10
15
T
LOAD CURRENT (A)
Figure 13. DCM Waveforms, 3 A Load Current
Figure 10. Load Line Accuracy
35
30
25
20
15
10
5
4
2
OUTPUT VOLTAGE
SWITCH NODE
INDUCTOR CURRENT
LOW-SIDE GATE DRIVE
3
1
V
= 12V
IN
0
CH1 5.00V
CH3 5.00A
CH2 5.00V
CH4 20.0mV~
M400ns
10.00%
A
CH3
4.60A
0
2
4
6
T
VCC VOLTAGE (V)
Figure 11. VCC Current vs. VCC Voltage with Enable Low
Figure 14. CCM Waveforms, 6 A Load Current
4
OUTPUT VOLTAGE
PWRGD
SS
3
SWITCH NODE
OUTPUT VOLTAGE
EN
4
1
2
1
LOAD CURRENT
CH1 2.00V CH2 1.00V
CH3 2.00V CH4 1.00V
M400ꢀs
13.20%
A
CH1
800mV
CH1 100mV CH2 10.0V~
CH4 20.0mV
M40.0ꢀs
25.00%
A
CH1
120mV
T
T
Figure 12. Start-Up Waveforms
Figure 15. Load Transient, 2 A to 10 A, VIN = 19 V
Rev. 2 | Page 11 of 32 | www.onsemi.com
ADP3209
4
OUTPUT VOLTAGE
SWITCH NODE
4
OUTPUT VOLTAGE
2
1
LOAD CURRENT
CH1 100mV CH2 10.0V~
CH4 20.0mV
M2.00ꢀs
20.00%
A
CH1
120mV
M2.00ꢀs
10.00%
A
CH4
9.20mV
CH4 20.0mV~
T
T
Figure 16. Load Transient, 2 A to 10 A, VIN = 19 V
Figure 18. Output Ripple, 15 A Load, CX = 470 µF, CZ = 44 µF
4
OUTPUT VOLTAGE
VID 0
1
CH1 1.00V
M40.0ꢀs
20.00%
A
CH1
600mV
CH4 100mV
T
Figure 17. VID on the Fly, 1.25 V to 0.825 V
Rev. 2 | Page 12 of 32 | www.onsemi.com
ADP3209
THEORY OF OPERATION
The ADP3209 is a ramp-pulse-modulated (RPM) controller for
synchronous buck Intel GMCH core power supply. The internal
5-bit VID DAC conforms to the Intel IMVP-6+ specifications. The
ADP3209 is a stable, high performance architecture that includes
OPERATION MODES
The ADP3209 runs in RPM mode for the purpose of fast
transient response and high light load efficiency. During the
following transients, the ADP3209 runs in PWM mode:
•
•
High speed response at the lowest possible switching
frequency and minimal count of output decoupling capacitors
Minimized thermal switching losses due to lower frequency
operation
•
•
•
Soft start
Soft transient: the period of 100 µs following any VID change
Current overload
•
•
High accuracy load line regulation
High power conversion efficiency with a light load by
automatically switching to DCM operation
5V
VRMP
FLIP-FLOP
I
= A × I
RAMP
R
R
S
Q
BST
VCC
GATE DRIVER
RD
BST
DRVH
R
L
DRVH
SW
I
C
R
IN
SW
DCM
FLIP-FLOP
400ns
Q
1V
DRVL
LOAD
S
Q
DRVL
Q
R2
R1
RD
R2
R1
30mV
1V
VDC
+–
CSREF
CSFB
–
+
+
+
V
CS
CSCOMP
COMP
FBRTN
LLINE
FB
A
R
R
PH
CS
C
C
B
R
A
C
CS
C
FB
R
FB
Figure 19. RPM Mode Operation
Rev. 2 | Page 13 of 32 | www.onsemi.com
ADP3209
5V
BST
VCC
GATE DRIVER
BST
DRVH
I
= A × I
RAMP
R
R
FLIP-FLOP
DRVH
SW
R
L
I
CLOCK
OSCILLATOR
SW
IN
S
Q
DRVL
DRVL
RD
C
LOAD
R
A
VCC
D
VDC
+ –
0.2V
CSREF
CSFB
–
+
+
V
CS
RAMP
+
CSCOMP
COMP
FBRTN
LLINE
FB
A
R
R
CS
PH
R
C
C
A
B
C
CS
C
FB
R
FB
Figure 20. PWM Mode Operation
Rev. 2 | Page 14 of 32 | www.onsemi.com
ADP3209
current across a sense element, such as the low-side MOSFET.
The current sense amplifier can be configured several ways,
depending on system optimization objectives, and the current
information can be obtained by
Setting Switch Frequency
Master Clock Frequency in PWM Mode
When the ADP3209 runs in PWM, the clock frequency is set
by an external resistor connected from the RT pin to GND. The
frequency varies with the VID voltage: the lower the VID
voltage, the lower the clock frequency. The variation of clock
frequency with VID voltage maintains constant VCCGFX ripple and
improves power conversion efficiency at lower VID voltages.
Figure 9 shows the relationship between clock frequency and
VID voltage, parameterized by RT resistance.
•
•
•
Output inductor ESR sensing without the use of a
thermistor for the lowest cost
Output inductor ESR sensing with the use of a thermistor
that tracks inductor temperature to improve accuracy
Discrete resistor sensing for the highest accuracy
At the positive input of the CSA, the CSREF pin is connected to
the output voltage. At the negative input (that is, the CSFB pin of
the CSA), signals from the sensing element (in the case of inductor
DCR sensing, signals from the switch node side of the output
inductors) are connected with a resistor. The feedback resistor
between the CSCOMP and CSFB pins sets the gain of the current
sense amplifier, and a filter capacitor is placed in parallel with
this resistor. The current information is then given as the voltage
difference between the CSCOMP and CSREF pins. This signal
is used internally as a differential input for the current limit
comparator.
Switching Frequency in RPM Mode
When the ADP3209 operates in RPM mode, its switching
frequency is controlled by the ripple voltage on the COMP pin.
Each time the COMP pin voltage exceeds the RPM pin voltage
threshold level determined by the VID voltage and the external
resistor connected between RPM and VRPM, an internal ramp
signal is started and DRVH is driven high. The slew rate of the
internal ramp is programmed by the current entering the
RAMP pin. One-third of the RAMP current charges an internal
ramp capacitor (5 pF typical) and creates a ramp. When the
internal ramp signal intercepts the COMP voltage, the DRVH
pin is reset low.
An additional resistor divider connected between the CSCOMP
and CSREF pins with the midpoint connected to the LLINE pin
can be used to set the load line required by the GMCH specifi-
cation. The current information to set the load line is then given
as the voltage difference between the LLINE and CSREF pins. This
configuration allows the load line slope to be set independent
from the current limit threshold. If the current limit threshold and
load line do not have to be set independently, the resistor divider
between the CSCOMP and CSREF pins can be omitted and the
CSCOMP pin can be connected directly to LLINE. To disable
voltage positioning entirely (that is, to set no load line), LLINE
should be tied to CSREF.
In continuous current mode, the switching frequency of RPM
operation is almost constant. While in discontinuous current
conduction mode, the switching frequency is reduced as a
function of the load current.
DIFFERENTIAL SENSING OF OUTPUT ꢀOLTAGE
The ADP3209 combines differential sensing with a high accuracy
VID DAC, referenced by a precision band gap source and a low
offset error amplifier, to meet the rigorous accuracy requirement
of the Intel IMVP-6+ specification. In steady-state mode, the
combination of the VID DAC and error amplifier maintain the
output voltage for a worst-case scenario within 8 mV of the
full operating output voltage and temperature range.
To provide the best accuracy for current sensing, the CSA has a
low offset input voltage and the sensing gain is set by an external
resistor ratio.
The VCCGFX output voltage is sensed between the FB and FBRTN
pins. FB should be connected through a resistor to the positive
regulation point—the VCC remote sensing pin of the GMCH.
FBRTN should be connected directly to the negative remote
sensing point—the VSS sensing point of the GMCH. The internal
VID DAC and precision voltage reference are referenced to
FBRTN and have a typical current of 200 µA for guaranteed
accurate remote sensing.
ACTIꢀE IMPEDANCE CONTROL MODE
To control the dynamic output voltage droop as a function of
the output current, the signal that is proportional to the total
output current, converted from the voltage difference between
LLINE and CSREF, can be scaled to be equal to the required
droop voltage. This droop voltage is calculated by multiplying
the droop impedance of the regulator by the output current.
This value is used as the control voltage of the PWM regulator.
The droop voltage is subtracted from the DAC reference output
voltage, and the resulting voltage is used as the voltage positioning
setpoint. The arrangement results in an enhanced feedforward
response.
OUTPUT CURRENT SENSING
The ADP3209 includes a dedicated current sense amplifier (CSA)
to monitor the total output current of the converter for proper
voltage positioning vs. load current and for overcurrent detection.
Sensing the current delivered to the load is an inherently more
accurate method than detecting peak current or sampling the
Rev. 2 | Page 15 of 32 | www.onsemi.com
ADP3209
In VCC UVLO or shutdown mode, the SS pin is held at zero
potential. When VCC ramps to a value greater than the upper
UVLO threshold while EN is asserted high, the ADP3209 enables
the internal bias and starts a reset cycle of about 50 µs to 60 µs.
When the initial reset is complete, the chip signals to ramp up the SS
voltage. During soft start, the external SS capacitor is charged by an
internal 8 µA current source. The VCCGFX voltage follows the ramping
SS voltage up to the VID code. While the VCCGFX is regulated at the
VID code voltage, the SS capacitor continues to rise. When the SS
pin voltage reaches 1.7 V, the ADP3209 completes its soft start,
PWRGD asserts high, and the chip switches to normal operation.
ꢀOLTAGE CONTROL MODE
A high-gain bandwidth error amplifier is used for the voltage
mode control loop. The noninverting input voltage is set via the
5-bit VID DAC. The VID codes are listed in Table 4. The
noninverting input voltage is offset by the droop voltage as a
function of current, commonly known as active voltage
positioning. The output of the error amplifier is the COMP pin,
which sets the termination voltage of the internal PWM ramps.
At the negative input, the FB pin is tied to the output sense
location using RB, a resistor for sensing and controlling the
output voltage at the remote sensing point. The main loop
compensation is incorporated in the feedback network
connected between the FB and COMP pins.
V5_S
GFXCORE_EN
POWER-GOOD MONITORING
2.9V
1.7V
The power-good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output that
can be pulled up through an external resistor to a voltage rail—
not necessarily the same VCC voltage rail that is running the
controller. A logic high level indicates that the output voltage is
within the voltage limits defined by a range around the VID
voltage setting. PWRGD goes low when the output voltage is
outside of this range.
V
V
SS
CCGFX
PGDELAY
PWRGD
Following the GMCH specification, the PWRGD range is
defined to be 300 mV less than and 200 mV greater than the
actual VID DAC output voltage. To prevent a false alarm, the
power-good circuit is masked during any VID change and
during soft start. The duration of the PWRGD mask is set to
approximately 100 µs by an internal timer. In addition, for a
VID change from high to low, there is an additional period of
PWRGD masking before the voltage of the ST pin drops within
200 mV of the new lower VID DAC output voltage, as shown in
Figure 21.
Figure 22. Power-Up Sequence of ADP3209
If EN is taken low or VCC drops below the lower VCC UVLO
threshold, the SS capacitor is reset to ground to prepare the chip
for a subsequent soft start cycle.
ꢀID CHANGE AND SOFT TRANSIENT
When a VID input changes, the ADP3209 detects the change but
ignores new code for a minimum of 400 ns. This delay is required to
prevent the device from reacting to digital signal skew while the 5-
bit VID input code is in transition. Additionally, the VID change
triggers a PWRGD masking timer to prevent a PWRGD failure.
Each VID change resets and retriggers the internal PWRGD
masking timer.
VID SIGNAL
CHANGE
ST PIN
VOLTAGE
The ADP3209 provides a soft transient function to reduce inrush
current during VID transitions. Reducing the inrush current helps
decrease the acoustic noise generated by the MLCC input capacitors
and inductors.
200mV
PWRGD
MASK
100ꢀs
100ꢀs
The soft transient feature is implemented with an ST buffer
amplifier that outputs constant sink or source current on the ST pin
that is connected to an external capacitor. The capacitor is used to
program the slew rate of VCCGFX voltage during a VID voltage
transient. During steady-state operation, the reference inputs of the
voltage error amplifier and the ST amplifier are connected to the
VID DAC output. Consequently, the ST voltage is a buffered version
of VID DAC output. When a VID change triggers a soft transition,
the reference input of the voltage error amplifier switches from the
DAC output to the ST output while the input of the ST amplifier
Figure 21. PWRGD Masking for VID Change
POWER-UP SEQUENCE AND SOFT START
The power-on ramp-up time of the output voltage is set with a
capacitor tied from the SS pin to GND. The capacitance on the SS
pin also determines the current limit latch-off time, as explained in
the Current Limit, Short-Circuit, and
Latch-Off Protection section. The power-up sequence, including the
soft start is illustrated in Figure 22.
Rev. 2 | Page 16 of 32 | www.onsemi.com
ADP3209
remains connected to the DAC. The ST buffer input recognizes the
almost instantaneous VID voltage change and tries to track it.
However, tracking is not instantaneous because the slew rate of the
buffer is limited by the source and sink current capabilities (7.5 µA
and 2.5 µA, respectively) of the ST output. Therefore, the VCCGFX
voltage slew rate is controlled. When the transient period is
complete, the reference input of the voltage amplifier reverts to the
VID DAC output to improve accuracy.
The latch-off function can be reset either by removing and
reapplying VCC or by briefly pulling the EN pin low. To disable
the current limit latch-off function, an external resistor pulls the
SS pin to the VCC voltage to override the 2 µA sink current.
This pull-up prevents the SS capacitor from discharging to the
1.65 V latch-off threshold.
During startup, when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot extend below ground. This
secondary current limit clamp controls the minimum internal
COMP voltage to the PWM comparators to 1.5 V. This limits
the voltage drop across the low-side MOSFETs through the
current balance circuitry.
Charging/discharging the external capacitor on the ST pin programs
the voltage slew rate of the ST pin and consequently of the VCCGFX
output.
CURRENT LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
Light Load RPM DCM Operation
The ADP3209 has an adjustable current limit set by the RCLIM
resistor. This resistor is connected from the CLIM pin to GND,
and the CLIM pin outputs a 10 μA current. The voltage created
by 10 μA through RCLIM is divided by 10 and then level shifted
and connected in series with CSCOMP to form a current limit
threshold. The current sense amplifier sets an output voltage
between CSREF and CSCOMP that is proportional to the output
current. When the difference in voltage between CSREF and
CSCOMP is greater than the current limit threshold, there is a
current overload.
The ADP3209 operates in RPM mode. With higher loads, the
ADP3209 operates in continuous conduction mode (CCM),
and the upper and lower MOSFETs run synchronously and in
complementary phase. See Figure 24 for the typical waveforms
of the ADP3209 running in CCM with a 7 A load current.
OUTPUT VOLTAGE 20mV/DIV
4
INDUCTOR CURRENT 5A/DIV
Normally, the ADP3209 operates in RPM mode. During a
current overload, the ADP3209 switches to PWM mode.
SWITCH NODE 5V/DIV
2
With low impedance loads, the ADP3209 operates in a constant
current mode to ensure that the external MOSFETs and inductor
function properly and to protect the GPU. With a low constant
impedance load, the output voltage decreases to supply only the
set current limit. If the output voltage drops below the power-
good limit, the PWRGD signal transitions. After the PWRGD
single transitions, the SS capacitor begins to discharge with a
2 µA internal constant current sink. When the SS capacitor has
discharged voltage from 2.9 V to 1.65 V, the ADP3209 latches
off. The current limit latch-off delay time is therefore set by the
SS pin capacitance. Figure 23 shows how the ADP3209 reacts to
a current overload.
LOW-SIDE GATE DRIVE 5V/DIV
3
1
1ms/DIV
Figure 24. Single-Phase Waveforms in CCM
With lighter loads, the ADP3209 enters discontinuous con-
duction mode (DCM). Figure 25 shows a typical single-phase
buck with one upper FET, one lower FET, an output inductor,
an output capacitor, and a load resistor. Figure 26 shows the
path of the inductor current with the upper FET on and the
lower FET off. In Figure 27 the high-side FET is off and the low-
side FET is on. In CCM, if one FET is on, its complementary FET
must be off; however, in DCM, both high- and low-side FETs are
off and no current flows into the inductor (see Figure 28). Figure
29 shows the inductor current and switch node voltage in
DCM.
OUTPUT VOLTAGE 1V/DIV
4
PWRGD 2V/DIV
1
In DCM with a light load, the ADP3209 monitors the switch
node voltage to determine when to turn off the low-side FET.
Figure 30 shows a typical waveform in DCM with a 1 A load
current. Between t1 and t2, the inductor current ramps down. The
current flows through the source drain of the low-side FET and
creates a voltage drop across the FET with a slightly negative
switch node. As the inductor current ramps down to 0 A, the
SS PIN 2V/DIV
3
SWITCH NODE 10V/DIV
2
1ms/DIV
CURRENT LIMIT
APPLIED
LATCHED
OFF
Figure 23. Current Overload
Rev. 2 | Page 17 of 32 | www.onsemi.com
ADP3209
switch voltage approaches 0 V, as seen just before t2. When the
switch voltage is approximately −6 mV, the low-side FET is
turned off.
INDUCTOR
CURRENT
Figure 29 shows a small, dampened ringing at t2. This is caused
by the LC created from capacitance on the switch node,
including the CDS of the FETs and the output inductor. This
ringing is normal.
The ADP3209 automatically goes into DCM with a light load.
Figure 30 shows the typical DCM waveform of the ADP3209
with a 1 A load current. As the load increases, the ADP3209
enters into CCM. In DCM, frequency decreases with load
current, and switching frequency is a function of the inductor,
load current, input voltage, and output voltage.
SWITCH
NODE
VOLTAGE
Q1
DRVH
OUTPUT
VOLTAGE
INPUT
VOLTAGE
SWITCH
NODE
t0 t1
t2
t3 t4
L
Figure 29. Inductor Current and Switch Node in DCM
Q2
C
LOAD
DRVL
4
Figure 25. Buck Topology
OUTPUT VOLTAGE
20mV/DIV
SWITCH NODE 5V/DIV
ON
2
L
INDUCTOR CURRENT
5A/DIV
OFF
C
LOAD
3
1
Figure 26. Buck Topology Inductor Current During t0 and t1
LOW-SIDE GATE DRIVE 5V/DIV
2ꢀs/DIV
Figure 30. Single-Phase Waveforms in DCM with 1 A Load Current
OFF
L
OUTPUT CROWBAR
To protect the load and output components of the supply, the
DRVL output is driven high (turning the low-side MOSFETs on)
and DRVH is driven low (turning the high-side MOSFETs off)
when the output voltage exceeds the GMCH OVP threshold.
C
LOAD
ON
Figure 27. Buck Topology Inductor Current During t1 and t2
Turning on the low-side MOSFETs forces the output capacitor
to discharge and the current to reverse due to current build up
in the inductors. If the output overvoltage is due to a drain-
source short of the high-side MOSFET, turning on the low-side
MOSFET results in a crowbar across the input voltage rail. The
crowbar action blows the fuse of the input rail, breaking the
circuit and thus protecting the GMCH chipset from destruction.
OFF
L
C
LOAD
OFF
Figure 28. Buck Topology Inductor Current During t2 and t3
When the OVP feature is triggered, the ADP3209 is latched off.
The latch-off function can be reset by removing and reapplying
VCC to the ADP3209 or by briefly pulling the EN pin low.
REꢀERSE ꢀOLTAGE PROTECTION
Very large reverse current in inductors can cause negative
V
CCGFX voltage, which is harmful to the chipset and other output
components. The ADP3209 provides a reverse voltage
Rev. 2 | Page 18 of 32 | www.onsemi.com
ADP3209
protection (RVP) function without additional system cost. The
VCCGFX voltage is monitored through the CSREF pin. When the
CSREF pin voltage drops to less than −300 mV, the ADP3209
triggers the RVP function by setting both DRVH and DRVL
low, thus turning off all MOSFETs. The reverse inductor
currents can be quickly reset to 0 by discharging the built-up
energy in the inductor into the input dc voltage source via the
forward-biased body diode of the high-side MOSFETs. The
RVP function is terminated when the CSREF pin voltage
returns to greater than −100 mV.
low, shorts the capacitors of the SS and PGDELAY pins to
ground, and drives PWRGD to low.
The user must adhere to proper power-supply sequencing during
startup and shutdown of the ADP3209. All input pins must be
at ground prior to removing or applying VCC, and all output
pins should be left in high impedance state while VCC is off.
POWER MONITOR FUNCTION
The ADP3209 includes a power monitor function. The PMON
pin is an open-drain MOSFET. A pull-up resistor is required on
PMON. PMON switches at a duty cycle proportional to the load
current. The full-scale duty cycle of PMON at the maximum load
current is set by a resistor, RPMONFS, connected from PMONFS to
GND. RPMONFS also sets the switching frequency of the PMON
open-drain transistor.
Connecting an RC to PMON will average the PMON voltage. If
the PMON pull-up resistor is connected to a dc voltage, the average
PMON voltage is proportional to the load current. Figure 32 shows
the PMON function used to monitor load current.
Sometimes the crowbar feature inadvertently results in negative
V
CCGFX voltage because turning on the low-side MOSFETs
results in a very large reverse inductor current. To prevent
damage to the chipset caused from negative voltage, the
ADP3209 maintains its RVP monitoring function even after
OVP latch-off. During OVP latch-off, if the CSREF pin voltage
drops to less than −300 mV, the low-side MOSFETs is turned
off by setting DRVL low. DRVL will be set high again when the
CSREF voltage recovers to greater than −100 mV.
Figure 31 shows the reverse voltage protection function of the
ADP3209. The CSREF pin is disconnected from the output
voltage and pulled negative. As the CSREF pin drops to less
than −300 mV, the low-side and high-side FETs turn off.
DC
VOLTAGE
ADP3209
R
PULL UP
CURRENT
SIGNAL
R
FILTER
PMON
6
7
PMON
PWM
C
PMONFS
FILTER
R
PMONFS
3
CSREF
Figure 32. PMON Current Monitor Configuration
PWRGD
Because the output voltage of the ADP3209 can vary in the
same application, the average PMON voltage is proportional to
the load current, but not to the output power. Connecting the
PMON pull-up resistor to VCCGFX results in a PMON average
voltage that is proportional to the output power.
2
DRVH
4
DRVL
M2.00ꢀs
1
CH1 5.00V
CH3 1.00V
CH2 5.00V
CH4 20.0V
A
CH3
580mV
V
CCGFX
Figure 31. ADP3209 RVP Function
ADP3209
R
PULL UP
POWER
SIGNAL
OUTPUT ENABLE AND UꢀLO
R
FILTER
PMON
6
7
For the ADP3209 to begin switching, the VCC supply voltage to
the controller must be greater than the VCCOK threshold and the
EN pin must be driven high. If the VCC voltage is less than the
PMON
PWM
C
PMONFS
FILTER
R
PMONFS
V
CCUVLO threshold or the EN pin is logic low, the ADP3209 shuts
off. In shutdown mode, the controller holds DRVH and DRVL
Figure 33. PMON Power Monitor Configuration
Rev. 2 | Page 19 of 32 | www.onsemi.com
ADP3209
Table 4. VID Codes
Nominal
Enable ꢀID4 ꢀID3 ꢀID2 ꢀID1 ꢀID0 ꢀCCGFX (ꢀ)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
0.750
0.725
0.700
0.675
0.650
0.625
0.600
0.575
0.550
0.525
0.500
0.400
0.000
Rev. 2 | Page 20 of 32 | www.onsemi.com
ADP3209
0 3 5 4 - 0 6 3 7
4 D V I
V I D 3
4 I D V
3 I V D
2 I D V
1 I V D
0 I D V
N E
T R
M P R
V I D 2
V I D 1
M P R V
P M A R
B F S C
V I D 0
N O V R _
F E R S C
P M O C S C
E N I L L
D G R W P
Q E R F R A V
Figure 34. Typical Application Circuit
Rev. 2 | Page 21 of 32 | www.onsemi.com
ADP3209
APPLICATION INFORMATION
The design parameters for a typical IMVP-6+-compliant GPU
core VR application are as follows:
SETTING THE SWITCHING FREQUENCY FOR
RPM OPERATION
During the RPM operation, the ADP3209 runs in pseudoconstant
frequency if the load current is high enough for continuous current
mode. While in DCM, the switching frequency is reduced with
the load current in a linear manner. To save power with light
loads, lower switching frequency is usually preferred during
RPM operation. However, the VCCGFX ripple specification of
IMVP-6+ sets a limitation for the lowest switching frequency.
Therefore, depending on the inductor and output capacitors,
the switching frequency in RPM can be equal to, greater than,
or less than its counterpart in PWM.
•
•
•
•
•
•
•
Maximum input voltage (VINMAX) = 19 V
Minimum input voltage (VINMIN) = 8 V
Output voltage by VID setting (VVID) = 1.25 V
Maximum output current (IO) = 15 A
Droop resistance (RO) = 5.1 mΩ
Nominal output voltage at 15 A load (VOFL) = 1.174 V
Static output voltage drop from no load to full load
(∆V) = VONL − VOFL = 1.25 V − 1.174 V = 76 mV
Maximum output current step (∆IO) = 8 A
Number of phases (n) = 1
Switching frequency (fSW) = 390 kHz
Duty cycle at maximum input voltage (DMAX) = 0.15 V
Duty cycle at minimum input voltage (DMIN) = 0.062 V
•
•
•
•
•
A resistor between the VRPM and RPM pins sets the
pseudoconstant frequency as follows:
AR ×(1− D)×VVID
RR ×CR × fSW
4×RT
(VVID +1.0 V)
RRPM
=
×
(2)
SETTING THE CLOCK FREQUENCY FOR PWM
where:
In PWM operation, the ADP3209 uses a fixed-frequency control
architecture. The frequency is set by an external timing resistor
(RT). The clock frequency determines the switching frequency,
which relates directly to the switching losses and the sizes of the
inductors and input and output capacitors. For example, a clock
frequency of 300 kHz sets the switching frequency to 300 kHz.
This selection represents the trade-off between the switching
losses and the minimum sizes of the output filter components.
To achieve a 300 kHz oscillator frequency at a VID voltage of
1.2 V, RT must be 452 kΩ. Alternatively, the value for RT can
be calculated by using the following equation:
AR is the internal ramp amplifier gain.
CR is the internal ramp capacitor value.
RR is an external resistor on the RAMP pin to set the internal
ramp magnitude (see the Ramp Resistor Selection section for
information about the design of RR resistance).
If RR = 340 kΩ, the following resistance results in 390 kHz
switching frequency in RPM operation.
4 × 357 kΩ
1.174 V +1.0 V 390 kΩ×5 pF×390 kHz
0.2×(1 − 0.062)×1.174
RRPM
=
×
= 218 kΩ
VVID +1.0 V
2× fSW × 7.2 pF
SOFT START AND CURRENT LIMIT
LATCH-OFF DELAY TIMES
RT =
−35 kΩ
(1)
The soft start and current limit latch-off delay functions share
the SS pin; consequently, these parameters must be considered
together. First, set CSS for the soft start ramp. This ramp is
generated with an 8 µA internal current source. The value for
CSS can be calculated as
where:
7.2 pF and 35 kΩ are internal IC component values.
VID is the VID voltage in volts.
SW is the switching frequency in hertz.
V
f
8 μA×tSS
For good initial accuracy and frequency stability, it is
recommended to use a 1% resistor.
CSS
=
(3)
VVID
With VARFREQ pulled above 4 V, the ADP3209 operates with a
constant switching frequency. The switching frequency does not
change with VID voltage, input voltage, or load current. In
addition, the DCM operation at light load is disabled, so the
ADP3209 operates in CCM. The value of RT can be calculated
by using the following equation:
where tSS is the desired soft start time and is recommended in
IMVP-6+ to be less than 3 ms.
Therefore, assuming a desired soft start time of 2 ms, CSS is 13.3 nF,
and the closest standard capacitance is 12 nF.
After CSS is set, the current limit latch-off time can be calculated
by using the following equation:
1.6 V
RT =
−35 kΩ
fSW × 7.2 pF
1.2 V ×CSS
tDELAY
=
(4)
2μA
where CSS is 7.2 ms.
Rev. 2 | Page 22 of 32 | www.onsemi.com
ADP3209
Selecting a Standard Inductor
INDUCTOR SELECTION
After the inductance and DCR are known, select a standard
inductor that best meets the overall design goals. It is also
important to specify the inductance and DCR tolerance to
maintain the accuracy of the system. Using 20% tolerance for
the inductance and 15% for the DCR at room temperature are
reasonable values that most manufacturers can meet.
The choice of inductance determines the ripple current of the
inductor. Less inductance results in more ripple current, which
increases the output ripple voltage and the conduction losses in
the MOSFETs. However, this allows the use of smaller-size
inductors, and for a specified peak-to-peak transient deviation,
it allows less total output capacitance. Conversely, a higher
inductance results in lower ripple current and reduced conduction
losses, but it requires larger-size inductors and more output
capacitance for the same peak-to-peak transient deviation. For
a buck converter, the practical value for peak-to-peak inductor
ripple current is less than 50% of the maximum dc current of
that inductor. Equation 5 shows the relationship between the
inductance, oscillator frequency, and peak-to-peak ripple
current. Equation 6 can be used to determine the minimum
inductance based on a given output ripple voltage.
Power Inductor Manufacturers
The following companies provide surface-mount power inductors
optimized for high power applications upon request.
•
•
•
•
Vishay Dale Electronics, Inc.
(605) 665-9301
Panasonic
(714) 373-7334
Sumida Electric Company
(847) 545-6700
VVID ×(1− DMIN
)
IR
=
(5)
(6)
NEC Tokin Corporation
(510) 324-4110
fSW ×L
V
VID ×RO ×(1− DMIN
)
L ≥
fSW ×VRIPPLE
Output Droop Resistance
The design requires that the regulator output voltage measured at
the chipset pins decreases when the output current increases. The
specified voltage drop corresponds to the droop resistance (RO).
In this example, RO is assumed to be the ESR of the output
capacitance, which results in an optimal transient response. Solving
Equation 6 for a 16 mV peak-to-peak output ripple voltage yields
The output current is measured by low-pass filtering the voltage
across the inductor or current sense resistor. The filter is
implemented by the CS amplifier that is configured with RPH,
RCS, and CCS. The output resistance of the regulator is set by the
following equations:
1.174 V × 5.1 mΩ × (1− 0.062)
L ≥
= 901 nH
390 kHz ×16 mV
If the resultant ripple voltage is less than the initially selected
value, the inductor can be changed to a smaller value until the
ripple value is met. This iteration allows optimal transient
response and minimum output decoupling. In this example, the
iteration showed that a 560 nH inductor was sufficient to
achieve a good ripple.
RCS
RO
=
×RSENSE
(7)
(8)
RPH
L
CCS
=
R
SENSE × RCS
The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 560 nH inductor is a
good choice for a starting point, and it provides a calculated
ripple current of 6.6 A. The inductor should not saturate at the
peak current of 18.3 A, and it should be able to handle the sum
of the power dissipation caused by the winding’s average current
(15 A) plus the ac core loss.
where RSENSE is the DCR of the output inductors.
Either RCS or RPH can be chosen for added flexibility. Due to the
current drive ability of the CSCOMP pin, the RCS resistance
should be greater than 100 kΩ. For example, initially select RCS
to be equal to 200 kΩ, and then use Equation 8 to solve for CCS:
560 nH
1.3 mΩ×200 kΩ
CCS
=
= 2.2 nF
Another important factor in the inductor design is the DCR,
which is used for measuring the inductor current. Too large of a
DCR causes excessive power losses, whereas too small of a value
leads to increased measurement error. For this example, an
inductor with a DCR of 1.3 mΩ is used.
If CCS is not a standard capacitance, RCS can be tuned. In this
case, the required CCS is a standard value and no tuning is
required. For best accuracy, CCS should be a 5% NPO capacitor.
Next, solve for RPH by rearranging Equation 7 as follows:
Rev. 2 | Page 23 of 32 | www.onsemi.com
ADP3209
1.3 mΩ
5.1mΩ
3. Find the relative value of RCS required for each of the two
temperatures. The relative value of RCS is based on the
percentage of change needed, which is initially assumed to
be 0.39%/°C in this example. The relative values are called
r1 (r1 is 1/(1+ TC × (T1 − 25))) and r2 (r2 is 1/(1 + TC ×
(T2 − 25))), where TC is 0.0039, T1 is 50°C, and T2 is 90°C.
4. Compute the relative values for rCS1, rCS2, and rTH by using
the following equations:
RPH
≥
×200 kΩ = 51.0 kΩ
The standard 1% resistor for RPH is 51.1 kΩ.
Inductor DCR Temperature Correction
If the DCR of the inductor is used as a sense element and
copper wire is the source of the DCR, the temperature changes
associated with the inductor’s winding must be compensated
for. Fortunately, copper has a well-known temperature
coefficient (TC) of 0.39%/°C.
(A − B)×r1 ×r2 − A×(1− B)×r2 + B×(1− A)×r1
rCS2
rCS1
=
=
(9)
A×(1− B)×r1 − B×(1− A)×r2 −(A − B)
(1− A)
If RCS is designed to have an opposite but equal percentage of
change in resistance, it cancels the temperature variation of the
inductor’s DCR. Due to the nonlinear nature of NTC thermistors,
series resistors RCS1 and RCS2 (see Figure 35) are needed to linearize
the NTC and produce the desired temperature coefficient tracking.
1
A
−
1−rCS2 r1 −rCS2
1
rTH
=
1
1
−
1−rCS2 rCS1
TO
SWITCH
NODE
PLACE AS CLOSE AS POSSIBLE
TO INDUCTOR OR LOW-SIDE MOSFET
5. Calculate RTH = rTH × RCS, and then select a thermistor of
TO
R
TH
V
CCGFX
the closest value available. In addition, compute a scaling
factor k based on the ratio of the actual thermistor value
used relative to the computed one:
R
PH
SENSE
ADP3209
CSCOMP
R
R
CS2
CS1
10
RTH(ACTUAL)
C
C
CS2
CS1
k =
(10)
CSFB
12
RTH(CALCULATED)
KEEP THIS PATH
AS SHORT AS POSSIBLE
AND AWAY FROM SWITCH
NODE LINES
6. Calculate values for RCS1 and RCS2 by using the following
equations:
CSREF
11
RCS1 = RCS ×k ×rCS1
(11)
Figure 35. Temperature-Compensation Circuit Values
RCS2 = RCS ×((1−k)+(k×rCS2 ))
The following procedure and expressions yield values for
RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given
RCS value.
For example, if a thermistor value of 100 kΩ is selected in Step 1,
an available 0603-size thermistor with a value close to RCS is the
Vishay NTHS0603N04 NTC thermistor, which has resistance
values of A = 0.3359 and B = 0.0771. Using the equations in
Step 4, rCS1 is 0.359, rCS2 is 0.729, and rTH is 1.094. Solving for rTH
yields 219 kΩ, so a thermistor of 220 kΩ would be a reasonable
selection, making k equal to 1.005. Finally, RCS1 and RCS2 are
found to be 72.2 kΩ and 146 kΩ. Choosing the closest 1%
resistor values yields a choice of 71.5 kΩ and 147 kΩ.
1. Select an NTC to be used based on its type and value.
Because the value needed is not yet determined, start with
a thermistor with a value close to RCS and an NTC with an
initial tolerance of better than 5%.
2. Find the relative resistance value of the NTC at two
temperatures. The appropriate temperatures will depend
on the type of NTC, but 50°C and 90°C have been shown
to work well for most types of NTCs. The resistance values
are called A (A is RTH(50°C)/RTH(25°C)) and B (B is
RTH(90°C)/RTH(25°C)). Note that the relative value of the
NTC is always 1 at 25°C.
Rev. 2 | Page 24 of 32 | www.onsemi.com
ADP3209
For example, if two pieces of 22 µF, 0805-size MLC capacitors
(CZ = 44 µF) are used during a VID voltage change, the VCCGFX
change is 220 mV in 22 µs with a setting error of 10 mV. If k = 3.1,
solving for the bulk capacitance yields
COUT SELECTION
The required output decoupling for processors and platforms is
typically recommended by Intel. For systems containing both
bulk and ceramic capacitors, however, the following guidelines
can be a helpful supplement.
C
D
S
T
D
T
560 nH × 8 A
Select the number of ceramics and determine the total ceramic
capacitance (CZ). This is based on the number and type of
capacitors used. Keep in mind that the best location to place
ceramic capacitors is inside the socket; however, the physical
limit is twenty 0805-size pieces inside the socket. Additional
ceramic capacitors can be placed along the outer edge of the
socket. A combined ceramic capacitor value of 40 µF to 50 µF
is recommended and is usually composed of multiple 10 µF or
22 µF capacitors.
D
T
CX
CX
≥
MIN )
− 44 μF = 256 µF
(
(
D C
S
T
T
U
T
10 mV
8 A
D
D
5.1 mΩ+
×1.174 V
T
T
U
D
D
E
E
560 nH × 220 mV
3.12 ×(5.1 mΩ)2 ×1.174 V
≤
)
×
MAX
C
S2
T
U
C
D
S
T
22 μs ×1.174 V × 3.1× 5.1 mΩ
220 mV × 560 nH
D
D
E
1+
−1 − 44 μF
D
T
T
D
E
T
U
Ensure that the total amount of bulk capacitance (CX) is within
its limits. The upper limit is dependent on the VID on-the-fly
output voltage stepping (voltage step, VV, in time, tV, with error
of VERR); the lower limit is based on meeting the critical capacitance
for load release at a given maximum load step, ∆IO. The current
version of the IMVP-6+ specification allows a maximum VCCGFX
overshoot (VOSMAX) of 10 mV more than the VID voltage for a
step-off load current.
= 992 µF
Using two 220 µF Panasonic SP capacitors with a typical ESR of
7 mΩ each yields CX = 440 µF and RX = 3.5 mΩ.
Ensure that the ESL of the bulk capacitors (LX) is low enough to
limit the high frequency ringing during a load change. This is
tested using
LX ≤ CZ × RO 2 × Q2
(14)
C
D
S
T
LX ≤ 44 μF ×
(
5.1mΩ
)
2 ×2 = 2.3 nH
D
D
D
D
E
T
Z T
T
L × ∆IO
CX
≥
≤
−C
(12)
(
MIN )
C
D
D
E
S
T
T
U
VOSMAX
∆IO
RO +
×VVID
where:
T
U
Q is limited to the square root of 2 to ensure a critically damped
system.
LX is about 450 pH for the two SP capacitors, which is low
enough to avoid ringing during a load change. If the LX of the
chosen bulk capacitor bank is too large, the number of ceramic
capacitors may need to be increased to prevent excessive
ringing.
C
D
E
S2
T
U
C
S
T
VV
VVID k×RO
L
D
D
CX(MAX)
×
×
1+ tv
×
−1 −CZ
D
D
E
T
k2 ×RO2 VVID
VV
L
T
T
U
C
D
D
E
S
T
T
U
VERR
VV
k = −ln
where
(13)
For this multimode control technique, an all ceramic capacitor
design can be used if the conditions of Equations 12, 13, and 14
are satisfied.
To meet the conditions of these expressions and the transient
response, the ESR of the bulk capacitor bank (RX) should be less
than two times the droop resistance, RO. If the CX(MIN) is greater
than CX(MAX), the system does not meet the VID on-the-fly
specifications and may require less inductance. In addition, the
switching frequency may have to be increased to maintain the
output ripple.
Rev. 2 | Page 25 of 32 | www.onsemi.com
ADP3209
voltage that are being switched. Basing the switching speed on
the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET:
POWER MOSFETS
For typical 15 A per phase applications, the N-channel power
MOSFETs are selected for one high-side switch and one low-
side switch. The main selection parameters for the power
MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). Because the
voltage of the gate driver is 5 V, logic-level threshold MOSFETs
must be used.
V
DC ×IO
nMF
PS(MF) = 2× fSW
×
×RG ×nMF ×CISS
(16)
where:
MF is the total number of main MOSFETs.
RG is the total gate resistance.
ISS is the input capacitance of the main MOSFET.
The maximum output current, IO, determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. With
conduction losses being dominant, the following expression
shows the total power that is dissipated in each synchronous
MOSFET in terms of the ripple current per phase (IR) and the
average total output current (IO):
n
C
The most effective way to reduce switching loss is to use lower
gate capacitance devices.
S2
C
D
D
S
T
T
U
F
G
2 V
W
The conduction loss of the main MOSFET is given by the
following equation:
C
D
D
E
IO
nSF
IR
1
T
PSF = (1− D)×
+
×
×RDS(SF)
(15)
T
12 nSF
G
H
W
X
U
E
C
D
D
E
S2
C
D
D
S
T
T
U
F
G
2 V
W
IO
nMF
IR
1
T
PC(MF) = D×
+
×
×RDS(MF)
(17)
where:
T
12 nMF
G
H
W
X
U
E
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
IR is the inductor peak-to-peak ripple current and is
approximately
where RDS(MF) is the on resistance of the MOSFET.
Typically, a user wants the highest speed (low CISS) device for a
main MOSFET, but such a device usually has higher on resistance.
Therefore, the user must select a device that meets the total power
dissipation (about 0.8 W to 1.0 W for an 8-lead SOIC) when
combining the switching and conduction losses.
(1− D)×VOUT
IR
=
L× fSW
Knowing the maximum output current and the maximum
allowed power dissipation, the user can calculate the required
DS(ON) for the MOSFET. For an 8-lead SOIC or 8-lead SOIC-
For example, an IRF7821 device can be selected as the main
MOSFET (one in total; that is, nMF = 1), with approximately
CISS = 1010 pF (maximum) and RDS(MF) = 18 mΩ (maximum at
TJ = 120°C), and an IR7832 device can be selected as the
synchronous MOSFET (two in total; that is, nSF = 2), with
R
compatible MOSFET, the junction-to-ambient (PCB) thermal
impedance is 50°C/W. In the worst case, the PCB temperature is
70°C to 80°C during heavy load operation of the notebook, and a
safe limit for PSF is about 0.8 W to 1.0 W at 120°C junction temper-
ature. Therefore, for this example (15 A maximum), the RDS(SF)
per MOSFET is less than 18.8 mΩ for the low-side MOSFET.
This RDS(SF) is also at a junction temperature of about 120°C;
therefore, the RDS(SF) per MOSFET should be less than 13.3 mΩ
at room temperature, or 18.8 mΩ at high temperature.
RDS(SF) = 6.7 mΩ (maximum at TJ = 120°C). Solving for the
power dissipation per MOSFET at IO = 15 A and IR = 5.0 A
yields 178 mW for each synchronous MOSFET and 446 mW
for each main MOSFET. A third synchronous MOSFET is an
option to further increase the conversion efficiency and reduce
thermal stress.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input must be small (less than 10% is recommended)
to prevent accidentally turning on the synchronous MOSFETs
when the switch node goes high.
Finally, consider the power dissipation in the driver. This is best
described in terms of the QG for the MOSFETs and is given by
the following equation:
f
F
V
SW
PDRV
=
×
(
n
MF ×QGMF +nSF ×QGSF
)
+ ICC ×VCC
(18)
G
W
2×n
H
X
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction losses and
switching losses. Switching loss is related to the time for the
main MOSFET to turn on and off and to the current and
where QGMF is the total gate charge for each main MOSFET, and
GSF is the total gate charge for each synchronous MOSFET.
Q
The previous equation also shows the standby dissipation (ICC
times the VCC) of the driver.
Rev. 2 | Page 26 of 32 | www.onsemi.com
ADP3209
RAMP RESISTOR SELECTION
CURRENT LIMIT SETPOINT
The ramp resistor (RR) is used to set the size of the internal PWM
ramp. The value of this resistor is chosen to provide the best
combination of stability and transient response. Use the
following expression to determine a starting value:
To select the current limit setpoint, the resistor value for RCLIM must
be determined. The current limit threshold for the ADP3209 is
set with RCLIM. RCLIM can be found using the following equation:
RCS ×10×RSENSE × ICLIM
RCLIM
=
(22)
AR × L
3× AD × RDS ×CR
RPH ×10 μA
RR =
(19)
where:
PH is the resistor connecting the current sense resistor or
0.2×560 nH
3×5×3.4 mΩ×5 pF
R
RR =
= 439 kΩ
inductor switch node to the current sense amplifier.
RCS is the current sense amplifier feedback resistor.
where:
RSENSE is the sense current resistor or the inductor DCR.
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
ICLIM is the current limit setpoint.
R
DS is the total low-side MOSFET on resistance.
If RCLIM is greater than 500 kΩ, the current limit may be lower
than expected and require an adjustment of RCLIM. In this
example, ICLIM is the average current limit for the output of the
supply. For this example, choosing 20 A for ICLIM, results in an
RCLIM of 104 kΩ.
CR is the internal ramp capacitor value.
Another consideration in the selection of RR is the size of the
internal ramp voltage (see Equation 20). For stability and noise
immunity, keep the ramp size larger than 0.5 V. Taking this into
consideration, the value of RR in this example is selected as 340 kΩ.
POWER MONITOR
The PMON duty cycle is proportional to the load current. RPMONFS
sets the maximum duty cycle at the maximum current.
The internal ramp voltage magnitude can be calculated as follows:
AR ×(1 − D)×VVID
RR ×CR × fSW
VR =
(20)
I
LOAD ×RO × 9
+1 V
RPMONFS
=
(23)
10 μA
0.2×(1−0.062)×1.174 V
340 kΩ×5 pF×390 kHz
VR =
= 0.33 V
where ILOAD is the load current in amps when PMON is 100%
duty cycle, and RO is the droop resistance in ohms.
The size of the internal ramp can be increased or decreased. If it
is increased, stability and transient response improves but
thermal balance degrades. Conversely, if the ramp size is
decreased, thermal balance improves but stability and transient
response degrade. In the denominator of Equation 19, the factor
of 3 sets the minimum ramp size that produces an optimal
balance of good stability and transient response.
When PMON is connected with a pull-up resistor to the output
voltage, as shown in Figure 33, the average PMON voltage is
given by
VGFX × ILOAD ×RO ×9
PMON =
(24)
(
R
MONFS ×10 μA
)
− 1 V
FEEDBACK LOOP COMPENSATION DESIGN
COMP PIN RAMP
Optimized compensation of the ADP3209 allows the best
In addition to the internal ramp, there is a ramp signal on the
COMP pin due to the droop voltage and output voltage ramps.
This ramp amplitude adds to the internal ramp to produce the
following overall ramp signal at the PWM input:
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and that is equal to the droop
resistance (RO). With the resistive output impedance, the output
voltage droops in proportion with the load current at any load
current slew rate, ensuring the optimal position and allowing
the minimization of the output decoupling.
VR
(21)
VRT
=
C
D
D
E
S
T
T
U
2×
(1− D)
1−
fSW ×CX ×RO
where CX is the total bulk capacitance, and RO is the droop
resistance of the regulator.
For this example, the overall ramp signal is 0.23 V.
Rev. 2 | Page 27 of 32 | www.onsemi.com
ADP3209
With the multimode feedback structure of the ADP3209, it is
necessary to set the feedback compensation so that the
converter’s output impedance works in parallel with the output
decoupling. In addition, it is necessary to compensate for the
several poles and zeros created by the output inductor and
decoupling capacitors (output filter).
The expressions that follow compute the time constants for the
poles and zeros in the system and are intended to yield an
optimal starting point for the design; some adjustments may be
necessary to account for PCB and component parasitic effects
(see the Tuning Procedure for ADP3209 section):
RL ×VRT
VVID
RE = RO + AD × RDS
+
+
(29)
A Type III compensator on the voltage feedback is adequate
for proper compensation of the output filter. Figure 36 shows the
Type III amplifier used in the ADP3209. Figure 37 shows the
locations of the two poles and two zeros created by this amplifier.
2 × L ×(1− (n× D))×VRT
CX × RO ×VVID
LX RO − R'
VOLTAGE ERROR
(
)
TA = CX × RO − R' +
×
(30)
(31)
AMPLIFIER
REFERENCE
VOLTAGE
RO
×CX
RX
TB =
RX + R'−RO
ADP3209
C
S
T
T
U
AD × RDS
2× fSW
D
COMP
FB
V
RT × L −
2
3
D
E
TC =
(32)
(33)
OUTPUT
VOLTAGE
V
VID × RE
CX ×CZ ×RO2
RO − R' +CZ ×RO
C
A
R
R
FB
A
TD
where:
=
CX ×
(
)
C
C
FB
B
Figure 36. Voltage Error Amplifier
R' is the PCB resistance from the bulk capacitors to the ceramics
GAIN
and is approximately 0.4 mΩ (assuming an 8-layer motherboard).
R
DS is the total low-side MOSFET for on resistance.
AD is 5.
RT is 1.25 V.
–20dB/DEC
V
LX is the ESL of the bulk capacitors (450 pH for the two
–20dB/DEC
Panasonic SP capacitors).
The compensation values can be calculated as follows:
0dB
FREQUENCY
fP1
fZ2 fZ1
fP2
RO ×TA
RE ×RB
CA
=
=
=
(34)
(35)
Figure 37. Poles and Zeros of Voltage Error Amplifier
TC
CA
The following equations give the locations of the poles and
zeros shown in Figure 37:
RA
CB
CFB
1
TB
RB
fZ1
fZ2
fP1
fP2
=
=
=
=
(25)
(26)
(27)
(28)
(36)
(37)
2π×CA ×RA
1
TD
RA
=
2π×CFB ×RFB
1
The standard values for these components are subject to the
tuning procedure described in the Tuning Procedure for
ADP3209 section.
2π(CA +CB )×RFB
CA +CB
2π×RA ×CB ×CA
Rev. 2 | Page 28 of 32 | www.onsemi.com
ADP3209
voltages is more than a few millivolts, adjust RCS2 using
Equation 40.
CIN SELECTION AND INPUT CURRENT
di/dt REDUCTION
VNL −VFLCOLD
VNL −VFLHOT
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to VOUT/VIN. To prevent large voltage transients, use a
low ESR input capacitor sized for the maximum rms current.
The maximum rms capacitor current occurs at the lowest input
voltage and is given by
RCS2(NEW ) = RCS2(OLD)
×
(40)
3. Repeat Step 2 until no adjustment of RCS2 is needed.
4. Compare the output voltage with no load to that with a full
load using 5 A steps. Compute the load line slope for each
change and then find the average to determine the overall
load line slope (ROMEAS).
5. If the difference between ROMEAS and RO is more than 0.05 mΩ,
use the following equation to adjust the RPH values:
1
D
ICRMS = D × IO
×
−1
(38)
1
0.15
ICRMS = 0.15×15A ×
−1 = 5.36 A
ROMEAS
RO
RPH(NEW) = RPH(OLD)
×
(41)
where IO is the output current.
6. Repeat Steps 4 and 5 until no adjustment of RPH is needed.
Once this is achieved, do not change RPH, RCS1, RCS2, or RTH
for the rest of the procedure.
7. Measure the output ripple with no load and with a full load
with scope, making sure both are within the specifications.
In a typical notebook system, the battery rail decoupling is
achieved by using MLC capacitors or a mixture of MLC
capacitors and bulk capacitors. In this example, the input
capacitor bank is formed by four pieces of 10 µF, 25 V MLC
capacitors, with a ripple current rating of about 1.5 A each.
Set the AC Load Line
SOFT TRANSIENT SETTING
1. Remove the dc load from the circuit and connect a
dynamic load.
2. Connect the scope to the output voltage and set it to dc
coupling mode with a time scale of 100 µs/div.
3. Set the dynamic load for a transient step of about 40 A at
1 kHz with 50% duty cycle.
4. Measure the output waveform (note that use of a dc offset
on the scope may be necessary to see the waveform). Try to
use a vertical scale of 100 mV/div or finer.
5. The resulting waveform will be similar to that shown in
Figure 38. Use the horizontal cursors to measure VACDRP and
VDCDRP, as shown in Figure 38. Do not measure the under-
shoot or overshoot that occurs immediately after the step.
As described in the Theory of Operation section, during the soft
transient, the slew rate of the VCCGFX reference voltage change is
controlled by the ST pin capacitance. The ST pin capacitance is
set to satisfy the slew rate for a fast exit as follows:
7.5 μA
SLEWRATE
CST
=
(39)
where:
7.5 µA is the source/sink current of the ST pin.
SLEWRATE is the voltage slew rate after a change in VID voltage
and is defined as 10 mV/µA in the IMVP-6+ specification.
CST is 750 pF, and the closest standard capacitance is 680 pF.
TUNING PROCEDURE FOR ADP3209
Set Up and Test the Circuit
1. Build a circuit based on the compensation values computed
from the design spreadsheet.
2. Connect a dc load to the circuit.
3. Turn on the ADP3209 and verify that it operates properly.
4. Check for jitter with no load and full load conditions.
V
ACDRP
V
DCDRP
Set the DC Load Line
1. Measure the output voltage with no load (VNL) and verify
that this voltage is within the specified tolerance range.
2. Measure the output voltage with a full load when the device is
cold (VFLCOLD). Allow the board to run for ~10 minutes with
a full load and then measure the output when the device is
hot (VFLHOT). If the difference between the two measured
Figure 38. AC Load Line Waveform
6. If the difference between VACDRP and VDCDRP is more than a
couple of millivolts, use Equation 42 to adjust CCS. It may
Rev. 2 | Page 29 of 32 | www.onsemi.com
ADP3209
be necessary to try several parallel values to obtain an
time a change is made to ensure that the output decoupling
is stable.
adequate one because there are limited standard capacitor
values available (it is a good idea to have locations for two
capacitors in the layout for this reason).
3. For load release (see Figure 40), if VTRANREL is larger than
the value specified by IMVP-6+, a greater percentage of
output capacitance is needed. Either increase the
capacitance directly or decrease the inductor values. (If
inductors are changed, however, it will be necessary to
redesign the circuit using the information from the
spreadsheet and to repeat all tuning guide procedures).
VACDRP
VDCDRP
CCS(NEW ) = CCS(OLD)
×
(42)
7. Repeat Steps 5 and 6 until no adjustment of CCS is needed.
Once this is achieved, do not change CCS for the rest of the
procedure.
8. Set the dynamic load step to its maximum step size (but do
not use a step size that is larger than needed) and verify
that the output waveform is square, meaning VACDRP and
VDCDRP are equal.
V
TRANREL
V
DROOP
9. Ensure that the load step slew rate and the power-up slew
rate are set to ~150 A/µs to 250 A/µs (for example, a load
step of 50 A should take 200 ns to 300 ns) with no
overshoot. Some dynamic loads have an excessive
overshoot at power-up if a minimum current is incorrectly
set (this is an issue if a VTT tool is in use).
Set the Initial Transient
Figure 40. Transient Setting Waveform, Load Release
1. With the dynamic load set at its maximum step size,
expand the scope time scale to 2 µs/div to 5 µs/div. This
results in a waveform that may have two overshoots and
one minor undershoot before achieving the final desired
value after VDROOP (see Figure 39).
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
1. For best results, use a PCB of four or more layers. This
should provide the needed versatility for control circuitry
interconnections with optimal placement; power planes for
ground, input, and output; and wide interconnection traces
in the rest of the power delivery current paths. Keep in
mind that each square unit of 1 oz copper trace has a
resistance of ~0.53 mΩ at room temperature.
V
DROOP
2. When high currents must be routed between PCB layers, vias
should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating
is not exceeded.
V
TRAN1
V
TRAN2
Figure 39. Transient Setting Waveform, Load Step
3. If critical signal lines (including the output voltage sense
lines of the ADP3209) must cross through power circuitry,
it is best if a signal ground plane can be interposed between
those signal lines and the traces of the power circuitry. This
serves as a shield to minimize noise injection into the
signals at the expense of increasing signal ground noise.
4. An analog ground plane should be used around and under
the ADP3209 for referencing the components associated
with the controller. This plane should be tied to the nearest
ground of the output decoupling capacitor, but should not
be tied to any other power circuitry to prevent power
currents from flowing into the plane.
2. If both overshoots are larger than desired, try the following
adjustments in the order shown.
a. Increase the resistance of the ramp resistor
(RRAMP) by 25%.
b. For VTRAN1, increase CB or increase the switching
frequency.
c. For VTRAN2, increase RA by 25% and decrease CA by 25%.
If these adjustments do not change the response, it is
because the system is limited by the output decoupling.
Check the output response and the switching nodes each
Rev. 2 | Page 30 of 32 | www.onsemi.com
ADP3209
5. The components around the ADP3209 should be located
close to the controller with short traces. The most important
traces to keep short and away from other traces are those
to the FB and CSFB pins. Refer to Figure 35 for more
details on the layout for the CSFB node.
6. The output capacitors should be connected as close as
possible to the load (or connector) that receives the power
(for example, a microprocessor core). If the load is distributed,
the capacitors should also be distributed and generally placed
in greater proportion where the load is more dynamic.
7. Avoid crossing signal lines over the switching power path
loop, as described in the Power Circuitry section.
for this are improved current rating through the vias and
improved thermal performance from vias extended to the
opposite side of the PCB, where a plane can more readily
transfer heat to the surrounding air. To achieve optimal
thermal dissipation, mirror the pad configurations used to
heat sink the MOSFETs on the opposite side of the PCB. In
addition, improvements in thermal performance can be
obtained using the largest possible pad area.
3. The output power path should also be routed to encompass
a short distance. The output power path is formed by the
current path through the inductor, the output capacitors,
and the load.
4. For best EMI containment, a solid power ground plane
should be used as one of the inner layers and extended
under all power components.
Power Circuitry
1. The switching power path on the PCB should be routed to
encompass the shortest possible length to minimize
radiated switching noise energy (that is, EMI) and
conduction losses in the board. Failure to take proper
precautions often results in EMI problems for the entire PC
system as well as noise-related operational problems in the
power-converter control circuitry. The switching power
path is the loop formed by the current path through the
input capacitors and the power MOSFETs, including all
interconnecting PCB traces and planes. The use of short,
wide interconnection traces is especially critical in this
path for two reasons: it minimizes the inductance in the
switching loop, which can cause high energy ringing, and it
accommodates the high current demand with minimal
voltage loss.
Signal Circuitry
1. The output voltage is sensed and regulated between the FB
and FBRTN pins, and the traces of these pins should be
connected to the signal ground of the load. To avoid
differential mode noise pickup in the sensed signal, the
loop area should be as small as possible. Therefore, the FB
and FBRTN traces should be routed adjacent to each other,
atop the power ground plane, and back to the controller.
2. The feedback traces from the switch nodes should be
connected as close as possible to the inductor. The CSREF
signal should be Kelvin connected to the center point of
the copper bar, which is the VCCGFX common node for the
inductor.
2. When a power-dissipating component (for example, a
power MOSFET) is soldered to a PCB, the liberal use of
vias, both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons
3. On the back of the ADP3209 package, there is a metal pad
that can be used to heat sink the device. Therefore, running
vias under the ADP3209 is not recommended because the
metal pad may cause shorting between vias.
Rev. 2 | Page 31 of 32 | www.onsemi.com
ADP3209
OUTLINE DIMENSION
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 41. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option Ordering Quantity
5,000
ADP3209JCPZ-RL1
0°C to 100°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
1 Z = RoHS Compliant Part.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or
use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800-282-9855
Toll Free USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81-3-5773-3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
Rev. 2 | Page 32 of 32 | www.onsemi.com
相关型号：
ADP3211AMNR2
SWITCHING CONTROLLER, 400kHz SWITCHING FREQ-MAX, QCC32, 5 X 5 MM, 1 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, QFN-32
ONSEMI
ADP3211MNR2
IC SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, QCC32, 5 X 5 MM, 1 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, QFN-32, Switching Regulator or Controller
ONSEMI
©2020 ICPDF网 联系我们和版权申明