ADP3808A [ONSEMI]
High Efficiency Switch Mode Li-Ion Battery Charger; 高效率开关模式锂离子电池充电器
| 型号： | ADP3808A |
| 厂家： | 
ONSEMI |
| 描述： | High Efficiency Switch Mode Li-Ion Battery Charger |
| 文件： | 总15页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADP3808A
High Efficiency Switch
Mode Li-Ion Battery
Charger
The ADP3808A is a complete Li-Ion battery charging controller for
3− or 4−cell battery packs. The device combines accurate final battery
charge voltage control with constant current control to simplify the
implementation of constant-current, constant-voltage (CCCV)
chargers.
The final battery charge voltage is programmable between 4.0 V to
4.5 V per cell, allowing the charging of various cell types. The charge
current is programmable over a wide range from trickle charging to
full charging. The system current sense amplifier includes an ac
adapter detection output to signal that the adapter is connected. The
bootstrapped synchronous driver controls two N−channel MOSFET
transistors for high efficiency charging at a low system cost.
The ADP3808A is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 24−lead
LFCSP package.
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MARKING
DIAGRAM
LFCSP24
CASE 932AG
ADP
3808A
JPZ
#YYWW
xx
#
= Device Code
= Pb−Free Package
Features
• Selectable 3−Cell or 4−Cell Operation
• Adjustable 4.0 V to 4.5 V Per Cell
• High End-of-Charge Voltage Accuracy
YYWW = Date Code
PIN ASSIGNMENT
♦
♦
♦
0.4% @ 25°C
0.6% @ 5°C to 55°C
0.8% @ 0°C to 100°C
• Programmable Charge Current, Including Trickle Charge
• Bootstrapped Synchronous Drive for External N−Channel MOSFETs
• Programmable Oscillator Frequency
ISYS
LIMSET
LIMIT
1
2
3
4
5
6
18 DRVREG
17 DRVL
16 PGND
15 CSP
ADP3808A
TOP VIEW
EXTPWR
RT
(Not to Scale)
• This is a Pb−Free Device
14 CSM
REFIN
13 CSADJ
Applications
• Portable Computers
• Portable Equipment
ORDERING INFORMATION
†
Device*
Package
Shipping
ADP3808AJCPZ−RL LFCSP24 5000/Tape & Reel
*The “Z’ suffix indicates Pb−Free package.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
January, 2009 − Rev. 1
ADP3808A/D
ADP3808A
VCC
22
LOW−SIDE
DRIVE
REGULATOR
UVLO
AND BIAS
8
EN
DRVREG
BST
19
20
21
EN
IN
DRVH
SW
REFERENCE
OSCILLATOR
DRVREG
10
AGND
CONTROL
LOGIC
18 DRVREG
17
DRVLSD
DRVL
5
RT
CELLSEL
BAT
16
PGND
12
11
3−/4−
CELL
VTH
CSP
CSM
15
14
6
REFIN
BATTERY
VOLTAGE
ADJUST
g
m
7
9
BATADJ
COMP
g
m
CHARGE
CURRENT
SETPOINT
23
24
SYSM
SYSP
13
4
CSADJ
CMP
1V
EXTPWR
CMP
SYS+
CMP
18.25V
1
2
3
ISYS LIMSET
LIMIT
Figure 1. Functional Block Diagram
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2
ADP3808A
ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Value
−0.3 to +25
Unit
V
Supply Voltage Input
VCC
Power Ground
PGND
−0.3 to +0.3
V
Bootstrap Supply Voltage Input
BST to Switching Node
Switching Node
BST
BST to SW
SW
−0.3 to +30
V
−0.3 to +6
V
−4 to +25
V
High−Side Driver Output
Low−Side Driver Output
DRVH
SW − 0.3 to BST + 0.3
PGND − 0.3 to DRVREG + 0.3
V
DRVL
V
System Sense Inputs to Analog Ground
SYSP, SYSM to AGND
V
DC
−25 to +30
−25 to +35
< 50 msec
Battery Input, Current Sense Inputs to Analog
Ground
BAT, CSP, CSM to AGND
SYSP to SYSM
−0.3 to V + 0.3
V
V
V
V
CC
Positive System Sense Input to Negative System
Sense Input
−5 to +5
−5 to +5
Positive Current Sense Input to Negative Current
Sense Input
CSP to CSM
All Other Inputs and Outputs
DRVREG, CSADJ, EN,
CELLSEL, REFIN, BATADJ,
LIMSET, LIMIT, ISYS, EXTPWR
−0.3 to +6
2-Layer Board
4-Layer Board
q
125
83
°C/W
JA
Operating Ambient Temperature Range
Junction Temperature Range
T
0 to 100
0 to 150
°C
°C
°C
°C
A
T
J
Storage Temperature Range
T
S
−65 to +150
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
300
215
220
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
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3
ADP3808A
PIN DESCRIPTION
Pin No.
Symbol
Description
1
2
3
ISYS
LIMSET
LIMIT
Output for System Current Sense Amplifier.
System Current Limit Set Point Input.
System Current Limit Output. This is an open-drain pin and requires a pull-up resistor to a maximum
of 6.0 V.
4
5
EXTPWR
RT
External Adapter Sense Open-Drain Output. This pin pulls low when the ac adapter voltage is
present. A pullup resistor is required to a maximum of 6 V.
Frequency Setting Resistor Input. An external resistor connected between this pin and AGND sets
the oscillator frequency of the device.
6
7
REFIN
Reference Input for BATADJ and CSADJ.
BATADJ
Battery Voltage Adjust Input. This pin uses an analog voltage referenced to REFIN to program
voltage from 4.0 V to 4.5 V per cell.
8
EN
Charger Enable Input. Pulling this pin to AGND disables the DRVH and DRVL outputs and puts the
circuitry powered by V into a low power state. The system amplifier and EXTPWR are still active.
CC
9
COMP
AGND
Output of Error Amplifiers and Compensation Point.
Analog Ground. Reference point for the battery sense and all analog functions.
Battery Sense Input.
10
11
12
BAT
CELLSEL
Battery Cell Selection Input. Pulling this pin high selects 3-cell operation; pulling it low selects 4-cell
operation.
13
14
15
CSADJ
CSM
Charge Current Programming Input. This pin uses an analog voltage referenced to REFIN to program
the battery charge current. (V
− V
) = 96 mV x CSADJ/REFIN.
CSP
CSM
Negative Current Sense Input. This pin connects to the battery side of the battery current sense
resistor.
CSP
Positive Current Sense Input. This pin connects to the inductor side of the battery current sense
resistor.
16
17
18
PGND
DRVL
Power Ground. This pin should closely connect to the source of the lower MOSFET.
Synchronous Rectifier Drive. Output drive for the lower MOSFET.
DRVREG
Driver Supply Output. A bypass capacitor should be connected from this pin to PGND to provide
filtering for the low−side supply.
19
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins
holds this bootstrapped voltage for the high−side MOSFET as it is switched.
20
21
DRVH
SW
Main Switch Drive. Output drive for the upper MOSFET.
Switch Node Input. This pin is connected to the buck-switching node, close to the source of the upper
MOSFET, and is the floating return for the upper MOSFET drive signal.
22
23
VCC
Input Supply. This pin does not power the SYS amplifier section.
SYSM
Negative System Current Sense Input. This pin connects to the battery side of the system current
sense resistor.
24
25
SYSP
Positive System Current Sense Input. This pin connects to the adapter side of the system current
sense resistor. This pin also provides power to the system amplifier section.
Paddle
This pin should be connected to AGND.
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4
ADP3808A
ELECTRICAL CHARACTERISTICS
V
CC
= 20 V, EN = 5.0 V, REFIN = 3.0 V, T = 0°C to 100°C; unless otherwise noted. (Note 1)
A
Parameter
Symbols
Symbol
Min
Typ
Max
Unit
Battery Voltage Sensing
Accuracy
ΔV
T = 25°C, 13 V ≤ V ≤ 21 V,
−0.4
+0.4
%
BAT
A
CC
BATADJ = 0 V or BATADJ = REFIN
5°C ≤ T ≤ 55°C, 13 V ≤ V ≤ 21 V,
−0.6
−0.8
+0.6
+0.8
%
%
A
CC
BATADJ = 0 V or BATADJ = REFIN
13 V ≤ V ≤ 21 V,
CC
BATADJ = 0 V or BATADJ = REFIN
Input Resistance
R
170
0.2
135
1
kW
mA
%
BAT
Shutdown Leakage Current
Overvoltage Threshold
Overvoltage Response Time
Battery Voltage Adjust
BATADJ Input Range
REFIN Input Range
I
EN = 0 V
1.0
BAT(SD)
V
120
BAT(OV)
BAT(OV)
t
V
to COMP < 1 V
ms
BAT(OV)
V
0
REFIN
3.5
V
V
V
V
V
V
BATADJ
V
REFIN
2.0
3-Cell Voltage Low
V
BATADJ = 0 V, CELLSEL = 3.3 V
BATADJ = REFIN, CELLSEL = 3.3 V
BATADJ = 0 V, CELLSEL = 0 V
BATADJ = REFIN, CELLSEL = 0 V
12.0
13.5
16.0
18.0
BAT
BAT
BAT
BAT
3-Cell Voltage High
V
V
V
4-Cell Voltage Low
4-Cell Voltage High
Battery Current Sense Amplifier
Accuracy (Note 2)
CSADJ = REFIN, 3 V ≤ V
≤ 21 V
−5
−9
+5
+9
%
%
CS(CM)
CSADJ = REFIN / 5, 3 V ≤ V
21 V
≤
CS(CM)
0°C ≤ T ≤ 55°C, CSADJ = REFIN / 32,
−33
−40
0
+33
+40
%
%
A
3 V ≤ V
≤ 12 V
CS(CM)
0°C ≤ T ≤ 55°C, CSADJ = REFIN / 32,
A
12 V < V
≤ 21 V
CS(CM)
Input Common Mode Range
Input Bias Current, Operating
Input Bias Current, Shutdown
Input Bias Current, CSM
Gain
V
V
CC
V
CM(CS)
I
40
0.1
0.1
31.25
1
mA
mA
mA
V/V
mA
mV
ms
B(CSP)
I
EN = 0 V
1
2
B(CSP,SD)
I
B(CSM)
A
V(CS)
B(CSADJ)
CSADJ Bias Current
I
2
Overcurrent Threshold (Note 2)
Overcurrent Response Time
DRVL Shutdown Threshold
System Current Sense Amplifier
Input Common Mode Range
Input Bias Current, SYSP
Input Bias Current, SYSM
Voltage Gain
V
90
100
1
110
CS(OC)
t
V
OC
> 130 mV to COMP < 1 V
DC
CS(DRVLSD)
V
28
mV
V
SYSP and SYSM to AGND
10
22
400
1
V
CM(SYS)
I
V
V
V
V
= 19 V
= 19 V
300
0.1
50
5
mA
mA
V/V
mA
mV
V
B(SYSP)
SYS(CM)
SYS(CM)
I
B(SYSM)
/(V
− V )
SYSM
49.5
51.5
ISYS
ISYS
SYSP
ISYS Output Current
= 2.5 V
LIMIT Threshold
V
V
SYSP to SYSM, LIMSET = 2.5 V
48
0
53
58
3.5
75
TH(LIMIT)
LIMSET Input Range
V
LIMSET
LIMIT Output Voltage Low
I
= −100 mA
30
mV
OL(LIMIT)
LIMIT
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2. Measured between CSP and CSM. (V − V ) = 96 mV x CSADJ/REFIN.
CSP
CSM
3. For propagation delays, t
refers to the specified signal going high, and t refers to it going low.
pdh
pdl
4. The turn−on of DRVL is initiated after DRVH turns off by either SW crossing a ~1.0 V threshold or by examination of the timeout delay.
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5
ADP3808A
ELECTRICAL CHARACTERISTICS
V
CC
= 20 V, EN = 5.0 V, REFIN = 3.0 V, T = 0°C to 100°C; unless otherwise noted. (Note 1)
A
Parameter
Symbols
Symbol
Min
Typ
Max
Unit
LIMIT Propagation Delay Time
t
(SYSP) − (SYSM) rising > 55 mV to
LIMIT going low
1
ms
pdl(LIMIT)
EXTPWR Current Threshold
EXTPWR Voltage Threshold
EXTPWR Output Voltage Low
V
V
V
V
SYSP to SYSM
SYSP to AGND
17.5
18.0
22.5
18.25
5
27.5
18.5
50
mV
V
TH(EXTPWR)
TH(EXTPWR)
TH(EXTPWR)
dpl(EXTPWR)
I
= −100 mA
mV
ms
EXTPWR
EXTPWR Propagation Delay
Time
SYSP Rising > 18.5 V to EXTPWR
going low
1
Oscillator
Maximum Frequency
Frequency Variation
RT Output Voltage
f
1
290
2
MHz
kHz
V
OSC
Δf
RT = 150 kW
250
1.9
340
2.1
OSC
V
RT
Zero Duty Cycle Threshold
Maximum Duty Cycle Threshold
Logic Inputs (EN, CELLSEL)
Input Voltage High
Measured at COMP
Measured at COMP
1
V
2
V
V
2.0
–1
V
V
IH
Input Voltage Low
V
0.8
+1
IL
Input Current
I
IN
Inputs = 0 V or 5 V
mA
High−Side Driver
Output Resistance, Sourcing
Current
BST to SW = 5 V
BST to SW = 5 V
BST to SW = 0 V
3
3
8
8
W
W
Output Resistance, Sinking
Current
Output Resistance, Unbiased
Transition Time
10
20
45
kW
ns
ns
t
, t
BST to SW = 5 V, C
= 1 nF
= 1 nF
40
70
rDRVH fDRVH
LOAD
LOAD
Propagation Delay Time
Low−Side Driver
t
BST to SW = 5 V, C
25
pdhDRVH
Output Resistance, Sourcing
Current
3.8
1.5
8
8
W
W
Output Resistance, Sinking
Current
Output Resistance, Unbiased
Transition Time
VCC = PGND
10
20
15
kW
ns
ns
ns
t
, t
C
C
= 1 nF
= 1 nF
40
35
rDRVL fDRVL
LOAD
LOAD
Propagation Delay Time (Note 3)
Timeout Delay (Note 4)
t
pdhDRVL
SW = 5 V
SW = PGND
150
150
300
300
Supply V
CC
Supply Voltage Range
Supply Current
V
CC
10
22
V
Normal Mode
I
EN = 5 V
EN = 0 V
9.8
1
14
10
10
mA
mA
V
VCC
Shutdown Mode
I
VCC(SD)
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
DRV Regulator Output Voltage
DRV Regulator Output Current
V
UVLO
V
CC
rising
9
9.5
600
5.25
mV
V
V
C = 100 nF
L
5.0
10
5.5
DRVREG
I
mA
DRVREG
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2. Measured between CSP and CSM. (V − V ) = 96 mV x CSADJ/REFIN.
CSP
CSM
3. For propagation delays, t
refers to the specified signal going high, and t refers to it going low.
pdh
pdl
4. The turn−on of DRVL is initiated after DRVH turns off by either SW crossing a ~1.0 V threshold or by examination of the timeout delay.
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6
ADP3808A
TYPICAL CHARACTERISTICS
30
25
20
0.15
V
T
= 16V
CC
A
V
= 16V
CC
= 255C
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
15
10
5
–0.25
–0.3
0
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
0
100
10
20
30
40
50
60
70
80
90
V
ACCURACY (%)
TEMPERATURE (5C)
BAT
Figure 2. VBAT Accuracy Distribution
Figure 3. VBAT Accuracy vs. Temperature
0.07
0.06
12
T
= 255C
NO LOADS
A
T
= 05C
A
11
10
9
0.05
0.04
0.03
0.02
0.01
0
T
= 255C
A
T
= 1005C
A
8
–0.01
–0.02
–0.03
–0.04
7
6
12
13
14
15
16
(V)
17
18
19
20
13
14
15
16
V
17
(V)
18
19
20
V
CC
CC
Figure 4. VBAT Accuracy vs. VCC
Figure 5. On Supply Current vs. VCC
126
106
86
20
18
16
14
12
V
T
= 16V
fOASC = 300kHz
CC
T
= 1005C
= 255C
A
T
= 255C
A
66
46
T
= 05C
A
26
6
10
0
13
14
15
16
17
18
19
12
20
0
500
1000
1500
2000
2500
3000
3500
V
(V)
DRIVER LOAD CAPACITANCE (pF)
CC
Figure 6. Off Supply Current vs. VCC
Figure 7. Supply Current vs. Driver Load
Capacitance
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7
ADP3808A
TYPICAL CHARACTERISTICS
6
5
ISYS RISING
ISYS FALLING
400
350
4
3
2
300
250
1
0
200
90
110
130
150
170
190
210
0
0.5
1
1.5
2
2.5
3.0
V
(V)
RT (kW)
ISYS
Figure 8. Oscillator Frequency vs. RT
Figure 9. VLIMIT vs. VISYS
3.3
3.2
3.1
3.0
2.9
4.5
4
V
= 16V
V
= 16V
CC
CC
SOURCE
3.5
3
SINK
2.5
2
SOURCE
SINK
2.8
2.7
1.5
1
0
20
40
60
80
100
0
20
40
60
80
100
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 10. DRVH On Resistance vs. Temperature
Figure 11. DRVL On Resistance vs. Temperature
V
T
= 16V
CC
A
DRVH
5V/DIV
= 255C
DRVL 5V/DIV
200ns/DIV
Figure 12. Driver Waveforms
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8
ADP3808A
TYPICAL CHARACTERISTICS
100
95
90
85
80
75
70
65
60
V
V
T
= 19V
BAT
= 255C
CC
= 12.4V
A
0
0.5
1.0
1.5
2.0
2.5
3.0
CHARGE CURRENT (A)
Figure 13. Conversion Efficiency vs. Charge Current
97
96
I
= 2A
CHARGE
95
94
93
92
91
90
89
88
I
= 3A
CHARGE
V
T
= 19V
= 255C
CC
A
3
4
5
6
7
8
9
10
11
12
13
V
(V)
BAT
Figure 14. Conversion Efficiency vs. Battery Voltage
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9
ADP3808A
Theory of Operation
drives two external power NMOS transistors for a simple,
lower cost power stage.
The ADP3808A combines a bootstrapped synchronous
switching driver with programmable current control and
accurate final battery voltage control in a constant-current,
constant-voltage (CCCV) Li-Ion battery charger. High
accuracy voltage control is needed to safely charge Li-Ion
batteries, which are typically specified at 4.2 V 1% per
cell. For a typical notebook computer battery pack, three or
four cells are in series, giving a total voltage of 12.6 V or
16.8 V. The ADP3808A allows the final battery voltage to
be programmed. The programmable range is 4.0 V to 4.5 V
per cell. The total number of cells to be charged can be set
to either 3 or 4 via a control pin.
Another requirement for safely charging Li-Ion batteries
is accurate control of the charge current. The actual charge
current depends on the number of cells in parallel within the
battery pack. Typically, this is in the range of 2.0 A to 3.0A.
The ADP3808A provides flexibility in programming the
charge current over a wide range. An external resistor is used
to sense the charge current. The charge current can be set by
programming the sense resistor voltage drop. The voltage
drop can be set to a maximum of 96 mV. This
programmability allows the current to be changed during
charging. For example, the charge current can be reduced for
trickle charging.
The ADP3808A also provides an uncommitted current
sense amplifier. This amplifier provides an analog output
pin for monitoring the current through an external sense
resistor. The amplifier can be used anywhere in the system
that high-side current sensing is needed. The sense amplifier
output is compared to a programmable voltage limit. If the
limit is exceeded, the LIMIT pin is asserted. The system
sense amplifier is also used to detect the presence of an ac
adaptor. If the adaptor is detected, the ADP3808A asserts a
logic pin to signal the detection.
Setting the Charge Current
The charge current is measured across an external sense
resistor, R , between the CSP and CSM pins. The input
CS
common-mode range is from ground to V , allowing
CC
current control in short-circuit and low dropout conditions.
The voltage between CSP and CSM is programmed by a
ratio of the voltages at CSADJ and REFIN according to
Equation 1.
CSADJ
REFIN
(eq. 1)
V
CSP * VCSM + 96 mV
For example, using a 20 mW sense resistor gives a range
from 150 mA with CSADJ = REFIN/32 to 4.8 A maximum
when CSADJ = REFIN.
The synchronous driver provides high efficiency when
charging at high currents. Efficiency is important mainly to
reduce the amount of heat generated in the charger, but also
to stay within the power limits of the ac adapter. With the
addition of a bootstrapped high-side driver, the ADP3808A
The power dissipation in R should be kept below
CS
500 mW. Components R4 and C13 in Figure 15 provide high
frequency filtering for the current sense signal.
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10
ADP3808A
R
SS
10mR
SYSTEM
DC/DC
R
20mR
1/2 Q1
FD56990A
CS
L1
V
IN
+
–
22uH
C16
22uF
+
C15
22uF
R13
10R
1/2 Q1
FD56990A
R4
510R
R2
510R
BATTERY
12.6V/16.8V
–
C13
22nF
C1
2.2uF
3.3V
C14
2.2uF
C9
100nF
BST DRV
ISYS
LIMIT
SW DRVL PGND
V
CSP
CSM
SYSP
SYSM
CC
BOOTSTRAPPED
SYNCHRONOUS
DRIVER
3.3V
+
–
+
–
AMP2
AMP1
–
+
R9
EN
IN DRVLSD DRVLSD
LIMSET
–
+
–
V
+ V
REG
REF
R10
V
TH
UVLO
DRVREG
+
BIAS
5.25V
C10
0.1uF
1V
EXTPWR
–
gm1
+
–
–
+
+
SYSP
18.25V
EN
CSADJ
BAT
LOGIC
CONTROL
CHARGE
CURRENT
SETPOINT
3.3V
R11
3−/4−CELL
OSCILLATOR
–
gm2
+
SELECTION
REFIN
BATTERY
VOLTAGE
ADJUST
ADP3808A
BATADJ
R12
COMP
RT
CELLSEL
AGND
C8
0.22uF
150k
R8
56R
C11
Figure 15. Typical Application Circuit
Final Battery Voltage Control
As the battery approaches its final voltage, the
ADP3808A switches from CC mode to CV mode. The
BATADJ pin and is ratioed to the REFIN pin. The battery
voltage V is set according to Equation 2 and Equation 3.
BAT
For CELLSEL > 2 V:
change is achieved by the common output node of g 1 and
m
BATADJ
REFIN
(eq. 2)
(eq. 3)
V
BAT + 12 V ) 1.5 V
g 2. Only one of the two outputs controls the voltage at the
m
COMP pin. Both amplifiers can only pulldown on COMP,
such that when either amplifier has a positive differential
input voltage, its output is not active. For example, when the
For CELLSEL < 0.8 V:
BATADJ
REFIN
V
BAT + 16 V ) 2.0 V
battery voltage, V , is low, g 2 does not control VCOMP.
BAT
m
When the battery voltage reaches the desired final voltage,
Oscillator and PWM
g 2 takes control of the loop, and the charge current is
m
The oscillator generates a triangle waveform between
1.0 V and 2.0 V, which is compared to the voltage at the
COMP pin, setting the duty cycle of the driver stage. When
reduced.
Amplifier g 2 compares the battery voltage to a
m
programmable level set by pins BATADJ and REFIN. The
target battery voltage is dependent on the state of the
CELLSEL pin as CELLSEL sets the number of cells to be
charged. Pulling CELLSEL high sets the ADP3808A to
charge three cells. When CELLSEL is tied to ground, four
cells are selected. CELLSEL has a 2 mA pullup current as a
fail−safe to select three cells when it is left open.
V
COMP
is below 1.0 V, the duty cycle is zero. Above 2.0 V,
the duty cycle reaches its maximum. The oscillator
frequency is set by the external resistor at the RT pin, R
and is given by Equation 4.
,
OSC
41 109
ROSC
(eq. 4)
fOSC
+
The final battery voltage is programmable from 4.0 V to
4.5 V per cell. The programming voltage is applied to the
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ADP3808A
DRVREG
ADP3808A
BOOTSTRAPPED
SYNCHRONOUS DRIVER
BST
CMP3
CBST
DRVH
MIN
OFF
TIME
IN
Q1
EN
SW
–
CMP2
+
DELAY
DELAY
1V
DRVL
PGND
–
Q2
CMP1
+
1V
DRVLSD
Figure 16. Bootstrapped Synchronous Driver
5.25 V Bootstrap Regulator
Overlap protection is included in the driver to ensure that
both external MOSFETs are not on at the same time. When
DRVH turns off the upper MOSFET, the SW node goes low
due to the inductor current. The ADP3808A monitors the
SW voltage, and DRVL goes high to turn on the lower
MOSFET when SW goes below 1.0 V. When DRVL turns
off, an internal timer adds a delay of 50 ns before turning
DRVH on. When the charge current is low, the DRVLSD
comparator signals the driver to turn off the low-side
MOSFET and DRVL is held low. The DRVLSD threshold
is set to 0.8 V corresponding to a 32 mV differential between
the CS pins.
The driver stage monitors the voltage across the BST
capacitor with CMP3. When this voltage is less than 4.0 V,
CMP3 forces a minimum off time of 200 ns. This ensures
that the BST capacitor is charged even during DRVLSD.
However, because a minimum off time is only forced when
needed, the maximum duty cycle is greater than 99%.
The driver stage is powered by the internal 5.25 V
bootstrap regulator, which is available at the DRVREG pin.
Because the switching currents are supplied by this
regulator, decoupling must be added. A 0.1 mF capacitor
should be placed close to the ADP3808A, with the ground
side connected close to the power ground pin, PGND. This
supply is not recommended for use externally due to high
switching noise.
Bootstrapped Synchronous Driver
The PWM comparator controls the state of the
synchronous driver shown in Figure 16. A high output from
the PWM comparator forces DRVH on and DRVL off. The
drivers have an on resistance of less than 4.0 W for fast rise
and fall times when driving external MOSFETs.
Furthermore, the bootstrapped drive allows an external
NMOS transistor for the main switch instead of a PMOS. A
boost capacitor of 0.1 mF must be added externally between
BST and SW.
System Current Sense
The DRVL pin switches between DRVREG and PGND.
The 5.25 V output of DRVREG drives the external NMOS
An uncommitted differential amplifier is provided for
additional high-side current sensing. This amplifier, AMP2,
has a fixed gain of 50 V/V from the SYSP and SYSM pins
to the analog output at ISYS. The common-mode range of
the input pins is from 10 V to 22 V. This amplifier is the only
part of the ADP3808A that remains active during shutdown.
The power to this block is derived from the bias current on
the SYSP and SYSM pins.
with high V to lower the on resistance. PGND should be
GS
connected close to the source pin of the external
synchronous NMOS. When DRVL is high, this turns on the
lower NMOS and pulls the SW node to ground. At this point,
the boost capacitor is charged up through the internal boost
diode. When the PWM switches high, DRVL is turned off
and DRVH turns on. DRVH switches between BST and SW.
When DRVH is on, the SW pin is pulled up to the input
supply (typically 16 V), and BST rises above this voltage by
approximately 4.75 V.
LIMIT
The LIMIT pin is an open-drain output that signals when
the voltage at ISYS exceeds the voltage at LIMSET. The
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12
ADP3808A
internal comparator produces the function shown in
Figure 9. This is a graph of V vs. V where
comparator limits the maximum voltage. Neither of these
comparators affects the loop under normal charging
conditions.
LIMIT
ISYS
LIMSET is set to 1.5 V. The LIMIT pin should be pulled up
to a maximum of 6.0 V through a resistor. When ISYS is
below LIMSET, the LIMIT pin has high output impedance.
The open-drain output is capable of sinking 100 mA when
the threshold is exceeded. This comparator is turned off
during shutdown to conserve power.
Application Information
Design Procedure
Refer to Figure 15, the typical application circuit, for the
following description. The design follows that of a buck
converter. With Li-Ion cells it is important to have a regulator
with accurate output voltage control.
AC Adaptor Detection
The EXTPWR pin on the ADP3808A is an open−drain
active low output used to signal that an ac adaptor is
connected. If the ISYS voltage level is greater than 1.0 V or
the SYSP sense pin voltage is greater then 18.25 V, the
EXTPWR pin is driven low. A pullup resistor must be
connected when this function is required. The maximum
pullup voltage is 6.0 V.
Battery Voltage Settings
Inductor Selection
Usually the inductor is chosen based on the assumption
that the inductor ripple current is 15% of the maximum
output dc current at maximum input voltage. As long as the
inductor used has a value close to this, the system should
work fine. The final choice affects the trade−offs between
cost, size, and efficiency. For example, the lower the
inductance, the size is smaller but ripple current is higher.
This situation, if taken too far, leads to higher ac losses in the
core and the windings. Conversely, a higher inductance
results in lower ripple current and smaller output filter
capacitors, but the transient response will be slower. With
these considerations, the required inductance can be
calculated using Equation 5.
EN
A high impedance CMOS logic input is provided to turn
off the ADP3808A. When the voltage on EN is less than
0.8 V, the ADP3808A is placed in low power shutdown.
With the exception of the system current sense amplifier,
AMP2, all other circuitry is turned off. The reference and
regulators are pulled to ground during shutdown and all
switching is stopped. During this state, the supply current is
less than 5.0 mA. In addition, the BAT, CSP, CSM, and SW
pins go to high impedance to minimize current drain from
the battery.
V
IN, MAX * VBAT
(eq. 5)
L1 +
DMIN TS
DI
where the maximum input voltage V
is used with the
UVLO
IN, MAX
Undervoltage lock−out, UVLO, is included in the
minimum duty ratio D
. The duty ratio is defined as the
MIN
ADP3808A to ensure proper startup. As V rises above
ratio of the output voltage to the input voltage, V
The ripple current is calculated using Equation 6.
/V .
BAT IN
CC
1.0 V, the regulator tracks V
until it reaches its final
CC
voltage. However, the rest of the circuitry is held off by the
UVLO comparator. The UVLO comparator monitors the
regulator to ensure that it is above 5.0 V before turning on
DI + 0.3 IBAT, MAX
(eq. 6)
The maximum peak-to-peak ripple is 30%, that is 0.3, and
maximum battery current, I , is used.
BAT, MAX
the main charger circuitry. This occurs when V reaches
CC
For example, with V
= 19 V, V
= 12.6 V, I
BAT BAT,
IN, MAX
9.5 V. Monitoring the regulator outputs makes sure that the
charger circuitry and driver stage have sufficient voltage to
operate normally. The UVLO comparator includes 600 mV
of hysteresis to prevent oscillations near the threshold.
= 3.0 A, and T = 4 ms, the value of L1 is calculated as
MAX
S
18.9 mH. Choosing the closest standard value gives L1 = 22 mH.
Output Capacitor Selection
An output capacitor is needed in the charger circuit to
absorb the switching frequency ripple current and smooth
the output voltage. The rms value of the output ripple current
is given by:
Loop Feed Forward
As the startup sequence discussion shows, the response
time at COMP is slowed by the large compensation
capacitor. To speed up the response, two comparators can
quickly feed forward around the normal control loop and
pull the COMP node down to limit any overshoot in either
short-circuit or overvoltage conditions. The overvoltage
comparator has a trip point set to 35% higher than the final
battery voltage. The overcurrent comparator threshold is set
to 100 mV across the CS pins. When these comparators are
tripped, a normal soft−start sequence is initiated. The
overvoltage comparator is valuable when the battery is
removed during charging. In this case, the current in the
inductor causes the output voltage to spike up, and the
VIN, MAX
( )
D 1 * D
(eq. 7)
Irms
+
Ǹ
f L1 12
The maximum value occurs when the duty cycle is 0.5. Thus,
VIN, MAX
(eq. 8)
I
rms_MAX + 0.072
f L1
For an input voltage of 19 V and a 22 uH inductance, the
maximum rms current is 0.26 A. A typical 10 mF or 22 mF
ceramic capacitor is a good choice to absorb this current.
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13
ADP3808A
Input Capacitor Ripple
MOSFET Selection
As is the case with a normal buck converter, the pulse
current at the input has a high rms component. Therefore,
because the input capacitor has to absorb this current ripple,
it must have an appropriate rms current rating. The maximum
input rms current is given by
One of the features of the ADP3808A is that it allows use of
a high-side NMOS switch instead of a more costly PMOS
device. The converter also uses synchronous rectification for
optimal efficiency. To use a high-side NMOS, an internal
bootstrap regulator automatically generates a 5.25 V supply
across C10.
Ǹ
PBAT
h DVIN
(
)
D 1 * D
Maximum output current determines the
R
DS(ON)
(eq. 9)
Irms
+
D
requirement for the two power MOSFETs. When the
ADP3808A is operating in continuous mode, the simplifying
assumption can be made that one of the two MOSFETs is
always conducting the load current. The power dissipation for
each MOSFET is given by:
where h is the estimated converter efficiency (approximately
90%, 0.9) and P is the maximum battery power consumed.
BAT
This is a worst−case calculation and, depending on total
charge time, the calculated number could be relaxed.
Consult the capacitor manufacturer for further technical
information.
Upper MOSFET:
2
Ǹ
Ǹ
ǒ
DǓ
P
DISS + RDS(ON) IBAT
) VIN IBAT D
Decoupling the VCC Pin
TSW f
(eq. 10)
It is a good idea to use an RC filter (R13 and C14) from the
input voltage to the IC both to filter out switching noise and
to supply bypass to the chip. During layout, this capacitor
should be placed as close to the IC as possible. Values
between 0.1 mF and 2.2 mF are recommended.
Lower MOSFET:
2
Ǹ
ǒ
DǓ
P
DISS + RDS(ON) IBAT
) VIN
2
Ǹ
ǒ
1 * DǓ
IBAT
TSW f
(eq. 11)
Current Sense Filtering
where f is the switching frequency and t
is the switch
During normal circuit operation, the current sense signals
can have high frequency transients that need filtering to
ensure proper operation. In the case of the CSP and CSM
inputs, Resistor R4 is set to 510 W and the filter capacitor C13
is 22 nF. For the system current sense filter on SYSP, SYSM,
R2 is set to 510 W, C1 is 2.2 mF.
SW
transition time, usually 10 ns.
The first term accounts for conduction losses while the
second term estimates switching losses. Using these
equations and the manufacturer’s data sheets, the proper
device can be selected.
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14
ADP3808A
PACKAGE DIMENSIONS
LFCSP24 4x4, 0.5P
CASE 932AG−01
ISSUE O
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
B
E
D1
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
E1
MILLIMETERS
0.15
C
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
0.15
C
TOP VIEW
H
0.18
0.30
D
4.00 BSC
3.75 BSC
1.95 2.25
4.00 BSC
3.75 BSC
D1
D2
E
E1
E2
e
(A3)
0.10
C
1.95
2.25
A
0.50 BSC
NOTE 4
0.08
C
°
−−−
0.50
0.60
H
K
L
M
−−−
0.20
0.30
−−−
12
A1
SEATING
C
SIDE VIEW
PLANE
4X
M
4X
M
D2
K
SOLDERING FOOTPRINT*
7
4.30
13
PIN 1
INDICATOR
24X
0.63
2.30
E2
24X
L
1
1
24
24X
b
0.10
4.30
2.30
e
C
C
A
B
0.05
NOTE 3
BOTTOM VIEW
PACKAGE
OUTLINE
24X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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ADP3808A/D
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