AMIS30543C5431RG_技术文档

AMIS-30543

Micro-Stepping Motor

Driver

Introduction

The AMIS−30543 is a micro−stepping stepper motor driver for

bipolar stepper motors. The chip is connected through I/O pins and an

SPI interface with an external microcontroller. It has an on−chip

voltage regulator, reset−output and watchdog reset, able to supply

peripheral devices. AMIS−30543 contains a current−translation table

and takes the next micro−step depending on the clock signal on the

“NXT” input pin and the status of the “DIR” (=direction) register or

input pin. The chip provides a so−called “speed and load angle”

output. This allows the creation of stall detection algorithms and

control loops based on load−angle to adjust torque and speed. It is

using a proprietary PWM algorithm for reliable current control.

The AMIS−30543 is implemented in I2T100 technology, enabling

both high−voltage analog circuitry and digital functionality on the

same chip. The chip is fully compatible with the automotive voltage

requirements.

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1

32

QFN32

CASE 485J

MARKING DIAGRAM

32

1

The AMIS−30543 is ideally suited for general−purpose stepper

motor applications in the automotive, industrial, medical, and marine

environment. With the on−chip voltage regulator it further reduces the

BOM for mechatronic stepper applications.

AMIS30543

0C543−001

AWLYYWWG

Key Features

• Dual H−Bridge for 2−Phase Stepper Motors

• Programmable Peak−Current Up to 3 A

• On−Chip Current Translator

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

WL

YY

WW

G

• SPI Interface

• Speed and Load Angle Output

• Eleven Step Modes from Full Step Up to 128 Micro−Steps

• Fully Integrated Current−Sense

• PWM Current Control with Automatic Selection of Fast and Slow

Decay

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 37 of this data sheet.

• Low EMC PWM with Selectable Voltage Slopes

• Active Fly−Back Diodes

• Full Output Protection and Diagnosis

• Thermal Warning and Shutdown

• Compatible with 5 V and 3.3 V Microcontrollers

• Integrated 5 V Regulator to Supply External Microcontroller

• Integrated Reset Function to Reset External Microcontroller

• Integrated Watchdog Function

• These Devices are Pb−Free and are RoHS Compliant

1

Publication Order Number:

April, 2019 − Rev. 3

AMIS−30543/D

AMIS−30543

BLOCK DIAGRAM

VDD

CPN CPP VCP

VBB

Timebase

Vreg

CLK

Chargepump

POR

OTP

EMC

MOTXP

MOTXN

CS

DI

P

W

M

T

R

A

N

S

L

A

T

O

R

SPI

I−sense

DO

NXT

DIR

SLA

Logic &

Registers

EMC

Load

Angle

MOTYP

MOTYN

P

W

M

Tem. p

Sense

I−sense

POR/WD

CLR

AMIS−30543

Band−

gap

ERR

TST0

GND

Figure 1. Block Diagram AMIS−30543

32

31

30

29

28

27

26

25

24

1

GND

23

22

2

3

GND

DI

CLK

NXT

MOTXN

MOTYN

21

20

19

4

5

6

AMIS−30543

DIR

ERR

SLA

MOTYN

GND

18

17

7

8

9

10

11

12

13

14

15

16

Figure 2. Pin Out AMIS−30543

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AMIS−30543

Table 1. PIN LIST AND DESCRIPTION

Equivalent

Schematic

Name

GND

DI

1

Description

Type

Supply

Ground

2

SPI Data In

Digital Input

Digital Output

Analog Output

Type 2

Type 4

Type 5

CLK

3

SPI Clock Input

NXT

4

Next micro−step input

Direction input

DIR

5

ERR

SLA

6

Error output (open drain)

Speed load angle output

7

/

8

No function (to be left open in normal operation)

Negative connection of charge pump capacitor

Positive connection of charge pump capacitor

Charge pump filter−capacitor

CPN

CPP

VCP

CLR

9

High Voltage

Digital Input

Supply

10

11

12

“Clear” = chip reset input

Type 1

Type 2

Type 3

CS

13

SPI chip select input

VBB

MOTYP

GND

MOTYN

MOTXN

GND

MOTXP

VBB

POR/WD

TST0

/

14

High voltage supply Input

15, 16

17, 18

19, 20

21, 22

23, 24

25, 26

27

Negative end of phase Y coil output

Ground, heat sink

Driver Output

Supply

Positive end of phase Y coil output

Positive end of phase X coil output

Ground, heat sink

Driver Output

Supply

Negative end of phase X coil output

High voltage supply input

Driver Output

Supply

Type 3

Type 4

28

Power−on−reset and watchdog reset output (open drain)

Test pin input (to be tied to ground in normal operation)

No function (to be left open in normal operation)

SPI data output (open drain)

Digital Output

Digital Input

29

30

DO

31

Digital Output

Supply

Type 4

Type 3

VDD

32

Logic supply output (needs external decoupling capacitor)

Table 2. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

−0.3

−55

−50

−2

Max

Unit

V

BB

T

ST

Analog DC supply voltage (Note 1)

+40

+160

+175

+2

V

Storage temperature

°C

kV

T

J

Junction Temperature under bias (Note 2)

V

ESD

V

ESD

Electrostatic discharges on component level, All pins (Note 3)

Electrostatic discharges on component level, HiV pins (Note 4)

−8

+8

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. For limited time < 0.5 s.

2. Circuit functionality not guaranteed.

3. Human body model (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B).

4. HiV = High Voltage Pins MOTxx, V , GND; (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B).

BB

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AMIS−30543

EQUIVALENT SCHEMATICS

Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified

representations of the circuits used.

4K

IN

OUT

TYPE 1: CLR input

4 K

TYPE 4: DO, ERRB and PORB/WD open drain outputs

Rout

IN

SLA

TYPE 2: CLK , DI, CSB , NXT , DIR inputs

TYPE 5: SLA analog output

VDD

VBB

VDD

VBB

.

TYPE 3: VDD and VBB power supply inputs

Figure 3. In− and Output Equivalent Diagrams

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AMIS−30543

PACKAGE THERMAL CHARACTERISTICS

The AMIS−30543 is available in a NQFP32 package. For

The Rthja for 2S2P is simulated conform JEDEC

cooling optimizations, the NQFP has an exposed thermal

pad which has to be soldered to the PCB ground plane. The

ground plane needs thermal vias to conduct the heat to the

bottom layer. Figure 4 gives an example for good power

distribution solutions.

For precise thermal cooling calculations the major

thermal resistances of the device are given in Table 5. The

thermal media to which the power of the devices has to be

given are:

JESD−51 as follows:

• A 4−layer printed circuit board with inner power planes

and outer (top and bottom) signal layers is used

• Board thickness is 1.46 mm (FR4 PCB material)

• The 2 signal layers: 70 mm thick copper with an area of

2

5500 mm copper and 20% conductivity

• The 2 power internal planes: 36 mm thick copper with

2

an area of 5500 mm copper and 90% conductivity

The Rthja for 1S0P is simulated conform to JEDEC

JESD−51 as follows:

• Static environmental air (via the case)

• PCB board copper area (via the exposed pad)

The major thermal resistances of the device are the Rth

from the junction to the ambient (Rthja) and the overall Rth

from the junction to exposed pad (Rthjp). In Table 4 below

one can find the values for the Rthja and Rthjp, simulated

according to JESD−51.

• A 1−layer printed circuit board with only 1 layer

• Board thickness is 1.46 mm (FR4 PCB material)

• The layer has a thickness of 70 mm copper with an area

2

of 5500 mm copper and 20% conductivity

NQFP−32

Figure 4. Example of NQFP−32 PCB Ground Plane Layout in Top View (Preferred Layout at Top and Bottom)

ELECTRICAL SPECIFICATION

Recommend Operation Conditions

ranges is not guaranteed. Operating outside the

recommended operating ranges for extended periods of time

may affect device reliability.

Operating ranges define the limits for functional

operation and parametric characteristics of the device. Note

that the functionality of the chip outside these operating

Table 3. OPERATING RANGES

Symbol

Parameter

Min

+6

Max

+30

Unit

V

BB

Analog DC Supply

T

J

Junction Temperature (Note 5)

−40

+172

°C

5. No more than 100 cumulative hours in life time above T .

tw

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AMIS−30543

Table 4. DC PARAMETERS (The DC parameters are given for V and temperature in their operating ranges unless otherwise

BB

specified) Convention: currents flowing in the circuit are defined as positive.

Symbol

Pin(s)

Parameter

Remark/Test Conditions

Min

Typ

Max

Unit

SUPPLY AND VOLTAGE REGULATORS

V

I

Nominal operating supply range

6

30

12

V

BB

V

BB

Total internal current consumption Unloaded outputs

(Note 6)

mA

BB

V

Regulated Output Voltage

I

within limits

4.5

4

5

5.5

V

DD

LOAD

V

Regulated Output Voltage in Sleep −1 mA ≤ I

Mode

≤ 0 mA

DD_SLP

LOAD

> 9 V

V

BB

mA

I

Internal load current (Note 6)

Max Output Current

Unloaded outputs

8

INT

I

6 V v V < 8 V

15

40

V

DD

LOAD

BB

8 V v V v 30 V

BB

I

Current limitation

Pin shorted to ground

200

mA

DDLIM

I

Current Consumption when in

Sleep Mode

V

BB

> 9 V

230

mA

LOAD_SLP

POWER−ON−RESET (POR)

V

Internal POR comparator threshold

V

rising

falling

3.9

4.2

4.4

V

DDH

DD

V

3.86

0.35

DDL

DD

V

DD

V

Internal POR comparator

hysteresis

DDHYS

MOTORDRIVER

I

MOTXP Max current through motor coil in

T = 130°C

J

3000

mA

MDmax,Peak

MOTXN normal operation

MOTYP

MOTYN

R

On−resistance high−side driver,

0.15

0.1

0.2

0.4

0.8

0.4

0.45

0.4

W

HS

CUR[4:0] = 0...31 (Note 7)

T = 160°C

J

R

On−resistance low−side driver,

CUR[4:0] = 16...25 (Note 7)

LS3

T = 160°C

J

0.45

0.7

R

On−resistance low−side driver,

CUR[4:0] = 10...15 (Note 7)

LS2

T = 160°C

J

0.8

R

On−resistance low−side driver,

CUR[4:0] = 3...9 (Note 7)

1.1

LS1

T = 160°C

J

1.25

2.2

R

On−resistance low−side driver,

CUR[4:0] = 0...2 (Note 7)

LS0

T = 160°C

J

2.50

DIGITAL INPUTS

I

Input Leakage (Note 8)

Logic Low Threshold

T = 160°C

J

1

mA

V

leak

DI, CLK

NXT, DIR

CLR, CS

V

0

2.35

120

3

0.65

IL

V

Logic High Threshold

V

DD

V

IH

R

CLR

Internal Pulldown Resistor

200

300

9

kW

pd_CLR

R

TST0

pd_TST

6. Current with oscillator running, all analogue cells active, SPI communication and NXT pulses applied. No floating inputs. Parameter

guaranteed by design.

7. Characterization Data Only

8. Not valid for pins with internal Pulldown resistor

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AMIS−30543

Table 4. DC PARAMETERS (The DC parameters are given for V and temperature in their operating ranges unless otherwise

BB

specified) Convention: currents flowing in the circuit are defined as positive.

Symbol

Pin(s)

Parameter

Remark/Test Conditions

Min

Typ

Max

Unit

DIGITAL OUTPUTS

V

OL

DO, ERR, Logic Low level open drain

POR/WD

I

OL

= 5 mA

0.5

V

THERMAL WARNING AND SHUTDOWN

T

Thermal Warning

150

160

170

°C

tw

T

tsd

Thermal shutdown (Notes 9

and 10)

T

+ 20

tw

CHARGE PUMP

V

cp

Output voltage

6 V< V < 15 V

2 * V – 2

V

BB

15 V < V < 30 V

V

BB

+ 9

V

BB

+ 12.5

V

BB

+16

VCP

BB

C

External buffer capacitor

180

220

470

nF

buffer

CPP CPN External pump capacitor

180

220

470

pump

PACKAGE THERMAL RESISTANCE VALUE

Rth

Thermal Resistance

Simulated Conform JEDEC

30

60

K/W

ja

Junction−to−Ambient

JESD−51, 2S2P

NQFP

Simulated Conform JEDEC

JESD−51, 1S0P

Rth

Thermal Resistance

Junction−to−Exposed Pad

0.95

jp

NQFP

SPEED AND LOAD ANGLE OUTPUT

V

out

Output Voltage Range

0.2

V

DD

0.2

−

V

Output Offset SLA pin

Gain of SLA Pin = V

−50

50

mV

off

SLA

G

/ V

COIL

SLAG = 0

SLAG = 1

0.5

sla

BEMF

0.25

R

Output Resistance SLA pin

1

kW

out

9. No more than 100 cumulated hours in life time above T .

tw

10.Thermal shutdown is derived from thermal warning. Characterization Data Only.

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AMIS−30543

Table 5. AC PARAMETERS (The AC parameters are given for V and temperature in their operating ranges)

BB

Symbol

Pin(s)

Parameter

Remark/Test Conditions

Min

Typ

Max

Unit

INTERNAL OSCILLATOR

f

Frequency of internal oscillator

3.6

4

4.4

MHz

osc

MOTOR DRIVER

f

PWM frequency

20.5

41.0

22.8

45.6

200

140

70

25.1

50.2

kHz

PWM

Frequency depends only on

internal oscillator

MOTxx

Double PWM frequency

tb

EMC[1:0] = 00

EMC[1:0] = 01

EMC[1:0] = 10

EMC[1:0] = 11

EMC[1:0] = 00

EMC[1:0] = 01

EMC[1:0] = 10

EMC[1:0] = 11

V/ms

rise

Turn−on voltage slope, 10% to

90%

MOTxx

35

tb

200

140

70

fall

Turn−off voltage slope, 90% to

10%

MOTxx

35

DIGITAL OUTPUTS

t

DO

Output fall−time from V to V

inL

Capacitive load 400 pF and

50

5

ns

H2L

inH

ERR

pullup resistor of 1.5 kW

CHARGE PUMP

CPN CPP Charge pump frequency

f

250

kHz

ms

CP

t

MOTxx

Startup time of charge pump

(Note 11)

Spec external components

CPU

CLR FUNCTION

t

CLR

Hard reset duration time

Powerup time

100

ms

CLR

POWER−UP

t

V

= 12 V, I

LOAD

= 50 mA,

100

PU

BB

LOAD

C

= 220 nF

POR/WD

t

Reset duration

Reset filter time

See Figure 16

100

0.5

ms

POR

t

RF

ms

WATCHDOG

t

Watchdog time out interval

32

512

ms

WDTO

WDPR

POR/WD

t

Prohibited watchdog

acknowledge delay

2

NXT FUNCTION

t

NXT Minimum, High Pulse Width See Figure 5

NXT Minimum, Low Pulse Width See Figure 5

2

ms

NXT_HI

t

NXT Hold Time, Following

Change of DIR

See Figure 5

0.5

DIR_SET

NXT

t

NXT Hold Time, Before Change

of DIR

See Figure 5

0.5

ms

DIR_HOLD

11. Guaranteed by design

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AMIS−30543

t_{NXT_HI}

t_{NXT_LO}

0.5 V_CC

NXT

DIR

t_{DIR_SET}

t_{DIR_HOLD}

VALID

Figure 5. NXT−Input Timing Diagram

Table 6. SPI TIMING PARAMETERS

Symbol

Parameter

Min

1

Typ

Max

Unit

ms

t

SPI Clock Period

CLK

CLK_HIGH

t

SPI Clock High Time

SPI Clock Low Time

100

50

ns

ms

t

CLK_LOW

t

DI Set Up Time, Valid Data Before Rising Edge of CLK

DI Hold Time, Hold Data After Rising Edge of CLK

CS High Time

SET_DI

t

50

HOLD_DI

t

2.5

100

CSB_HIGH

t

CS Set Up Time, CS Low Before Rising Edge of CLK

CLK Set Up Time, CLK Low Before Rising Edge of CS

ns

SET_CSB

t

SET_CLK

0.2 V_CC

CS

t_{SET _CSB}

t_CLK

t_{SET_CLK}

0.8 V_CC

CLK

0,2 V_CC

0.2 V_CC

t_{CLK_HI}

t_{HOLD_DI}

t_{CLK _LO}

t_{SET_DI}

0.8 V_CC

DI

VALID

Figure 6. SPI Timing

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AMIS−30543

TYPICAL APPLICATION SCHEMATIC

D₁

100 nF

C₂

100 nF

C₃

100 nF

C₄

V_BAT

C₁

C₅

C₆

mF

100

R₂R₃

R₄

100 nF

VDD

32

VBB

14

VBB

27

220 nF

VCP

CPN

11

9

POR/WD

28

5

C₇

DIR

AMIS−30543

220 nF

NXT

10

4

CPP

DO

DI

31

2

MOTXP

25, 26

21, 22

CLK

MOTXN

mC

3

CS

13

12

6

M

MOTYP

MOTYN

CLR

ERR

SLA

15, 16

19, 20

7

R₁

C₈

1

23 24 29

17 18

GND

Figure 7. Typical Application Schematic AMIS−30543

TSTO

Table 7. EXTERNAL COMPONENTS LIST AND DESCRIPTION

Component

Function

Typ Value

100

Tolerance

−20 +80%

Unit

mF

C

V

Buffer Capacitor (Note 12)

Decoupling Block Capacitor

1

BB

C , C

100

nF

2

3

BB

(Note 13)

C

V

Buffer Capacitor

100

$20%

$1%

nF

kW

4

DD

C

Buffer Capacitor

5

C

Charge Pump Buffer Capacitor

Charge Pump Pumping Capacitor

Low Pass Filter SLA

220

6

C

220

7

C

1

8

R

Low Pass Filter SLA

5.6

1

R

2, 3,

R

Pullup Resistor Open Drain Output

Optional Reverse Protection Diode

4.7

$1%

4

D

MURD530

1

12.ESR < 1 W.

13.ESR < 50 mW.

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AMIS−30543

FUNCTIONAL DESCRIPTION

H−Bridge Drivers

transistors will be adapted such that excellent current−sense

accuracy is maintained. The R of the high−side

transistors remain unchanged; see Table 4 DC Parameters

for more details.

A full H−bridge is integrated for each of the two stator

windings. Each H−bridge consists of two low−side and two

high−side N−type MOSFET switches. Writing logic ‘0’ in

bit <MOTEN> disables all drivers (high−impedance).

Writing logic ‘1’ in this bit enables both bridges and current

can flow in the motor stator windings.

In order to avoid large currents through the H−bridge

switches, it is guaranteed that the top− and bottom−switches

of the same half−bridge are never conductive

simultaneously (interlock delay).

DS(on)

PWM Current Control

A PWM comparator compares continuously the actual

winding current with the requested current and feeds back

the information to a digital regulation loop. This loop then

generates a PWM signal, which turns on/off the H−bridge

switches. The switching points of the PWM duty−cycle are

synchronized to the on−chip PWM clock. The frequency of

the PWM controller can be doubled and an artificial jitter

can be added (see Table 12 SPI Control Parameter Overview

PWMJ). The PWM frequency will not vary with changes in

the supply voltage. Also variations in motor−speed or

load−conditions of the motor have no effect. There are no

external components required to adjust the PWM frequency.

A two−stage protection against shorts on motor lines is

implemented. In a first stage, the current in the driver is

limited. Secondly, when excessive voltage is sensed across

the transistor, the transistor is switched off.

In order to reduce the radiated/conducted emission,

voltage slope control is implemented in the output switches.

The output slope is defined by the gate−drain capacitance of

output transistor and the (limited) current that drives the

gate. There are two trimming bits for slope control (see

Table 12 SPI Control Parameter Overview EMC[1:0]).

The power transistors are equipped with so−called “active

diodes”: when a current is forced trough the transistor switch

in the reverse direction, i.e. from source to drain, then the

transistor is switched on. This ensures that most of the

current flows through the channel of the transistor instead of

through the inherent parasitic drain−bulk diode of the

transistor.

Automatic Forward and Slow−Fast Decay

The PWM generation is in steady−state using a

combination of forward and slow−decay. The absence of

fast−decay in this mode, guarantees the lowest possible

current−ripple “by design”. For transients to lower current

levels, fast−decay is automatically activated to allow

high−speed response. The selection of fast or slow decay is

completely transparent for the user and no additional

parameters are required for operation.

Depending on the desired current range and the

micro−step position at hand, the R

of the low−side

DS(on)

Icoil

Set value

Actual value

t

0

T_PWM

Forward & Slow Decay

Fast Decay & Forward

Figure 8. Forward and Slow/Fast Decay PWM

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AMIS−30543

Automatic Duty Cycle Adaptation

process is completely automatic and requires no additional

parameters for operation. The over−all current−ripple is

divided by two if PWM frequency is doubled (see Table 12

SPI Control Parameter Overview PWMF)

In case the supply voltage is lower than 2*Bemf, then the

duty cycle of the PWM is adapted automatically to > 50% to

maintain the requested average current in the coils. This

Icoil

Duty Cycle

<

50%

Duty Cycle< 50%

Duty Cycle> 50%

Actual value

Set value

t

Figure 9. Automatic Duty Cycle Adaption

T_PWM

Step Translator and Step Mode

step mode, subsequent translator positions are all in the same

column and increased or decreased with 1. Table 9 lists the

output current vs. the translator position.

The step translator provides the control of the motor by

means of SM[2:0], ESM[2:0], SPI register DIRCTRL and

input pins DIR and NXT. It is translating consecutive steps

in corresponding currents in both motor coils for a given step

mode.

One out of eleven possible stepping modes can be selected

through SPI−bits SM[2:0] and ESM[2:0] (see Table 12 SPI

Control Parameter Overview). After power−on or hard

reset, the coil−current translator is set to the default 1/32

micro−stepping at position ‘0’. When remaining in the same

As shown in Figure 10 the output current−pairs can be

projected approximately on a circle in the (I , I ) plane.

x

y

There are, however, two exceptions: uncompensated half

step and uncompensated full step. In these step modes the

currents are not regulated to a fraction of I

but are in all

max

intermediate steps regulated at 100%. In the (I , I ) plane the

x

y

current−pairs are projected on a square. Table 8 lists the

output current vs. the translator position for these cases.

Table 8. SQUARE TRANSLATOR TABLE FOR UNCOMPENSATED FULL STEP AND UNCOMPENSATED HALF

STEP

Stepmode ( SM[2:0] )

% of I

max

101

110

Uncompensated Half Step

Uncompensated Full Step

MSP[8:0]

Coil x

0

Coil y

0 0000 0000

0 0100 0000

0 1000 0000

0 1100 0000

1 0000 0000

1 0100 0000

1 1000 0000

1 1100 0000

0

1

2

3

4

5

6

7

−

1

−

2

−

3

−

0

100

0

100

0

−100

0

−100

100

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AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE

SM[2:0]

xxx

001

xxx

010

000

001

000

010

ESM[2:0]

000

011

000

100

000

xxx

011

xxx

100

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

0

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

000000000

000000001

000000010

000000011

000000100

000000101

000000110

000000111

000001000

000001001

000001010

000001011

000001100

000001101

000001110

000001111

000010000

000010001

000010010

000010011

000010100

000010101

000010110

000010111

000011000

000011001

000011010

000011011

000011100

000011101

000011110

000011111

000100000

000100001

000100010

000100011

000100100

000100101

000100110

000100111

000101000

000101001

000101010

0

100

99

1

2

1

2

3

4

1

2

5

6

3

7

9

8

4

1

2

3

4

5

10

11

12

13

15

16

17

18

20

21

22

23

24

25

27

28

29

30

31

33

34

35

36

37

38

39

41

42

43

44

45

46

47

48

49

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

5

99

6

3

99

7

99

98

8

4

1

98

9

98

97

10

11

12

13

14

15

16

17

18

19

20

21

5

97

96

6

96

95

7

94

93

8

2

1

92

91

9

90

89

10

88

87

www.onsemi.com

13

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

000101011

000101100

000101101

000101110

000101111

000110000

000110001

000110010

000110011

000110100

000110101

000110110

000110111

000111000

000111001

000111010

000111011

000111100

000111101

000111110

000111111

001000000

001000001

001000010

001000011

001000100

001000101

001000110

001000111

001001000

001001001

001001010

001001011

001001100

001001101

001001110

001001111

001010000

001010001

001010010

001010011

001010100

001010101

50

51

52

53

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

53

52

51

50

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

11

12

13

14

15

16

17

18

19

20

21

6

3

7

8

4

2

1

0

9

10

5

www.onsemi.com

14

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

86

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

001010110

001010111

001011000

001011001

001011010

001011011

001011100

001011101

001011110

001011111

001100000

001100001

001100010

001100011

001100100

001100101

001100110

001100111

001101000

001101001

001101010

001101011

001101100

001101101

001101110

001101111

001110000

001110001

001110010

001110011

001110100

001110101

001110110

001110111

001111000

001111001

001111010

001111011

001111100

001111101

001111110

001111111

010000000

43

87

88

49

48

47

46

45

44

43

42

41

39

38

37

36

35

34

33

31

30

29

28

27

25

24

23

22

21

20

18

17

16

15

13

12

11

10

9

87

88

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

22

11

88

89

90

89

91

90

92

23

24

25

26

27

28

29

30

31

32

90

93

91

94

91

95

92

96

12

13

14

15

16

6

3

92

97

93

98

93

99

94

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

94

95

96

97

98

7

98

99

100

7

6

5

4

2

1

8

4

2

1

0

www.onsemi.com

15

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

010000001

010000010

010000011

010000100

010000101

010000110

010000111

010001000

010001001

010001010

010001011

010001100

010001101

010001110

010001111

010010000

010010001

010010010

010010011

010010100

010010101

010010110

010010111

010011000

010011001

010011010

010011011

010011100

010011101

010011110

010011111

010100000

010100001

010100010

010100011

010100100

010100101

010100110

010100111

010101000

010101001

010101010

010101011

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

−1

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

−2

−4

33

34

35

36

37

38

39

40

41

42

−5

−6

−7

−9

17

18

19

20

21

−10

−11

−12

−13

−15

−16

−17

−18

−20

−21

−22

−23

−24

−25

−27

−28

−29

−30

−31

−33

−34

−35

−36

−37

−38

−39

−41

−42

−43

−44

−45

−46

−47

−48

−49

−50

9

10

5

www.onsemi.com

16

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

010101100

010101101

010101110

010101111

010110000

010110001

010110010

010110011

010110100

010110101

010110110

010110111

010111000

010111001

010111010

010111011

010111100

010111101

010111110

010111111

011000000

011000001

011000010

011000011

011000100

011000101

011000110

011000111

011001000

011001001

011001010

011001011

011001100

011001101

011001110

011001111

011010000

011010001

011010010

011010011

011010100

011010101

011010110

86

43

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

53

52

51

50

49

−51

−52

−53

−55

−56

−57

−58

−59

−60

−61

−62

−63

−64

−65

−66

−67

−68

−69

−70

−71

−72

−73

−74

−75

−76

−77

−78

−79

−80

−81

−82

−83

−84

−85

−86

−87

87

88

44

45

46

47

48

49

50

51

52

53

22

11

89

90

91

92

23

24

25

26

93

94

95

96

12

6

3

1

97

98

99

100

101

102

103

104

105

106

107

13

www.onsemi.com

17

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

011010111

011011000

011011001

011011010

011011011

011011100

011011101

011011110

011011111

011100000

011100001

011100010

011100011

011100100

011100101

011100110

011100111

011101000

011101001

011101010

011101011

011101100

011101101

011101110

011101111

011110000

011110001

011110010

011110011

011110100

011110101

011110110

011110111

011111000

011111001

011111010

011111011

011111100

011111101

011111110

011111111

100000000

100000001

48

47

46

45

44

43

42

41

39

38

37

36

35

34

33

31

30

29

28

27

25

24

23

22

21

20

18

17

16

15

13

12

11

10

9

−88

−89

−90

−91

−92

−93

−94

−95

−96

−97

−98

−99

−100

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

54

27

55

56

57

58

59

60

61

62

63

64

28

29

30

31

32

14

7

15

7

6

5

4

2

1

16

8

4

2

0

−1

www.onsemi.com

18

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

100000010

100000011

100000100

100000101

100000110

100000111

100001000

100001001

100001010

100001011

100001100

100001101

100001110

100001111

100010000

100010001

100010010

100010011

100010100

100010101

100010110

100010111

100011000

100011001

100011010

100011011

100011100

100011101

100011110

100011111

100100000

100100001

100100010

100100011

100100100

100100101

100100110

100100111

100101000

100101001

100101010

100101011

100101100

129

−2

−100

−99

−98

−97

−96

−95

−94

−93

−92

−91

−90

−89

−88

−87

−86

−4

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

65

−5

−6

−7

−9

66

67

68

69

70

71

72

73

74

75

33

−10

−11

−12

−13

−15

−16

−17

−18

−20

−21

−22

−23

−24

−25

−27

−28

−29

−30

−31

−33

−34

−35

−36

−37

−38

−39

−41

−42

−43

−44

−45

−46

−47

−48

−49

−50

−51

34

35

36

37

17

18

9

www.onsemi.com

19

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

100101101

100101110

100101111

100110000

100110001

100110010

100110011

100110100

100110101

100110110

100110111

100111000

100111001

100111010

100111011

100111100

100111101

100111110

100111111

101000000

101000001

101000010

101000011

101000100

101000101

101000110

101000111

101001000

101001001

101001010

101001011

101001100

101001101

101001110

101001111

101010000

101010001

101010010

101010011

101010100

101010101

101010110

101010111

−52

−53

−55

−56

−57

−58

−59

−60

−61

−62

−63

−64

−65

−66

−67

−68

−69

−70

−71

−72

−73

−74

−75

−76

−77

−78

−79

−80

−81

−82

−83

−84

−85

−86

−87

−88

−85

−84

−83

−82

−81

−80

−79

−78

−77

−76

−75

−74

−73

−72

−71

−70

−69

−68

−67

−66

−65

−64

−63

−62

−61

−60

−59

−58

−57

−56

−55

−53

−52

−51

−50

−49

−48

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

76

77

78

79

80

81

82

83

84

85

38

19

39

40

41

42

20

10

5

2

21

www.onsemi.com

20

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

101011000

101011001

101011010

101011011

101011100

101011101

101011110

101011111

101100000

101100001

101100010

101100011

101100100

101100101

101100110

101100111

101101000

101101001

101101010

101101011

101101100

101101101

101101110

101101111

101110000

101110001

101110010

101110011

101110100

101110101

101110110

101110111

101111000

101111001

101111010

101111011

101111100

101111101

101111110

101111111

110000000

110000001

110000010

172

86

43

−88

−89

−90

−91

−92

−93

−94

−95

−96

−97

−98

−99

−100

−47

−46

−45

−44

−43

−42

−41

−39

−38

−37

−36

−35

−34

−33

−31

−30

−29

−28

−27

−25

−24

−23

−22

−21

−20

−18

−17

−16

−15

−13

−12

−11

−10

−9

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

87

88

89

90

91

92

93

94

95

96

44

45

46

47

48

22

11

23

−7

−6

−5

−4

−2

−1

24

12

6

3

0

1

2

www.onsemi.com

21

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

110000011

110000100

110000101

110000110

110000111

110001000

110001001

110001010

110001011

110001100

110001101

110001110

110001111

110010000

110010001

110010010

110010011

110010100

110010101

110010110

110010111

110011000

110011001

110011010

110011011

110011100

110011101

110011110

110011111

110100000

110100001

110100010

110100011

110100100

110100101

110100110

110100111

110101000

110101001

110101010

110101011

110101100

110101101

−100

−99

−98

−97

−96

−95

−94

−93

−92

−91

−90

−89

−88

−87

−86

−85

4

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

97

5

6

7

9

98

49

10

11

12

13

15

16

17

18

20

21

22

23

24

25

27

28

29

30

31

33

34

35

36

37

38

39

41

42

43

44

45

46

47

48

49

50

51

52

99

100

101

102

103

104

105

106

107

50

51

52

53

25

26

13

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22

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

460

461

462

463

464

465

466

467

468

469

470

471

472

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

110101110

110101111

110110000

110110001

110110010

110110011

110110100

110110101

110110110

110110111

110111000

110111001

110111010

110111011

110111100

110111101

110111110

110111111

111000000

111000001

111000010

111000011

111000100

111000101

111000110

111000111

111001000

111001001

111001010

111001011

111001100

111001101

111001110

111001111

111010000

111010001

111010010

111010011

111010100

111010101

111010110

111010111

111011000

215

−84

−83

−82

−81

−80

−79

−78

−77

−76

−75

−74

−73

−72

−71

−70

−69

−68

−67

−66

−65

−64

−63

−62

−61

−60

−59

−58

−57

−56

−55

−53

−52

−51

−50

−49

−48

−47

53

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

108

54

27

109

110

111

112

113

114

115

116

117

118

55

56

57

58

59

28

14

7

3

29

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23

AMIS−30543

Table 9. CIRCULAR TRANSLATOR TABLE (continued)

SM[2:0]

010

xxx

001

xxx

010

000

001

000

011

000

100

000

xxx

011

xxx

100

ESM[2:0]

000

% of

Imax

Comp

full

2ph

Comp

full

1ph

Comp

1/2

1/128

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

501

502

503

504

505

506

507

508

509

510

511

1/64

1/32

1/16

1/8

1/4

Coil X

Coil Y

MSP[8:0]

111011001

111011010

111011011

111011100

111011101

111011110

111011111

111100000

111100001

111100010

111100011

111100100

111100101

111100110

111100111

111101000

111101001

111101010

111101011

111101100

111101101

111101110

111101111

111110000

111110001

111110010

111110011

111110100

111110101

111110110

111110111

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

−46

−45

−44

−43

−42

−41

−39

−38

−37

−36

−35

−34

−33

−31

−30

−29

−28

−27

−25

−24

−23

−22

−21

−20

−18

−17

−16

−15

−13

−12

−11

−10

−9

89

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

90

119

120

121

122

123

124

125

126

127

90

91

92

60

61

62

63

30

15

92

93

94

95

96

97

98

31

98

99

100

−7

−6

−5

−4

−2

−1

www.onsemi.com

24

AMIS−30543

I_Y

Start = 0

Step 1

Step 2

Step 1

Step 3

Step 2

I_X

Step 3

1/4^thmicro step

Uncompensated

half step

Compensated

half step

I_Y

Step 3

Start = 0

Step 3

Step 1

I_X

Step 1

Step 2

Step 1

Step 2

Uncompensated

full step

Compensated full

step, 1 phase on

Compensated full

step, 2 phase on

Figure 10. Translator Table: Circular and Square

Direction

Parameter Overview), the next step is initiated either on the

rising edge or the falling edge of the NXT input.

The direction of rotation is selected by means of following

combination of the DIR input pin and the SPI−controlled

direction bit <DIRCTRL>. (see Table 12 SPI Control

Parameter Overview)

Translator Position

The translator position MSP[8:0] can be read in SPI Status

Register 3 and Status Register 4 (See Table 14 SR3 and

th

NXT Input

SR4). This is a 9−bit number equivalent to the 1/128

Changes on the NXT input will move the motor current

one step up/down in the translator table (even when the

micro−step (see Table 9 “Circular Translator Table”). The

translator position is updated immediately following a NXT

trigger.

motor is disabled: <MOTEN>

= 0). Depending on the

NXT−polarity bit <NXTP> (see Table 12 SPI Control

NXT

Update

Translator Position

Update

Translator Position

Figure 11. Translator Position Timing Diagram

Synchronization of Step Mode and NXT Input

When step mode is re−programmed to another resolution

(Figure 12), then this is put in effect immediately upon the

first arriving “NXT” input. If the micro−stepping resolution

is increased, the coil currents will be regulated to the nearest

micro−step, according to the fixed grid of the increased

resolution. If however the micro−stepping resolution is

decreased, then it is possible to introduce an offset (or phase

shift) in the micro−step translator table.

If the step resolution is decreased at a translator table

position that is shared both by the old and new resolution

setting, then the offset is zero and micro−stepping is

proceeds according to the translator table.

If the translator position is not shared both by the old and

new resolution setting, then the micro−stepping proceeds

with an offset relative to the translator table (See Figure 12

right hand side).

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25

AMIS−30543

Change from lower to higher resolution

Iy Iy

Change from higher to lower resolution

Iy Iy

DIR

NXT1

NXT2

NXT1

endpos

startpos

endpos

NXT3

NXT4

startpos

NXT2

Ix

NXT3

1/8^thstep

Halfstep

1/4^thstep

Figure 12. NXT−Step Mode Synchronization

Halfstep

PC20070604.6

Left: Change from lower to higher resolution. The left−hand side depicts the ending half−step position during which a new

step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the

micro−step position.

Right: Change from higher to lower resolution. The left−hand side depicts the ending micro−step position during which a new

step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the

half−step position.

Note: It is advised to reduce the micro−stepping resolution only at micro−step positions that overlap with desired micro−step

positions of the new resolution.

Programmable Peak−Current

The amplitude of the current waveform in the motor coils

Overview). Whenever this parameter is changed, the

coil−currents will be updated immediately at the next PWM

period. Figure 13 presents the Peak−Current and Current

Ratings in conjunction to the Current setting CUR[4:0].

(coil peak current = I ) is adjusted by means of an SPI

max

parameter “CUR[4:0]” (see Table 12 SPI Control Parameter

Peak Current

3090 mA

Current Range 3

CUR[4:0] = 16 −> 25

1205 mA

Current Range 2

CUR[4:0] = 10 −> 15

680 mA

305 mA

Current Range 1

CUR[4:0] = 3 −> 9

Current Range 0

CUR[4:0] = 0 −> 2

0

2

9

15

25

CUR[4:0]

Figure 13. Programmable Peak−Current Overview

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26

AMIS−30543

Speed and Load Angle Output

current zero crossings”. Per coil, two zero−current positions

exist per electrical period, yielding in total four zero−current

observation points per electrical period.

The SLA−pin provides an output voltage that indicates the

level of the Back−e.m.f. voltage of the motor. This

Back−e.m.f. voltage is sampled during every so−called ”coil

V_BEMF

I_COIL

t

ZOOM

Coil Current Zero Crossing

Current Decay

Zero Current

I_COIL

t

V _COIL

Voltage Transient

V_BB

|V_BEMF

|

t

Figure 14. Principle of Bemf Measurement

Because of the relatively high recirculation currents in the

coil during current decay, the coil voltage V shows a

behavior of the coil voltage is not visible anymore, this mode

generates smoother Back e.m.f. input for post−processing,

e.g. by software.

COIL

transient behavior. As this transient is not always desired in

application software, two operating modes can be selected

by means of the bit <SLAT>(see “SLA−transparency” in

Table 12 SPI Control Parameter Overview). The SLA pin

shows in “transparent mode” full visibility of the voltage

transient behavior. This allows a sanity−check of the

speed−setting versus motor operation and characteristics

and supply voltage levels. If the bit “SLAT” is cleared, then

only the voltage samples at the end of each coil current zero

crossing are visible on the SLA−pin. Because the transient

In order to bring the sampled Back e.m.f. to a descent

output level (0 V to 5 V), the sampled coil voltage V

is

COIL

divided by 2 or by 4. This divider is set through an SPI bit

<SLAG>. (see Table 12 SPI Control Parameter Overview)

The following drawing illustrates the operation of the

SLA−pin and the transparency−bit. “PWMsh” and “I

=

COIL

0” are internal signals that define together with SLAT the

sampling and hold moments of the coil voltage.

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27

AMIS−30543

Ssh

Sh

div2

div4

V_COIL

buf

SLA−pin

Ch

Csh

Icoil=0

SLAT

PWMsh

NOT(Icoil=0)

PWMsh

Icoil=0

SLAT

V_COIL

t

SLA−pin

last sample

is retained

V_BEMF

retain last sample

previous output is kept at SLA pin

t

SLAT = 1 => SLA−pin is “transparent” during

sampling @ Coil Current Zero

SLAT = 0 => SLA−pin is not “transparent” during

sampling @ Coil Current Zero Crossing.

V

BEMF

Crossing. SLA−pin is updated “real−time”.

SLA−pin is updated when leaving current−less state.

Figure 15. Timing Diagram of SLA−Pin

Warning, Error Detection and Diagnostics

Feedback

Open Coil/Current Not Reached Detection

Open coil detection is based on the observation of 100%

duty cycle of the PWM regulator. If in a coil 100% duty cycle

is detected for longer than 200 ms then the related driver

transistors are disabled (high−impedance) and an

appropriate bit in the SPI status register is set (<OPENX>or

<OPENY>). (Table 14)

When the resistance of a motor coil is very large and the

supply voltage is low, it can happen that the motor driver is

not able to deliver the requested current to the motor. Under

these conditions the PWM controller duty cycle will be

100% and after 200 ms the error pin and <OPENX>,

<OPENY> will flag this situation (motor current is kept

alive). This feature can be used to test if the operating

conditions (supply voltage, motor coil resistance) still allow

reaching the requested coil−current or else the coil current

should be reduced.

Thermal Warning and Shutdown

When junction temperature rises above T , the thermal

TW

warning bit <TW> is set (Table 14 SPI Status registers

Address SR0). If junction temperature increases above

thermal shutdown level, then the circuit goes in “Thermal

Shutdown” mode (<TSD>) and all driver transistors are

disabled (high impedance) (see Table 14 SPI Status registers

Address SR2). The conditions to reset flag <TSD>is to be

at a temperature lower than T and to clear the <TSD>flag

tw

by reading it using any SPI read command.

Overcurrent Detection

The overcurrent detection circuit monitors the load

current in each activated output stage. If the load current

exceeds the over−current detection threshold, then the

overcurrent flag is set and the drivers are switched off to

reduce the power dissipation and to protect the integrated

circuit. Each driver transistor has an individual detection bit

(see Table 14 SPI Status Registers Address SR1 and SR2:

<OVCXij> and <OVCYij>). Error condition is latched

and the microcontroller needs to clean the status bits to

reactivate the drivers.

Charge Pump Failure

The charge pump is an important circuit that guarantees

low R

for all drivers, especially for low supply

DS(on)

voltages. If supply voltage is too low or external components

are not properly connected to guarantee R of the

DS(on)

drivers, then the bit <CPFAIL>is set (Table 14). Also after

POR the charge pump voltage will need some time to exceed

the required threshold. During that time <CPFAIL>will be

set to “1”.

Note: Successive reading the SPI Status Registers 1 and 2 in

case of a short circuit condition, may lead to damage to the

drivers.

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28

AMIS−30543

Error Output

circuitry, the specified I

should be reduced with the

load

This is a digital output to flag a problem to the external

microcontroller. The signal on this output is active low and

the logic combination of:

consumption of internal circuitry (unloaded outputs) and the

loads connected to logic outputs. See Table 4. DC

parameters

NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR

Power−On Reset (POR) Function

The open drain output pin POR/WD provides an “active

low” reset for external purposes. At powerup of

AMIS−30543, this pin will be kept low for some time to reset

for example an external microcontroller. A small analogue

filter avoids resetting due to spikes or noise on the V

supply.

Logic Supply Regulator

AMIS−30543 has an on−chip 5 V low−drop regulator

with external capacitor to supply the digital part of the chip,

some low−voltage analog blocks and external circuitry. The

voltage level is derived from an internal bandgap reference.

To calculate the available drive−current for external

DD

VBB

t

t_PD

VDD

t_PU

V_DDH

V_DDL

t

< t_RF

POR/WD pin

t_POR

t_RF

Figure 16. Power−on−Reset Timing Diagram

Watchdog Function

The voltage regulator and charge pump remains

functional during and after the reset and the POR/WD pin is

not activated. Watchdog function is reset completely.

The watchdog function is enabled/disabled through

<WDEN> bit (Table 11: SPI CONTROL REGISTERS).

Once this bit has been set to “1” (watchdog enable), the

microcontroller needs to re−write this bit to clear an internal

timer before the watchdog timeout interval expires. In case

the timer is activated and WDEN is acknowledged too early

Sleep Mode

The bit <SLP>in SPI Control Register 2 (See Table 10)

is provided to enter a so−called “sleep mode”. This mode

allows reduction of current−consumption when the motor is

not in operation. The effect of sleep mode is as follows:

• The drivers are put in HiZ

• All analog circuits are disabled and in low−power mode

• All internal registers are maintaining their logic content

• NXT and DIR inputs are forbidden

• SPI communication remains possible (slight current

increase during SPI communication)

• Oscillator and digital clocks are silent, except during

SPI communication

(before t

) or not within the interval (after t

), then

WDPR

WDTO

a reset of the microcontroller will occur through POR/WD

pin. In addition, a warm/cold boot bit <WD>is available (see

Tables 14 and 15) for further processing when the external

microcontroller is alive again.

CLR pin (=Hard Reset)

Logic 0 on CLR pin allows normal operation of the chip.

To reset the complete digital inside AMIS−30543, the input

CLR needs to be pulled to logic 1 during minimum time

given by t

(Table 5 AC Parameters). This reset function

CLR

clears all internal registers without the need of a

power−cycle, except in sleep mode. Logic 0 on CLR pin

resumes normal operation again.

• Registers cannot be cleared by using the CLR pin

VBB should be minimum 9 V to be able to enter

Sleep Mode.

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29

AMIS−30543

The voltage regulator remains active but with reduced

current−output capability (I ). The watchdog timer

Normal operation is resumed after writing logic ‘0’ to bit

<SLP>. A startup time is needed for the charge pump to

LOADSLP

stops running and it’s value is kept in the counter. Upon

leaving sleep mode, this timer continues from the value it

had before entering sleep mode.

stabilize. After this time, NXT commands can be issued.

VBB

t

VDD

V_DDH

t_PU

t

t_POR

POR/WD pin

t_WDRD

t_POR

t_DSPI

Enable WD

= t_WDPRor = t_WDTO

> t_WDPRand < t_WDTO

Acknowledge WD

t

t_WDTO

WD timer

t

Figure 17. Watchdog Timing Diagram

NOTE:

t

is the time needed by the external microcontroller to shift−in the <WDEN> bit after a powerup.

DSPI

The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (See also Table 11: SPI

CONTROL REGISTERS. The timing is given in Table 10 below.

Table 10. WATCHDOG TIMEOUT INTERVAL AS FUNCTION OF WDT[3.0]

Index WDT[3:0]

0000

t

(ms)

Index WDT[3:0]

1000

t

(ms)

WDTO

0

1

2

3

4

5

6

7

32

8

288

0001

64

9

1001

320

352

384

416

448

480

512

0010

96

10

11

12

13

14

15

1010

0011

128

160

192

224

256

1011

0100

1100

0101

1101

0110

1110

0111

1111

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30

AMIS−30543

SPI INTERFACE

The serial peripheral interface (SPI) allows an external

DO signal is the output from the Slave (AMIS−30543), and

DI signal is the output from the Master. A chip select line

(CS) allows individual selection of a Slave SPI device in a

multiple−slave system. The CS line is active low. If

AMIS−30543 is not selected, DO is pulled up with the

external pull up resistor. Since AMIS−30543 operates as a

Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks

data out on the falling edge and samples data in on rising

edge of clock. The Master SPI port must be configured in

MODE 0 too, to match this operation. The SPI clock idles

low between the transferred bytes.

microcontroller (Master) to communicate with

AMIS−30543. The implemented SPI block is designed to

interface directly with numerous micro−controllers from

several manufacturers. AMIS−30543 acts always as a Slave

and can’t initiate any transmission. The operation of the

device is configured and controlled by means of SPI

registers which are observable for read and/or write from the

Master.

SPI Transfer Format and Pin Signals

During a SPI transfer, data is simultaneously transmitted

(shifted out serially) and received (shifted in serially). A

serial clock line (CLK) synchronizes shifting and sampling

of the information on the two serial data lines (DO and DI).

The diagram below is both a Master and a Slave timing

diagram since CLK, DO and DI pins are directly connected

between the Master and the Slave.

# CLK cycle

CS

1

2

3

4

5

6

7

8

CLK

DI

MSB

6

5

4

3

2

1

LSB

DO

Figure 18. Timing Diagram of a SPI Transfer

NOTE: At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the addressed internal SPI

register. The internal SPI registers are updated at the first rising edge of the AMIS−30543 system clock when CS = High

Transfer Packet:

Serial data transfer is assumed to follow MSB first rule.

The transfer packet contains one or more bytes.

BYTE 1

BYTE 2

Data

Command and SPI Register Address

MSB

LSB

MSB

D7

LSB

D0

CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0

D6

D5

D4

D3

D2

D1

Command

SPI Register Address

Figure 19. SPI Transfer Packet

Byte 1 contains the Command and the SPI Register

Address and indicates to AMIS−30543 the chosen type of

operation and addressed register. Byte 2 contains data, or

sent from the Master in a WRITE operation, or received

from AMIS−30543 in a READ operation.

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31

AMIS−30543

Two command types can be distinguished in the

READ command. This READ command contains the

address of the SPI register to be read out. At the falling edge

of the eight clock pulse the data−out shift register is updated

with the content of the corresponding internal SPI register.

In the next 8−bit clock pulse train this data is shifted out via

DO pin. At the same time the data shifted in from DI

(Master) should be interpreted as the following successive

command or the same command.

communication between master and AMIS−30543:

• READ from SPI Register with address ADDR[4:0]:

CMD2 = “0”

• WRITE to SPI Register with address ADDR[4:0]:

CMD2 = “1”

READ Operation

If the Master wants to read data from Status or Control

Registers, it initiates the communication by sending a

Registers are updated with internal status at the rising

edge of the internal AMIS−30543 clock when CS = 1

CS

COMMAND

DI

READ DATA from ADDR 1

DATA from previous command or

NOT VALID after POR or RESET

DATA

DO

OLD DATA or NOT VALID

DATA from ADDR1

Figure 20. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master

All 4 Status Registers (see SPI Registers) contain 7 data

bits and a parity check bit. The most significant bit (D7)

represents a parity of D[6:0]. If the number of logical ones

in D[6:0] is odd, the parity bit D7 equals “1”. If the number

of logical ones in D[6:0] is even then the parity bit D7 equals

“0”. This simple mechanism protects against noise and

increases the consistency of the transmitted data. If a parity

check error occurs it is recommended to initiate an

additional READ command to obtain the status again.

Also the Control Registers can be read out following the

same routine. Control Registers don’t have a parity check.

The CS line is active low and may remain low between

successive READ commands as illustrated in Figure 22.

There is however one exception. In case an error condition

is latched in one of Status Registers (see SPI Registers) the

ERR pin is activated (See Section Error Output). This signal

flags a problem to the external microcontroller. By reading

the Status Registers information about the root cause of the

problem can be determined. After this READ operation the

Status Registers are cleared. Because the Status Registers

and ERR pin (see SPI Registers) are only updated by the

internal system clock when the CS line is high, the Master

should force CS high immediately after the READ

operation. For the same reason it is recommended to keep

the CS line high always when the SPI bus is idle.

WRITE Operation

If the Master wants to write data to a Control Register it

initiates the communication by sending a WRITE

command. This contains the address of the SPI register to

write to. The command is followed with a data byte. This

incoming data will be stored in the corresponding Control

Register after CS goes from low to high! AMIS−30543

responds on every incoming byte by shifting out via DO the

data stored in the last received address.

It is important that the writing action (command − address

and data) to the Control Register is exactly 16 bits long. If

more or less bits are transmitted the complete transfer packet

is ignored.

A WRITE command executed for a read−only register

(e.g. Status Registers) will not affect the addressed register

and the device operation.

Because after a power−on−reset the initial address is

unknown the data shifted out via DO is not valid.

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32

AMIS−30543

The NEW DATA is written into the corresponding

internal register at the rising edge of CS

CS

DI

COMMAND

DATA

NEW DATA for ADDR3

WRITE DATA to ADDR3

DATA from previous command or

NOT VALID after POR or RESET

DATA

DO

OLD DATA or NOT VALID

OLD DATA from ADDR3

Figure 21. Single WRITE Operation Where DATA from the Master is Written in SPI Register with Address 3

Examples of combined READ and WRITE

Operations

In the following examples successive READ and WRITE

operations are combined. In Figure 22 the Master first reads

the status from Register at ADDR4 and at ADDR5 followed

by writing a control byte in Control Register at ADDR2.

Note that during the write command the old data of the

pointed register is returned at the moment the new data is

shifted in

Registers are updated with the internal

status at the rising edge of the internal

AMIS−30543 clock when CS = 1

The NEW DATA is written into the

corresponding internal register at

the rising edge of CS

CS

COMMAND

DATA

COMMAND

WRITE DATA

to ADDR2

READ DATA

from ADDR4

READ DATA

from ADDR5

NEW DATA

for ADDR2

DI

DATA from previous

command or NOT VALID

after POR or RESET

DATA

from ADDR4

OLD DATA

from ADDR2

OLD DATA

or NOT VALID

DATA

from ADDR5

DO

Figure 22. 2 Successive READ Commands Followed by a WRITE Command

After the write operation the Master could initiate a read

back command in order to verify the data correctly written

as illustrated in Figure 23. During reception of the READ

command the old data is returned for a second time. Only

after receiving the READ command the new data is

transmitted. This rule also applies when the master device

wants to initiate an SPI transfer to read the Status Registers.

Because the internal system clock updates the Status

Registers only when CS line is high, the first read out byte

might represent old status information.

www.onsemi.com

33

AMIS−30543

The NEW DATA is written into the

corresponding internal register at

the rising edge of CS

Registers are updated with

the internal status at the

rising edge of CS

CS

DI

COMMAND

DATA

COMMAND

READ DATA

from ADDR2

WRITE DATA

to ADDR2

NEW DATA

forADDR2

COMMAND

DATA from previous

command or NOT VALID

after POR or RESET

DATA

NEW DATA

from ADDR2

OLD DATA

or NOT VALID

OLD DATA

fromADDR2

OLD DATA

from ADDR2

DO

Figure 23. A WRITE Operation Where DATA from the Master is Written in SPI Register with Address 2 Followed by

a READ Back Operation to Confirm a Correct WRITE Operation

NOTE: The internal data−out shift buffer of AMIS−30543 is updated with the content of the selected SPI register only at the last (every

eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be

written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.

Table 11. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to “0” after power−on or hard

reset)

Structure

Bit 7

R/W

0

Bit 6

R/W

0

Bit 5

R/W

0

Bit 4

R/W

0

Bit 3

R/W

0

Bit 2

Bit 1

R/W

0

Bit 0

R/W

0

Content

Access

Reset

Data

R/W

0

−

Address

WR (00h)

CR0 (01h)

CR1 (02h)

CR2 (03h)

CR3 (09h)

WDEN

WDT[3:0]

−

Data

SM[2:0]

NXTP

SLP

CUR[4:0]

PWMJ

−

Data

DIRCTRL

MOTEN

−

SLAG

−

SLAT

−

PWMF

EMC[1:0]

Data

−

Data

−

ESM[2:0]

Where:

R/W

Reset:

Read and Write access

Status after power−On or hard reset

www.onsemi.com

34

AMIS−30543

Table 12. SPI CONTROL PARAMETER OVERVIEW

Symbol

Description

Status

<DIRCTRL> = 0

Value

DIRCTRL

Controls the direction of rotation (in combination with

logic level on input DIR)

<DIR> = 0

<DIR> = 1

CW motion (Note 15)

<DIRCTRL> = 1

<DIRCTRL> = 0

<DIRCTRL> = 1

CCW motion

(Note 15)

CCW motion

(Note 15)

CW motion (Note 15)

NXTP

Selects if NXT triggers on rising or falling edge

<NXTP> = 0

<NXTP> = 1

00

Trigger on rising edge

Trigger on falling edge

Very Fast

EMC[1:0]

Turn On – Turn−off Slopes of motor driver (Note 14)

01

Fast

10

Slow

11

Very Slow

SLAT

SLAG

Speed load angle transparency bit

Speed load angle gain setting

<SLAT> = 0

<SLAT> = 1

<SLAG> = 0

<SLAG> = 1

<PWMF> = 0

<PWMF> = 1

<PWMJ> = 0

<PWMJ> = 1

000

SLA is not transparent

SLA is transparent

Gain = 0.5

Gain = 0.25

PWMF

PWMJ

SM[2:0]

Enables doubling of the PWM frequency (Note 14)

Enables jittery PWM

Default Frequency

Double Frequency

Jitter disabled

Jitter enabled

Stepmode (only valid if ESM[2:0] = 000)

1/32 Micro − Step

1/16 Micro − Step

1/8 Micro − Step

001

010

011

1/4 Micro − Step

100

Compensated Half Step

Uncompensated Half Step

Uncompensated full step

1/128 Micro−Step

1/64 Micro−Step

101

110

111

001

ESM[2:0]

Stepmode

010

011

Compensated full step, 2 phase on

Compensated full step, 1 phase on

Stepping mode defined by SM[2:0]

Active mode

100

Other

SLP

Enables sleep mode (if V > 9 V)

<SLP> = 0

<SLP> = 1

<MOTEN> = 0

<MOTEN> = 1

BB

Sleep mode

MOTEN

Activates the motor driver outputs

Drivers disabled

Drivers enabled

14.The typical values can be found in Table 4: DC Parameters and in Table 5: AC parameters

15.Depending on the wiring of the motor connections

www.onsemi.com

35

AMIS−30543

CUR[4:0]

Selects IMCmaxpeak. This is the peak or amplitude of the regulated current waveform in the motor coils.

Table 13. SPI CONTROL PARAMETER OVERVIEW CUR[4:0]

Current Range

Current (mA)

Current Range

Current (mA)

(Note 17)

(Note 16)

(Note 17)

(Note 16)

Index CUR[4:0]

16

0

1

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

132

245

355

395

445

485

540

585

640

715

780

870

955

1060

1150

1260

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

1405

1520

1695

1850

2070

2240

2440

2700

2845

3000

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0

1

2

3

4

5

6

7

3

8

9

10

11

12

13

14

15

2

16.Typical current amplitude at T = 125

J

17.Reducing the current over different current ranges might trigger overcurrent detection. See dedicated application note for solutions

SPI Status Register Description

All 5 SPI status registers have Read Access and are default to “0” after power−on or hard reset.

Table 14. SPI STATUS REGISTERS

Structure

Bit 7

R

Bit 6

R

Bit 5

R

Bit 4

R

Bit 3

R

Bit 2

Bit 1

Bit 0

Content

Access

R

0

R

0

−

R

0

−

Reset

0

Address

SR0 (04h)

SR1 (05h)

SR2 (06h)

SR3 (07h)

SR4 (0Ah)

Data is not latched

Data is latched

Data is not latched

PAR

TW

CPFAIL

OVCXPB

OVCYPB

WD

OPENX

OVCXNB

OVCYNB

OPENY

−

OVCXPT

OVCYPT

OVCXNT

OVCYNT

TSD

MSP[8:2]

MSP[6:0]

Where:

R

Read only mode access

Reset

PAR

Status after power−on or hard reset

Parity check

www.onsemi.com

36

AMIS−30543

Table 15. SPI STATUS FLAGS OVERVIEW

Length

Reset

State

(bit)

Mnemonic

Flag

Comment

CPFail

Charge pump failure

1

Status Register 0

‘0’ = no failure

‘1’ = failure: indicates that the charge pump does

not reach the required voltage level. Note 1

‘0’

MSP[8:0]

Micro−step position

9

Status Register 3 and Translator micro step position

Status Register 4

‘000000000’

OPENX

OPENY

OPEN Coil X

OPEN Coil Y

1

Status Register 0

Status Register 1

‘1’ = Open coil detected

‘0’

OVCXNB OVer Current on X

H−bridge; MOTXN

terminal; Bottom

tran.

‘0’ = no failure

‘1’ = failure: indicates that over current is detected

at bottom transistor XN−terminal

OVCXNT OVer Current on X

H−bridge; MOTXN

1

Status Register 1

‘0’ = no failure

‘1’ = failure: indicates that over current is detected

at top transistor XN−terminal

‘0’

terminal; Top transist.

OVCXPB OVer Current on X

H−bridge; MOTXP

terminal; Bottom

tran.

‘0’ = no failure

‘1’ = failure: indicates that over current is detected

at bottom transistor XP−terminal

OVCXPT

OVer Current on X

H−bridge; MOTXP

terminal; Top transist.

1

Status Register 1

Status Register 2

‘0’ = no failure

‘1’ = failure: indicates that over current is detected

at top transistor XP−terminal

‘0’

OVCYNB OVer Current on Y

H−bridge; MOTYN

terminal; Bottom

tran.

‘0’ = no failure

‘1’ = failure: indicates that over current is detected

at bottom transistor YN−terminal

OVCYNT OVer Current on Y

H−bridge; MOTYN

1

Status Register 2

‘0’ = no failure

‘1’ = failure: indicates that over current is detected

at top transistor YN−terminal

‘0’

terminal; Top transist.

OVCYPB OVer Current on Y

H−bridge; MOTYP

terminal; Bottom

tran.

‘0’ = no failure

‘1’ = failure: indicates that over current is detected

at bottom transistor YP−terminal

OVCYPT

OVer Current on Y

H−bridge; MOTYP

terminal; Top transist.

1

Status Register 2

‘0’ = no failure

‘1’ = failure: indicates that over current is detected

at top transistor YP−terminal

‘0’

TSD

TW

Thermal shutdown

Thermal warning

Watchdog event

1

Status Register 2

Status Register 0

‘0’

WD

‘1’ = watchdog reset after time−out

NOTE: WD − This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to “1” after reset,

it means that a watchdog reset occurred (warm boot) instead of POR (cold boot). WD bit will be cleared only when the master

writes “0” to WDEN bit.

Table 16. ORDERING INFORMATION

Temperature

†

Range

Part No.

AMIS30543C5431G

Peak Current

Package

Shipping

3000 mA

−40°C to 125°C

NQFP−32 (7 x 7 mm)

(Pb−Free)

Units / Tubes

AMIS30543C5431RG

3000 mA

−40°C to 125°C

NQFP−32 (7 x 7 mm)

(Pb−Free)

Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

37

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFN32 7x7, 0.65P

CASE 485J−02

ISSUE E

DATE 30 JAN 2013

1

32

NOTES:

B

E

D

A

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

SCALE 2:1

L

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.25MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN 1

INDICATOR

L1

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

MILLIMETERS

DIM MIN

0.80

A1 0.00

MAX

1.00

0.05

A

0.15

C

2X

A3

0.20 REF

b

D

0.25

7.00 BSC

0.35

EXPOSED Cu

MOLD CMPD

2X

0.15 C

D2 5.16

5.36

TOP VIEW

E

7.00 BSC

5.36

DETAIL B

A3

0.10

C

DETAIL B

−−−

0.50

0.15

ALTERNATE

A

CONSTRUCTION

0.08

A1

SIDE VIEW

D2

SEATING

PLANE

NOTE 4

GENERIC

MARKING DIAGRAM*

C

DETAIL A

32X

1

L

K

9

16

XXXXXXXXX

AWLYYWWG

17

8

1

E2

A

= Assembly Location

WL = Wafer Lot

YY = Year

24

32

25

WW = Work Week

32X

b

0.10 C

e

e/2

G

= Pb−Free Package

A B

0.05 C

*This information is generic. Please refer

to device data sheet for actual part

marking.

NOTE 3

BOTTOM VIEW

RECOMMENDED

Pb−Free indicator, “G” or microdot “ G”,

MOUNTING FOOTPRINT

may or may not be present.

7.30

5.46

32X

0.63

PACKAGE

OUTLINE

1

5.46

7.30

32X

0.40

0.65

PITCH

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON11451D

QFN32 7X7, 0.65MM PITCH

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

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


型号：	AMIS30543C5431RG
厂家：	ONSEMI
描述：	微步进电机驱动器电动机控制电机驱动驱动器
文件：	总39页 (文件大小：584K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AMIS30543C5431RG [ONSEMI]

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