AP0201AT_技术文档

AP0201AT High-Dynamic

Range (HDR) Image Signal

Processor (ISP)

AP0201AT

GENERAL DESCRIPTION

www.onsemi.com

ON Semiconductor’s AP0201AT Image Signal Processor (ISP) is

optimized for use with HDR (High Dynamic Range) sensors. The

AP0201AT provides full auto−functions support (AWB and AE) and

ALTM (Adaptive Local Tone Mapping) to enhance HDR images and

advanced noise reduction which enables excellent low−light

performance.

Table 1. KEY PERFORMANCE PARAMETERS

VFBGA100, 7x7

CASE 138AH

Parameter

Image Sensor Interfaces

Input Data Format

Value

Parallel and HiSPi

MARKING DIAGRAM

Parallel: 12−bit SDR (linear) or 12−bit

HDR companded

HiSPI: 12−bit SDR (linear) or 12/14−bit

HDR companded

Output Interface

Ethernet−MII, RMII, GMII

H.264, MJPEG

Output Format

Maximum Resolution

Input Clock Range

Maximum Frame Rate

Output Ethernet Data Rate

1920×1080 (2.0 Mp)

10−29 MHz

XXXXXXXXXXX

= Laser Marking

1080p30, 960p45 and 720p60

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of

this data sheet.

Mll: 100 Mb/S

RMII: 100 Mb/s

GMII: 1 Gb/S at 2.5 V or higher

IO voltage

Supply Voltage

V

IO_S

IO_H

_REG

1.8 or 2.8 V

nominal

DD

• Auto Exposure, Auto White Balance,

50/60 Hz Auto Flicker Detection and

Avoidance

• Adaptive Local Tone Mapping (ALTM)

• Configurable through Low−cost SPI Flash

and EEPROM Devices

• Up to 7 GPIO

V

DD

1.8 or 2.8 or 3.3 V

nominal

V

DD

V

DD

V

DD

V

DD

V

DD

1.8 V nominal

1.2 V nominal

2.8 V nominal

_PLL

_PHY

• Fail−Safe IO

• Multi−Camera Synchronization Support

• MJPEG Encoding (8−bit)

IO_OTPM

2.5 to 3.3 V

nominal

Operating Temperature

Power Consumption

−40°C to +105°C

• H.264 Encoding (8 and 10 bit intra−frame)

• Integrated Full−duplex Ethernet MAC

159 mW (Note 1)

1. Refer to Table 22 and Table 23 for operating currents.

• Precise Timing Protocol (PTP): IEEE

802.1AS and 1588−2008

Features

• IEEE 802.1Qav (Annex L Configurable

Video Bandwidth)

• AVB (IEEE1722) and RTP Video

Transport Protocol

• Up to 2.0 Mp (1920 x 1080) ON Semiconductor Sensor Support

• 30 fps at 1080 p, 45 fps at 1.2 Mp, 60 fps at 720p

(Optimized for Operation with HDR Sensors)

• Color and Gamma Correction

1

Publication Order Number:

October, 2019 − Rev. 5

AP0201AT/D

AP0201AT

Features (continued)

Applications

• ON Semiconductor Custom UDP−based Protocol

• IPv4, IPv6, TCP, DHCP, QoS and ICMP4 Support

• Proxy Service for Customer Specific Protocol

• Metadata over Ethernet

• Hybrid Mode Operation: Configuration over Serial

Interface and Video over Ethernet

• Surround, Rear and Front View Cameras

• Blind Spot/Side Mirror Replacement Cameras

• Automotive Viewing/Processing Fusion Cameras

• AEC−Q101 Qualified and PPAP Capable

ORDERING INFORMATION

Table 2. AVAILABLE PART NUMBERS

Part Number

AP0201AT2L00XEGA0−DR

AP0201AT2L00XEGA0−TR

AP0201AT2L00XEGAD3−GEVK

AP0201AT2L00XEGAH3−GEVB

Product Description

Ethernet Co−Processor, 100−ball VFBGA

Orderable Product Attribute Description

Drypack

†

Ethernet Co−Processor, 100−ball VFBGA

AP0201AT Demo Kit

Tape & Reel

AP0201AT Head Board

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

FUNCTIONAL OVERVIEW

Figure 1 shows the typical configuration of the

AP0201AT in a camera system. On the host side, commands

and image data are sent out over the Ethernet bus. The

AP0201AT interface to the sensor supports a parallel

interface or HiSPi interface.

NOTE: The Hybrid mode supports configuring the AP0201AT through the serial interface and streaming video over Ethernet.

Hybrid Mode can be enabled by loading an available patch. Please contact ON Semiconductor support.

Figure 1. AP0201AT Connectivity

www.onsemi.com

2

AP0201AT

Image

Sensor

AP0201

PHY

CAMERA1

Image

Sensor

PHY

CAMERA2

Ethernet

Switch

uP

ECU

Image

Sensor

PHY

CAMERA3

Image

Sensor

AP0201

PHY

CAMERA4

NOTE: The AP0201AT example above shows the PHY which is used between the Ethernet switch and the AP0201AT.

Figure 2. Example AP0201AT Connectivity

www.onsemi.com

3

AP0201AT

SYSTEM INTERFACES

The AP0201AT signals to the sensor and host interfaces

can be at different supply voltage levels to optimize power

consumption and maximize flexibility. Table 3 on page 5

provides the signal descriptions for the AP0201AT.

Figure 3 shows typical AP0201AT device connections.

All power supply rails must be decoupled from ground

using capacitors as close as possible to the package.

PHY

power

Sensor IO

power

1.8 V

(Regulator IP)

1.2 V (Regulator OP)

Power up Core and PLL

OTP

power

HOST IO

power

VDDIO_S

V

IO_H

DD

S

CLK

M_S

CLK

DATA

S

ADDR

RESET_BAR

FRAME_SYNC

EXTCLK_OUT

STANDBY

EXTCLK

RESET_BAR_OUT

XTAL

PHY_RESET_BAR

FV_IN

LV_IN

PIXCLK_IN

DIN[11:0]

MDC

MDIO

TX_CLK

TX_EN

TXD[7:0]

Ethernet MAC Signals

OR

TX_ERR

RX_CLK

CRS_DV

RX_ERR

RXD[7:0]

HISPICN

HISPICP

HISPI0N

HISPI0P

HISPI1N

HISPI1NP

SPI_CS_BAR

GTX_CLK

SPI_S

CLK

SPI_SDO

SPI_SDI

GPIO[6:0]

TRIGGER_OUT

EXT_REG

RESERVED[1:0]

TRST_BAR

GND

V

IO_S

V

_REG

DD

(Note 4)

LDO_OP

(Note 4)

DD

V

IO_OTPM

V

IO_H

DD

(Note 6)

DD

NOTES: 1. This typical configuration shows only one scenario out of multiple possible variations for this device.

2. ON Semiconductor recommends a 1.5 kW resistor value for the two−wire serial interface R

3. RESET_BAR has an internal pull−up resistor and can be left floating if not used.

.

PULL−UP

4. The decoupling capacitors for the regulator input and output should have a value of 1.0 mF. The capacitors should be ceramic

and need to have X5R or X7R dielectric.

5. TRST and RESERVED[0] connect to GND for normal operation, RESERVED[3:2] are floating and RESERVED[1] is connected

to VDDIO_H for normal operation.

6. ON Semiconductor recommends that 0.1 mF and 1 mF decoupling capacitors for each power supply are mounted as close as

possible to the pin. Actual values and numbers may vary depending on layout and design consideration.

Figure 3. Typical Ethernet Configuration

www.onsemi.com

4

AP0201AT

HiSPi and Parallel Connection

Crystal Usage

When using the HiSPi interface, connect the parallel

interface to GND.

When using the parallel interface, it is recommended for

the HiSPi interface to be connected to ground, and the power

supply (VDD_PHY) to be connected to +2.8 V. Floating

these pins is allowed as well.

As an alternative to using an external oscillator, a crystal

may be connected between EXTCLK and XTAL. Two small

loading capacitors and a feedback resistor should be added,

as shown in Figure 4.

For applications above 85°C, ON Semiconductor does not

recommend using the crystal option. A crystal oscillator

with temperature compensation is recommended for

applications that require this.

AP0201AT

C1

C2

EXTCLK

Rf = 1 MW

XTAL

NOTE: Rf represents the feedback resistor, an Rf value of 1 MW is sufficient for AP0201AT. C1 and C2 are decided according to the

crystal or resonator CL specification. In the steady state of oscillation, CL is defined as (C1xC2)/(C1+C2). In fact, the I/O

ports, the bond pad, package pin and PCB traces all contribute the parasitic capacitance to C1 and C2. Therefore, CL can

be rewritten to be (C1*xC2*)/(C1*+C2*), where C1* = (C1 +C , STRAY) and C2* = (C2+C

). The stray

IN

OUT, STRAY

capacitance for the IO ports, bond pad and package pin are known which means the formulas can be rewritten as

C1* = (C1+1.5 pF+C , PCB) and C2* = (C2+1.3 pF+C , PCB).

IN

OUT

Figure 4. Using a Crystal Instead of External Oscillator

PIN DESCRIPTIONS

Table 3. PIN DESCRIPTIONS

Name

Type

Input

Description

EXTCLK

Master input clock, nominally 27 MHz. This can either be a square−wave generated from

an oscillator (in which case the XTAL input must be left unconnected) or direct connection

to a crystal.

XTAL

Output

If EXTCLK is connected to one pin of a crystal, this signal is connected to the other pin,

otherwise this signal must be left unconnected.

RESET_BAR

Input/PU

Asynchronous active−low reset. When asserted, the device will return all interfaces to

their reset state. When released, the device will initiate the boot sequence. This signal

has an internal pull−up resistor.

FRAME_SYNC

Input

Pass through to TRIGGER_OUT. This signal should be connected to GND if not used.

This pin has two modes of use for frame sync. One the pass through to TRIGGER_OUT.

The other goes to the frame_sync_monitor block.

STANDBY

EXT_REG

ENLDO

Input

Standby mode control, active HIGH.

Select external regulator if tied high.

Input

Regulator enable (V _REG domain).

DD

SPI_SCLK

SPI_SDI

Output

Input

Clock output for interfacing to an external SPI flash or EEPROM memory.

Data in from SPI flash or EEPROM memory. When no SPI device is fitted, this signal is

used to determine whether the AP0201AT should auto−configure:

0: Do not auto−configure; Two−wire or ethernet interface will be used to configure the

device (host−config mode).

1: Auto−configure. This signal has an internal pull−up resistor.

SPI_SDO

Output

Data out to SPI flash or EEPROM memory.

www.onsemi.com

5

AP0201AT

Table 3. PIN DESCRIPTIONS (continued)

Name

Type

Output

I/O

Description

SPI_CS_BAR

EXTCLK_OUT

RESET_BAR_OUT

Chip select out to SPI flash or EEPROM memory.

Clock to external sensor.

Reset signal to external sensor.

Two−wire serial interface clock (Master).

Two−wire serial interface data (Master).

Sensor frame valid input.

M_S

CLK

M_S

DATA

FV_IN

Input

LV_IN

Input

Sensor line valid input.

PIXCLK_IN

Input

Sensor pixel clock input.

D

[11:0]

Input

Sensor pixel data input D [11:0].

IN

HiSPiCN

HiSPiCP

Input

Differential HiSPi clock (negative).

Differential HiSPi clock (positive).

Differential HiSPi data, lane 0 (negative).

Differential HiSPi data, lane 0 (positive).

Differential HiSPi data, lane 1 (negative).

Differential HiSPi data, lane 1 (positive).

Trigger signal for external sensor.

PHY_RESET_BAR Output.

Input

HiSPi0N

Input

HiSPi0P

Input

HiSPi1N

Input

HiSPi1P

Input

TRIGGER_OUT

PHY_RESET_BAR

TX_CLK

Output

Host frame valid output.

RX_CLK

Host line valid output.

GTX_CLK

Host pixel clock output. This signal is only used in GMII mode and may be left floating

for all other modes.

TXD[7:4]

Output

Ethernet port. TXD[7:4] is only used for Gigabit Ethernet and should be tied to

GND for 100 Mbit applications.

TXD[3:0]

TX_ERR

TX_EN

Output

Input

Ethernet port.

RXD[7:4]

Ethernet port. RXD[7:4] is only used for Gigabit Ethernet and should be tied to GND

for 100 Mbit applications.

RXD[3:0]

RX_ERR

CRS_DV

MDC

Input

Ethernet port.

Input

Ethernet port.

Output

I/O

Management Data clock for controlling the PHY.

Management Data Input/Output for controlling the PHY.

General purpose digital I/O.

Must be tied to GND in normal operation.

Sensor I/O power supply.

Host I/O power supply.

MDIO

GPIO_[6:1]

TRST

I/O

Input

Reserved[0]

Input

V

IO_S

IO_H

_PLL

Supply

DD

PLL supply.

DD

V

DD

Core supply.

V

IO_OTPM

OTPM power supply.

DD

V

DD

_PHY

PHY IO voltage for HiSPi.

Ground.

GND

www.onsemi.com

6

AP0201AT

Table 3. PIN DESCRIPTIONS (continued)

Name

_REG

Type

Supply

Output

Input

Description

V

Input to on−chip 1.8 V to 1.2 V regulator.

Output from on chip 1.8 V to 1.2 V regulator.

On−chip regulator sense signal.

DD

LDO_OP

FB_SENSE

Table 4. PACKAGE PINOUT

1

2

3

4

5

6

7

8

9

10

A

B

C

Reserved[0]

SCLK

V

IO_H

M_S

D

0

V

D

IN

D

IN

D

IN

5

4

3

D

10

LV_IN

V IO_S

DD

FV_IN

DD

DATA

IN

DD

IN

GPIO_6

EXTCLK_OUT

M_S

D

IN

1

D

9

8

D 11

IN

HiSPi1N

HiSPiCN

HiSPi1P

HiSPiCP

CLK

IN

SPI_SCLK

Reserved[1]

(Note 2)

S

DATA

GPIO_5

TRIGGER_

OUT/

D

PIXCLK_IN

GPIO_0

D

SPI_SDO

SPI_SDI

SPI_CS_BAR

SADDR

GND

RESET_

BAR_OUT

D

2

D

7

6

V _PHY

DD

HiSPi0N

HiSPi0P

IN

E

F

V

DD

GPIO_1

GPIO_2

STANDBY

GPIO_3

GND

XTAL

V

DD

IO_H

DD

IN

V

DD

IO_

RESET_

BAR

GND

EXTCLK

V

OTMP

G

H

TRST

GPIO_4

TX_CLK

FRAME_SYNC

MDIO

RX_CLK

RX_ERR

RXD6

RXD4

RXD2

TXD5

TXD6

EXT_REG

TXD2

ENLDO

V

_PLL

DD

PHY_RESET_

BAR

TX_ERR

FB_SENSE

V

DD

_REG

J

GTX_CLK

Reserved[3]

CRS_DV

MDC

RXD7

RXD5

RXD3

RXD0

RXD1

TXD7

TXD3

TXD4

TXD0

TXD1

LDO_OP

GND

K

Reserved[2]

V

DD

IO_H

V

DD

TX_EN

1. Pin K1 and J2 should be left floating.

2. Pin C2 needs to be tied to V IO_H in all applications.

DD

3. A1 to be tied to ground.

ON−CHIP REGULATOR

The AP0201AT has an on−chip regulator, the output from

the regulator is 1.2V and should only be used to power up the

AP0201AT. It is possible to bypass the regulator and provide

power to the relevant pins that need 1.2 V. The following

table summarizes the key signals when using/bypassing the

regulator.

Table 5. KEY SIGNALS WHEN USING THE REGULATOR

Signal Name

_REG

Internal Regulator

1.8 V

External Regulator

V

Connect to V IO_H

DD

ENLDO

FB_SENSE

LDO_OP

Connect to 1.8 V (V _REG)

GND

Float

DD

1.2 V (input)

1.2 V (output)

GND

EXT_REG

Connect to V IO_H

DD

www.onsemi.com

7

AP0201AT

POWER−UP SEQUENCE

Powering up the AP0201AT requires voltages to be

applied in a particular order, as seen in Figure 5. The timing

requirements are shown below. The AP0201AT includes a

power−on reset feature that initiates a reset upon power up.

dv/dt

t1

V

DD

IO_H

t7

V

IO_S, V IO_OTPM,

DD

dv/dt

V

_PHY(when using HiSPi)

DD

t6

t5

t2

V

DD

_REG

t3

EXTCLK

S

CLK

t4

S

DATA

Figure 5. Power−Up and Power−Down Sequence

Table 6. POWER−UP AND POWER−DOWN SIGNAL TIMING

Symbol

Parameter

Min

Typ

Max

Unit

t1

Delay from V IO_H to V IO_S, V IO_OTPM, V _PHY

0

−

50

ms

DD

(when using HiSPi)

t2

t3

t4

t5

t6

t7

Delay from V IO_H to V _REG

0

t2+1

100

t6

−

50

−

ms

DD

EXTCLK activation

ms

First serial command (Note 4)

EXTCLK cutoff

−

EXTCLK cycles

−

ms

Delay from V _REG to V IO_H

0

50

DD

Delay from V IO_S, V IO_OTPM, V _PHY (when using

0

DD

HiSPi) to V IO_H

DD

dv/dt

Power supply ramp time (slew rate)

−

0.1

V/ms

4. When using XTAL the settling time should be taken into account.

RESET AND STANDBY MODES

• A soft reset is issued by writing commands through

the Ethernet interface.

• An internal power−on reset.

Reset

The AP0201AT has three types of reset available:

• A hard reset is issued by toggling the RESET_BAR

Table 7 shows the output states when the part is in various

states.

signal.

Table 7. OUTPUT STATES

Hardware States

Firmware States

Default

State

Hard

Standby

Soft

Standby

Reset State

Streaming

Idle

Name

Notes

EXTCLK

(clock running

or stopped)

(clock running)

(clock running

or stopped)

(clock running)

Input

XTAL

n/a

Output

Input

(asserted)

(negated)

RESET_BAR

www.onsemi.com

8

AP0201AT

Table 7. OUTPUT STATES (continued)

Hardware States

Firmware States

Default

Hard

Soft

State

Standby

Reset State

Streaming

Idle

Name

Notes

FRAME_

SYNC

n/a

Input. Must always be driven

to a valid logic level.

STANDBY

EXT_REG

ENLDO

n/a

(negated)

n/a

(negated)

n/a

(negated)

n/a

(negated)

n/a

(negated)

n/a

Input. Must always be driven

to a valid logic level.

Input. Must always be driven

to a valid logic level.

n/a

Input. Must be tied to

V

DD

_REG or GND.

SPI_SCLK

SPI_SDI

High−

impedance

driven, logic 0

Output

Internal pull−

Input. Internal pull−up

up enabled

permanently enabled.

SPI_SDO

SPI_CS_BAR

High−

impedance

driven, logic 0

driven, logic 1

driven, logic 0

driven, logic 1

driven, logic 0

driven, logic 1

driven, logic 0

Output

High−

impedance

EXT_CLK_

OUT

EXT_CLK_-

OUT

driven, logic 0

running in

streaming

state, stopped

or running in

idle state

(depending on

other FW sub−

state).

RESET_BAR

_OUT low in

streaming, low

or high in idle

state (depend-

ing on other

FW

sub−state).

RE-

SET_BAR_O-

UT

driven, logic 0

driven, logic 1

Output. Firmware will release

sensor reset.

M_S

High−

impedance

High−

impedance

High−

impedance

High−

impedance

Input/Output. A valid logic

level should be established

by pull−up.

CLK

M_S

High−

impedance

High−

impedance

High−

impedance

High−

impedance

Input/Output. A valid logic

level should be established

by pull−up.

DATA

FV_IN LV_IN,

PIXCLK_IN,

DIN [11:0]

n/a

Dependent on

interface used

n/a

Input. Must always be driven

to a valid logical level.

HiSPi_CN

HiSPi_CP

HiSPi0_N

HiSPi0_P

HiSPi1_N

HiSPi1_P

Disabled

Dependent on

interface used

Dependent on

interface used

Dependent on

interface used

Dependent on

interface used

Input. Will be disabled and

can be left floating.

TX_CLK,

RX_CLK,

GTX_CLK

High−

impedance

Varied

Driven if used

Output. Default state

dependent on

configuration.

www.onsemi.com

9

AP0201AT

Table 7. OUTPUT STATES (continued)

Hardware States

Firmware States

Default

Hard

Soft

State

Standby

Reset State

Streaming

Idle

Name

Notes

TXD[7:0],

TX_ERR,

TX_EN

Driven to ‘0‘

Driven if used

Transmit data bits 7 to 0 for

MII/RMII protocols (MAC to

PHY ). Transmit error.

Transmit enable.

RXD[7:0],

RX_ERR

High−

impedance

Receive data bits 7 to 0 for

MII/RMII protocols (PHY to

MAC). Receive error.

MDC, MDIO

MDC:

Driven to ‘0‘

MDIO:

MDC: Management data

clock line MDIO:

Management data I/O line

High

Impedance

GPIO[6:1]

High−

impedance

Input, then

high−

impedance

Driven if used

Input/Output.

TRIGGER_

OUT

High−

impedance

High−

impedance

Hard Reset

The AP0201AT enters the reset state when the external

RESET_BAR signal is asserted LOW, as shown in Figure 6.

Refer to Table 7 for details.

t

1

t

4

t

2

t

3

EXTCLK

RESET_BAR

Data Active

All Outputs

Mode

Enter streaming mode

Reset

Internal Initialization Time

Figure 6. Hard Reset Operation

Table 8. HARD RESET

Symbol

Parameter

Min

50

Typ

−

Max

−

Unit

t

1

t

2

t

3

t

4

RESET_BAR pulse width

EXTCLK cycles

Active EXTCLK required after RESET_BAR asserted

Active EXTCLK required after RESET_BAR de−asserted

Internal initialization time after RESET is HIGH

10

−

10

−

100

−

www.onsemi.com

10

AP0201AT

Soft Reset

reduction can be achieved by turning off the input clock, but

this must be restored before de−asserting the STANDBY pin

to LOW state to restart the device.

A soft reset sequence to the AP0201AT can be activated

by writing to a register through the Ethernet interface.

Entering Standby Mode

1. Assert STANDBY signal HIGH.

Hard Standby Mode

The AP0201AT can enter hard standby mode by using the

external STANDBY signal, as shown in Figure 7. In hard

standby mode, the total power consumption is reduced. In

this mode, the AP0201AT is switched off. A further power

Existing Standby Mode

1. De−assert STANDBY signal LOW.

t

1

t

2

t

3

EXTCLK

STANDBY

State

STANDBY

Asserted

STANDBY

Mode

EXTCLK Disabled

EXTCLK Enabled

Figure 7. Hard Standby Operation

Table 9. HARD STANDBY SIGNAL TIMING

Symbol

Parameter

Min

−

Typ

−

Max

2

Unit

t

1

t

2

t

3

Standby entry complete

Frames

Active EXTCLK required after going into STANDBY mode

10

−

EXTCLKs

Active EXTCLK required before STANDBY de−asserted

−

DEVICE CONFIGURATION

After power is applied and the device is out of reset (either

the power on reset, hard or soft reset), it will enter a boot

sequence to configure its operating mode. There are

essentially three configuration modes: Flash/EEPROM

Config, Auto Config, and Host Config.

♦ If SPI_SDI is low, then it enters the Host−Config

mode.

♦ If SPI_SDI is high, then it enters the Auto−Config

mode.

In the Flash−Config mode, the firmware interrogates the

device to determine if it contains valid configuration

records:

• If no records are detected, then the firmware enters the

Host−Config mode.

The AP0201AT firmware supports

a

System

Configuration phase at start−up. This consists of three

sub−phases of execution:

Flash detection, then one of:

a. Flash Config

b. Auto Config

c. Host Config

• After power is applied and the device is out of reset

(either the power on reset, hard or soft reset), it will

enter a boot sequence to configure its operating mode.

There are essentially three configuration modes:

Flash/EEPROM Config, Auto Config, and Host Config.

The System Configuration phase is entered immediately

following power−up or reset. Then the firmware performs

Flash Detection.

Flash Detection attempts to detect the presence of an SPI

Flash or EEPROM device:

• If a device is detected, the firmware switches to the

Flash−Config mode.

• If no device is detected, the firmware then samples the

SPI_SDI pin state to determine the next mode:

In the Host−Config mode, the firmware performs no

configuration, and remains idle waiting for configuration

and commands from the host. The System Configuration

phase is effectively complete and the AP0201AT will take

no actions until the host issues commands.

www.onsemi.com

11

AP0201AT

USAGE MODES

How a camera based on the AP0201AT will be configured

depends on what features are used. In the simplest case, an

AP0201AT operating in Auto−Config mode with no

customized settings might be sufficient.

A back−up camera with dynamic input from the steering

system will require a host system with

Ethernet capability. Flash sizes vary depending on the

register and firmware data being transferred—the

AP0201AT supports devices up to 2 GB.

In the simplest case no EEPROM or Flash memory is

required, as shown in Figure 8.

AP0201AT + image sensor

Auto−Config Mode

PHY

Host Ethernet

Figure 8. Auto−Config Mode

AP0201AT + image sensor

Serial EEPROM/Flash

PHY

Host Ethernet

SPI

Figure 9. Flash Mode

AP0201AT + image sensor

Serial EEPROM/Flash

PHY

Host Ethernet

SPI

NOTE: In this configuration all settings are communicated to the AP0201AT and sensor through the host.

Figure 10. Host Mode with Flash

AP0201AT + image sensor

PHY

Host Ethernet

Figure 11. Host Mode

www.onsemi.com

12

AP0201AT

Adaptive Local Tone Mapping (ALTM)

IMAGE FLOW PROCESSOR

Real world scenes often have very high dynamic range

(HDR) that far exceeds the electrical dynamic range of the

imager. Dynamic range is defined as the luminance ratio

between the brightest and the darkest object in a scene. In

recent years many technologies have been developed to

capture the full dynamic range of real world scenes. For

example, the multiple exposure method is widely adopted

for capturing high dynamic range images, which combines

a series of low dynamic range images of the same scene

taken under different exposure times into a single HDR

image.

Even though the new digital imaging technology enables

the capture of the full dynamic range, low dynamic range

display devices are the limiting factor. Today’s typical LCD

monitor has contrast ratio around 1,000:1; this contrast ratio

is not enough for an HDR image (the contrast ratio for an

HDR image is around 250,000:1). Therefore, in order to

reproduce HDR images on a low dynamic range display

device, the captured high dynamic range must be

compressed to the available range of the display device. This

is commonly called tone mapping.

Tone mapping methods can be classified into global tone

mapping and local tone mapping. Global tone mapping

methods apply the same mapping function to all pixels.

While global tone mapping methods provide

computationally simple and easy to use solutions, they often

cause loss of contrast and detail. A local tone mapping is thus

necessary in addition to global tone mapping for the

reproduction of visually more appealing images that also

reveal scene details that are important for automotive safety

applications. Local tone mapping methods use a spatially

variable mapping function determined by the neighborhood

of a pixel, which allows it to increase the local contrast and

the visibility of some details of the image. Local methods

usually yield more pleasing results because they exploit the

fact that human vision is more sensitive to local contrast.

ON Semiconductor’s ALTM solution significantly

improves the performance over global tone mapping.

ALTM is directly applied to the Bayer domain to compress

the dynamic range from 20−bit to 12−bit. This allows the

regular color pipeline to be used for HDR image rendering.

Image and color processing in the AP0201AT is

implemented as an image flow processor (IFP) coded in

hardware logic. During normal operation, the embedded

microcontroller will automatically adjust the operating

parameters. For normal operation of the AP0201AT, streams

of raw image data from the attached image sensor are fed

into the color pipeline. The AP201AT also has the option to

select a number of test patterns to be input instead of sensor

data.

Defect Correction

Image stream processing commences with the defect

correction function immediately after data decompanding.

To obtain defect free images, the pixels marked defective

during sensor readout and the pixels determined defective

by the defect correction algorithms are replaced with values

derived from the non−defective neighboring pixels.

AdaCD (Adaptive Color Difference)

The next step in the image stream processing is noise

reduction. The AP0201AT uses a noise reduction filter

called AdaCD which focuses on removing color noise while

preserving edge details. Automotive applications require

good performance in extremely low light, even at high

temperature conditions. In these stringent conditions the

image sensor is prone to higher noise levels, and so efficient

noise reduction techniques are required to circumvent this

sensor limitation and deliver a high quality image to the user.

Black Level Substraction and Digital Gain

After noise reduction, the pixel data goes through black

level subtraction and multiplication by a programmable

digital gain. Independent color channel digital gain can be

adjusted with registers. Black level subtraction (to

compensate for sensor data pedestal) is a single value

applied to all color channels. If the black level subtraction

produces a negative result for a particular pixel, the value of

this pixel is set to 0.

Positional Gain Adjustments (PGA)

Lenses tend to produce images whose brightness is

significantly attenuated near the edges. There are also other

factors causing fixed pattern signal gradients in images

captured by image sensors. The cumulative result of all these

factors is known as image shading. The AP0201AT has an

embedded shading correction module that can be

programmed to counter the shading effects on each

individual R, Gb, Gr, and B color signal.

Color Interpolation

In the raw data stream fed by the external sensor to the IFP,

each pixel is represented by a 20− or 12−bit integer number,

which can be considered proportional to the pixel’s response

to a one−color light stimulus, red, green, or blue, depending

on the pixel’s position under the color filter array. Initial data

processing steps, up to and including ALTM, preserve the

one−color−per−pixel nature of the data stream, but after

ALTM it must be converted to a three−colors−per−pixel

stream appropriate for standard color processing. The

conversion is done by an edge−sensitive color interpolation

module. The module pads the incomplete color information

available for each pixel with information extracted from an

The Correction Function

The correction functions can then be applied to each pixel

value to equalize the response across the image as follows:

P

(row, col) + P

(row, col) f(row, col)

(eq. 1)

corrected

sensor

where P are the pixel values and f is the color dependent

correction functions for each color channel.

www.onsemi.com

13

AP0201AT

appropriate set of neighboring pixels. The algorithm used to

2560, 3072, 3584, and 4096. The 10−bit ordinates are

programmable through variables.

select this set and extract the information seeks the best

compromise between preserving edges and filtering out

high frequency noise in flat field areas. The edge threshold

can be set through register settings.

The AP0201AT has the ability to calculate the 33−point

knee points based on the tuning of cam_ll_gamma and

cam_ll_contrast_gradient_bright. The other method is for

the host to program the 33 knee point curve directly.

Also included in this block is a Fade−to Black curve which

sets all knee points to zero and causes the image to go black

in extreme low light conditions.

Color Correction and Aperture Correction

To achieve good color fidelity of the IFP output,

interpolated RGB values of all pixels are subjected to color

correction. The IFP multiplies each vector of three pixel

colors by a 3 x 3 color correction matrix. The three

components of the resulting color vector are all sums of three

10−bit numbers. The color correction matrix can be either

programmed by the host or automatically selected by the

auto white balance (AWB) algorithm implemented in the

IFP. Color correction should ideally produce output colors

that are corrected for the spectral sensitivity and color

crosstalk characteristics of the image sensor. The optimal

values of the color correction matrix elements depend on

those sensor characteristics and on the spectrum of light

incident on the sensor. The color correction variables can be

adjusted through register settings.

The AP0201AT offers a three−CCM solution that will

give the user improved color fidelity when under CWF type

lighting.

To increase image sharpness, a programmable 2D

aperture correction (sharpening filter) is applied to

color−corrected image data. The gain and threshold for 2D

correction can be defined through register settings

Color Kill

To remove high−or low−light color artifacts, a color kill

circuit is included. It affects only pixels whose luminance

exceeds a certain preprogrammed threshold. The U and V

values of those pixels are attenuated proportionally to the

difference between their luminance and the threshold.

YUV Color Filter

As an optional processing step, noise suppression by

one−dimensional low−pass filtering of Y and/or UV signals

is possible. A 3− or 5−tap filter can be selected for each

signal.

CAMERA CONTROL AND AUTO FUNCTIONS

Auto Exposure

The auto exposure algorithm optimizes scene exposure to

minimize clipping and saturation in critical areas of the

image. This is achieved by controlling exposure time and

analog gains of the external sensor as well as digital gains

applied to the image.

Auto exposure is implemented by a firmware algorithm

that is running on the embedded microcontroller that

analyzes image statistics collected by the exposure

measurement engine, makes a decision, and programs the

sensor and color pipeline to achieve the desired exposure.

The measurement engine subdivides the image into 25

windows organized as a 5 x 5 grid.

Gamma Correction

The gamma correction curve is implemented as a

piecewise linear function with 33 knee points, taking 12−bit

arguments and mapping them to 10−bit output. The

abscissas of the knee points are fixed at 0, 8, 16, 24, 32, 40,

48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256, 320, 384,

448, 512, 640, 768, 896, 1024, 1280, 1536, 1792, 2048,

W 0,0

W 0,1

W 0,2

W 0,3

W 0,4

W 1,0

W 2,0

W 3,0

W 4,0

W 1,1

W 2,1

W 3,1

W 4,1

W 1,2

W 2,2

W 3,2

W 4,2

W 1,3

W 2,3

W 3,3

W 4,3

W 1,4

W 2,4

W 3,4

W 4,4

Figure 12. 5 x 5 Grid

The region of interest can be controlled through the

combination of an inclusion window and an exclusion

window.

www.onsemi.com

14

AP0201AT

AE Track Driver

Exposure and White Balance Modes

Other algorithm features include the rejection of fast

fluctuations in illumination (time averaging), control of

speed of response, and control of the sensitivity to small

changes. While the default settings are adequate in most

situations, the user can program target brightness,

measurement window, and other parameters described

above.

The AP0201AT supports auto and manual exposure and

white balance modes. In addition, it will operate within

synchronized multi−camera systems. In this use case, one

camera within the system will be the ’master’, and the others

’slaves’. The master is used to calculate the appropriate

exposure and white balance. This is then applied to all slaves

concurrently under host control.

The driver changes AE parameters (integration time,

gains, and so on) to drive scene brightness to the

programmable target.

To avoid unwanted reaction of AE on small fluctuations

of scene brightness or momentary scene changes, the AE

track driver uses a temporal filter for luma and a threshold

around the AE luma target. The driver changes AE

parameters only if the filtered luma is larger than the AE

target step and pushes the luma beyond the threshold.

Auto Mode

In Auto Exposure mode the AE algorithm is responsible

for calculating the appropriate exposure to keep the desired

scene brightness, and for applying the exposure to the

underlying hardware. In Auto White Balance mode the

AWB algorithm is responsible for calculating the color

temperature of the scene and applying the appropriate red

and blue gains to compensate.

Triggered Auto Mode

Auto White Balance

The Triggered Auto Exposure and Triggered Auto White

Balance modes are intended for the multicamera use cases,

where a host is controlling the exposure and white balance

of a number of cameras. The idea is that one camera is in

triggered−auto mode (the master), and the others in

hostcontrolled mode (slaves). The master camera must

calculate the exposure and gains, the host then copies this to

the slaves, and all changes are then applied at the same time.

The AP0201AT has a built−in AWB algorithm designed

to compensate for the effects of changing spectra of the

scene illumination on the quality of the color rendition. The

algorithm consists of two major parts: a measurement

engine performing statistical analysis of the image and a

driver performing the selection of the optimal color

correction matrix and IFP digital gain. While default

settings of these algorithms are adequate in most situations,

the user can reprogram base color correction matrices, place

limits on color channel gains, and control the speed of both

matrix and gain adjustments. The AP0201AT AWB displays

the current AWB position in color temperature, the range of

which is defined by programmable settings.

Manual Mode

Manual mode is intended to allow simple manual

exposure and white balance control by the host. The host

needs to set the CAM_AET_EXPOSURE_TIME_MS,

CAM_AET_EXPOSURE_GAIN

and CAM_AWB_COLOR_TEMPERATURE controls, the

camera will calculate the appropriate integration times and

gains.

The region of interest can be controlled through the

combination of an inclusion window and an exclusion

window.

Host Controlled

Exposure and White Balance Control

The Host Controlled mode is intended to give the host full

control over exposure and gains to allow host to control

desired output.

The Sensor Manager firmware component is responsible

for controlling the application of ’exposure’ and ’white

balance’ within the system. This effectively means that all

control of integration times and gains (whether for exposure

or white balance) is delegated to the Sensor Manager. The

Auto Exposure (AE) and Auto White Balance (AWB)

algorithms use services provided by the Sensor Manager to

apply exposure and/or white balance changes.

FLICKER AVOIDANCE

Flicker occurs when the integration time is not an integer

multiple of the period of the light intensity. The AP0201AT

can be programmed to avoid flicker for 50 or 60 Hertz. For

integration times below the light intensity period (10ms for

50Hz environment, 8.33 ms for a 60 Hz environment),

flicker cannot be avoided. The AP0201AT supports an

indoor AE mode, that will ensure flicker−free operation.

Dual Band IRCF

Manager firmware component is responsible for

controlling the application of ’exposure’ and ’white

balance’ within the system. This effectively means that all

control of integration times and gains (whether for exposure

or white balance) is delegated to the Sensor Manager. The

Auto Exposure (AE) and Auto White Balance (AWB)

algorithms use services provided by the Sensor Manager to

apply exposure and/or white balance changes.

FLICKER DETECTION

The AP0201AT supports flicker detection, the algorithm

is designed only to detect a 50Hz or 60 Hz flicker source.

Output Formatting.

The pixel output data in AP0201AT will be transmitted as

an 8−bit word over the Ethernet interface.

www.onsemi.com

15

AP0201AT

Output Video Formats

♦ Eliminates spares and insignificant transform

coefficients

♦ Improves the compression efficiency

♦ Near−zero impact to the measured video quality

♦ Zero impact to the perceived, subjective, video

quality

The AP0201AT conforms with the IEEE standard for both

MJPEG and H.264 video outputs. For reference, the

standard is “IEEE Standard for Layer 2 Transport Protocol

for Time−Sensitive Applications in Bridged Local Area

Networks” and can be obtained from IEEE.

• Run−time tunable operation enables decoder

H.264 Format

The AP0201AT is compliant with the ITU−T REC. H.264

standard published

Standardization Sector

Telecommunication Union, which is equivalent to ISO/IEC

14496−10.

compatibility trade−offs

♦ Full control of allowed Intra prediction modes

♦ Single or multiple slices per frame encoding

♦ Option and tunable deblocking filter operation

♦ CAVLC coding

by

the

of

Telecommunication

the International

The AP0201AT supports the standard H.264 for video

compression which is equivalent to MPEG−4 Part 10, also

known as MPEG−4 Advanced Video Coding (AVC). The

AP0201AT utilizes an advanced High profiles compliant

encoder, constrained to the All−Intra encoding schemes. It

supports real time encoding of 4:2:0 video streams, up to

Level 5.2, in 8 and 10 bit sample depths. The core only needs

to be programmed once per video sequence. Once

programmed, the AP0201AT can encode an arbitrary

number of video frames, without the need of any further

intervention from the host system.

MJPEG FORMAT

JPEG Encoder

The JPEG compression engine in the AP0201AT is a

highly integrated, high−performance solution that provides

for low power consumption and programmability of JPEG

compression parameters for image quality control.

The JPEG encoding block is designed for continuous

image flow and is ideal for low power applications. After

initial configuration for a target application, it can be

controlled easily for instantaneous stop or restart. A flexible

configuration and control interface allows for full

programmability of various JPEG−specific parameters and

tables.

H.264 Features

The AP0201AT H.264 encoding includes the following

features:

• High 10 intra profile encoding

JPEG Encoding Highlights

• Sequential DCT (baseline) ISO/IEC 10918−1

JPEG−compliant

• YCbCr 4:2:0 format compression

• JPEG capability at full resolution with JFIF− or

RFC2435−compliant header

• Programmable automatic control of bit rate

• 8− and 10−bit sample depth encoding

• Level up to 5.2

• ITU−T H.264 Annex B compliant NAL byte stream

output

• CQP − VBR encoding mode

♦ Rate−Distortion optimized output

♦ Up to 240MBits/s output (CAVLC)

Stream Breakdown

• CBR encoding mode

An MJPEG video stream consists of the following

sequence of data sections. Each JPEG frame must have the

following characteristics:

• Color Encoding is YcbCr

• 8 bits per color component, (24 bits/pixel before

subsampling)

♦ HRD CPB compliant CBR NAL output

♦ Sub−frame operation with tunable number of

macroblocks basis

♦ Further micro adjustment of quantization per

macroblock maximizes the perceived video quality

♦ Both Rate−Distortion metrics and perceived video

quality optimized

♦ On−the−fly rate changes are supported

♦ Up to 240 Mbits/s output (CAVLC)

• 420 Subsampling

• Baseline sequential DCT (SOF0)

JPEG Header

• Advanced Intra prediction

The MJPEG stream can be output with 4 different header

settings.

♦ All four Intra 16x16 prediction modes

♦ All four Intra Chroma prediction modes

♦ All nine Intra 4x4 prediction modes

Three of them are similar to each other. The first is the

standard JPEG header as defined in the original JPEG

specification. The second is a JFIF header which is the

standard header plus a JFIF segment. The third is a standard

header minus the Huffman table. Since, for this design, the

Huffman table is constant, some bandwidth can be saved by

not including it.

• Error resilience

♦ Multiple slices per frame encoding

♦ Deblocking filter in the decoder can be optionally

constrained to operate within slice boundaries

• Optional advanced thresholding of quantized transform

coefficients

www.onsemi.com

16

AP0201AT

The 4th header option is optimized for Ethernet and is

referred to as RFC2435.

• APP0, Application Segment 0. N bytes (only included

in JFIF headers):

Example JFIF marker: ff e0 00 10

4a 46 49 46 00 01 02 00 00 01 00 01 00 00

• DHT, Define Huffman Tables, 420 bytes (Not included

in standard header without Huffman table)

Example: ff c4 01 a2

JFIF, Standard and Standard minus Huffman Headers

For these three header types, the header segments that will

be included are listed below including examples. Note that

data values in the examples are in hex. Comments are in

decimal.

• SOI, Start of Image. 2 bytes.

ff d8

#DC Table 0

00

01

05

02

01

03

01

04

01

05

01

06

01

07

01

08

00

09

00

0a

00

0b

00

#12 codes

#AC Table 0

10

00

01

22

24

29

4a

6a

8a

a8

c6

e3

f9

02

71

33

2a

53

73

92

a9

c7

e4

fa

01

03

14

62

34

54

74

93

aa

c8

e5

03

00

32

72

35

55

75

94

b2

c9

e6

03

04

81

82

36

56

76

95

b3

ca

e7

02

11

91

09

37

57

77

96

b4

d2

e8

04

05

a1

0a

38

58

78

97

b5

d3

e9

03

12

08

16

39

59

79

98

b6

d4

ea

05

21

23

17

3a

5a

7a

99

b7

d5

f1

05

31

42

18

43

63

83

9a

b8

d6

f2

04

41

b1

19

44

64

84

a2

b9

d7

f3

04

06

c1

1a

45

65

85

a3

ba

d8

f4

00

13

15

25

46

66

86

a4

c2

d9

f5

00

51

52

26

47

67

87

a5

c3

da

f6

01

61

d1

27

48

68

88

a6

c4

e1

f7

7d

07

f0

#162 codes

28

49

69

89

a7

c5

e2

f8

#DC Table 1

01

00

03

01

02

01

03

01

04

01

05

01

06

01

07

01

08

01

09

01

0a

00

0b

00

#12 codes

#AC Table 1

11

00

13

15

27

49

69

88

a6

02

01

22

62

28

4a

6a

89

a7

01

02

04

03

05

42

24

37

57

77

95

b3

04

21

91

34

38

58

78

96

b4

07

31

a1

e1

39

59

79

97

b5

05

06

b1

25

3a

5a

7a

98

b6

04

12

c1

f1

04

00

51

23

18

45

65

84

a2

b9

01

07

33

19

46

66

85

a3

ba

02

61

52

1a

47

67

86

a4

c2

77

71

f0

#162 codes

02

32

72

29

53

73

8a

a8

03

81

d1

2a

54

74

92

a9

11

08

0a

35

55

75

93

aa

04

14

16

36

56

76

94

b2

41

09

17

44

64

83

9a

b8

26

59

68

87

a5

c3

43

63

82

99

b7

www.onsemi.com

17

AP0201AT

#AC Table 1

c4

e2

f9

c5

e3

fa

c6

e4

c7

e5

c8

e6

c9

e7

ca

e8

d2

e9

d3

ea

d4

f2

d5

f3

d6

f4

d7

d5

d8

f6

d9

f7

da

f8

• DQT, Define Quantization Tables. 134 bytes.

Example: ff db 00 84

#8−bit, Table 0

00

10

1a

38

5f

0b

18

37

62

0c

16

40

67

0e

16

48

68

0c

18

5c

67

0a

31

4e

3e

10

0e

25

44

71

0d

1d

57

79

0e

12

11

33

38

78

10

3d

50

5c

13

3c

6d

65

18

39

51

67

28

33

57

63

23

40

4d

28

45

70

3a

37

64

#8−bit, Table 1

01

11

63

12

63

12

63

18

63

15

63

18

63

2f

1a

63

1a

63

2f

63

42

63

38

63

42

63

The quantization table can be adjusted for each frame for

more or less compression.

• DRI, Define Restart Interval. 6 bytes.

Example: ff db 00 04 00 78

The segment is optional. The host will determine whether

to include Restart markers and at what interval.

• SOF0, Start of Frame 0. 19 bytes.

Example: ff c0 00 11

08

04

07

#Sample precision

38

80

#Number of rows = 1080

#Number of columns = 1920

03

01

02

03

#Number of components

21

11

00

01

#Component 1: HSF = 2, VSF = 1, Q Table = 0

#Component 2: HSF = 1, VSF = 1, Q Table = 1

#Component 3: HSF = 1, VSF = 1, Q Table = 1

• SOS, Start of Scan. 14 bytes.

Example: ff da 00 0c

03

01

02

03

00

3f

#Number of components

00

11

#Component 1: DC table 0, AC table 0

#Component 2: DC table 1, AC table 1

#Component 3: DC table 1, AC table 1

#Start of spectral selection

#End of spectral selection

00

#Successive approximation high/low

www.onsemi.com

18

AP0201AT

Compressed Data With or Without Restart Markers

Huffman Table

This is compressed binary data of the frame which can be

decoded to display the captured image. The JPEG

compression engine can be configured to insert restart

marker at programmable intervals.

When standard JPEG headers without Huffman tables is

selected, the Huffman table is not included in the data

stream. However, the decoder will need to know what the

table is to perform the decode.

The required Huffman table is:

EOI

This is the End of Image code. It is only 2 bytes long.

ff d9

/* Default DHT Segment */

MJPGHDTSEG_STORAGE BYTE MUPGDHTSeg[0x1A0] = {

/*JPEG DHT Segment for YCrCb omitted from MJPG data*/

0xFF

0x00

0xC4

0x00

0x03

0x01

0x00

0x01

0xA2

0x05

0x01

0x02

0x01

0x03

0x01

0x04

0x01

0x05

0x01

0x06

0x01

0x07

0x01

0x00

0x08

0x01

0x00

0x09

0x00

0x0A

0x00

0x0B

0x00

0x01

0x00

0x02

0x01

0x07

0xD1

0x26

0x46

0x00

0x01

0x02

0x22

0xF0

0x27

0x47

0x01

0x03

0x71

0x24

0x28

0x48

0x02

0x03

0x00

0x14

0x33

0x29

0x49

0x03

0x02

0x04

0x32

0x62

0x2A

0x4A

0x04

0x11

0x81

0x72

0x34

0x53

0x05

0x03

0x05

0x91

0x82

0x35

0x54

0x06

0x05

0x12

0xA1

0x09

0x36

0x55

0x07

0x05

0x21

0x08

0x0A

0x37

0x56

0x08

0x04

0x31

0x23

0x16

0x38

0x57

0x09

0x04

0x41

0x42

0x17

0x39

0x58

0x0A

0x00

0x06

0xB1

0x18

0x3A

0x59

0x0B

0x00

0x13

0xC1

0x19

0x43

0x5A

0x10

0x01

0x51

0x15

0x1A

0x44

0x63

0x00

0x7D

0x61

0x52

0x25

0x45

0x64

0x65

0x84

0x9A

0xB7

0xD4

0xE9

0x01

0x66

0x85

0xA2

0xB8

0xD5

0xEA

0x02

0x67

0x86

0xA3

0xB9

0xD6

0xF1

0x04

0x68

0x87

0xA4

0xBA

0xD7

0xF2

0x04

0x69

0x88

0xA5

0xC2

0xD8

0xF3

0x03

0x6A

0x89

0xA6

0xC3

0xD9

0xF4

0x04

0x73

0x8A

0xA7

0xC4

0xDA

0xF5

0x07

0x74

0x92

0xA8

0xC5

0xE1

0xF6

0x05

0x75

0x93

0xA9

0xC6

0xE2

0xF7

0x04

0x76

0x94

0xAA

0xC7

0xE3

0xF8

0x04

0x77

0x95

0xB2

0xC8

0xE4

0xF9

0x00

0x78

0x96

0xB3

0xC9

0xE5

0xFA

0x01

0x79

0x97

0xB4

0xCA

0xE6

0x11

0x02

0x7A

0x98

0xB5

0xD2

0xE7

0x00

0x77

0x83

0x99

0xB6

0xD3

0xE8

0x02

0x00

0x01

0x13

0xF0

0x1A

0x46

0x65

0x83

0x02

0x22

0x15

0x25

0x47

0x66

0x84

0x03

0x32

0x62

0x27

0x48

0x67

0x85

0x11

0x81

0x72

0x28

0x49

0x68

0x86

0x04

0x08

0xD1

0x29

0x4A

0x69

0x87

0x05

0x14

0x0A

0x2A

0x53

0x6A

0x88

0x21

0x42

0x16

0x35

0x54

0x73

0x89

0x31

0x91

0x24

0x36

0x55

0x74

0x8A

0x06

0xA1

0x34

0x37

0x56

0x75

0x92

0x23

0xB1

0xE1

0x38

0x57

0x76

0x93

0x41

0xC1

0x25

0x39

0x58

0x77

0x94

0x51

0x09

0xF1

0x3A

0x59

0x78

0x95

0x07

0x23

0x17

0x43

0x5A

0x79

0x96

0x61

0x33

0x18

0x44

0x63

0x7A

0x97

0x71

0x52

0x19

0x45

0x64

0x82

0x98

0x99

0x9A

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xB2

0xB3

0xB4

0xB5

0xB6

0xD3

0xE9

0xB7

0xD4

0xEA

0xB8

0xD5

0xF2

0xB9

0xD6

0xF3

0xBA

0xD7

0xF4

0xC2

0xD8

0xF5

0xC3

0xD9

0xF6

0xC4

0xDA

0xF7

0xC5

0xE2

0xF8

0xC6

0xE3

0xF9

0xC7

0xE4

0xFA

0xC8

0xE5

0xC9

0xE6

0xCA

0xE7

0xD2

0xE8

};

www.onsemi.com

19

AP0201AT

Embedded Data and Statistics

Table 10. TWO−WIRE INTERFACE ID ADDRESS

Some ON Semiconductor sensor’s support a feature that,

if enabled, inserts two extra lines at the beginning and end

of each frame which contain information about that frame.

The first two lines contain specific register values that were

used to capture that frame. These values allow the host to

know certain important things about how the sensor was

configured for that frame, e.g. exposure, gain, image size,

etc. The last two lines contain statistics about the image that

was captured, e.g. mean values, intensity histograms, etc.

In Ethernet mode AP0200AT sends out 4 lines of Sensor

Embedded data over Ethernet for every frame. Each line is

carried in a separate UDP packet. The destination port and

IP address can be specified. By default the destination IP

address and port are set to 255.255.255.255 and 50010.

UDP packet’s payload consists of following data bytes:

1. Four byte of Timestamp to match with the frame.

2. Four byte of line number. AP0201AT sends line

numbers zero and one at the beginning of the

SWITCHING

S

ADDR

Two−Wire Interface Address ID

0

0x90

1

0xBA

Start Condition

A start condition is defined as a HIGH−to−LOW

transition on SDATA while SCLK is HIGH.

At the end of a transfer, the master can generate a start

condition without previously generating a stop condition;

this is known as a “repeated start” or “restart” condition.

Data Transfer

Data is transferred serially, 8 bits at a time, with the MSB

transmitted first. Each byte of data is followed by an

acknowledge bit or a no−acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte

and for message bytes. One data bit is transferred during

each SCLK clock period. SDATA can change when SCLK is

low and must be stable while SCLK is HIGH.

frame. Line numbers two and three are sent at the

end of the frame.

3. Embedded Data.

Slave Address/Data Direction Byte

SUPPORTRED SPI DEVICES

Bits [7:1] of this byte represent the device slave address

and bit [0] indicates the data transfer direction. A “0” in bit

[0] indicates a write, and a “1” indicates a read. The default

slave addresses used by the AP0200AT are 0x90 (write

address) and 0x91 (read address). Alternate slave addresses

of 0xBA (write address) and 0xBB (read address) can be

selected by asserting the SADDR input signal.

The supported devices are those that conform to the

JEDEC−compliant programming interface. Please contact

ON Semiconductor for specific design criteria and

requirements. The maximum size supported in 2 GB.

SLAVE TWO−WIRE SERIAL INFTERFACE (CCIS)

The two−wire slave serial interface bus enables read/write

access to control and status registers within the AP0200AT.

The interface protocol uses a master/slave model in which

a master controls one or more slave devices.

Message Byte

Message bytes are used for sending register addresses and

register write data to the slave device and for retrieving

register read data. The protocol used is outside the scope of

the two−wire serial interface specification.

Protocol

Data transfers on the two−wire serial interface bus are

performed by a sequence of low−level protocol elements, as

follows:

Acknowledge Bit

Each 8−bit data transfer is followed by an acknowledge bit

or a no−acknowledge bit in the SCLK clock period following

the data transfer. The transmitter (which is the master when

writing, or the slave when reading) releases SDATA. The

receiver indicates an acknowledge bit by driving SDATA

LOW. As for data transfers, SDATA can change when SCLK

is LOW and must be stable while SCLK is HIGH.

• a start or restart condition

• a slave address/data direction byte

• a 16−bit register address

• an acknowledge or a no−acknowledge bit

• data bytes

• a stop condition

No−Acknowledge Bit

The bus is idle when both SCLK and SDATA are HIGH.

Control of the bus is initiated with a start condition, and the

bus is released with a stop condition. Only the master can

generate the start and stop conditions.

The SADDR pin is used to select between two different

addresses in case of conflict with another device. If SADDR

is LOW, the slave address is 0x90; if SADDR is HIGH, the

slave address is 0xBA. See Table 10. The user can change the

slave address by changing a register value.

The no−acknowledge bit is generated when the receiver

does not drive SDATA low during the SCLK clock period

following a data transfer. A no−acknowledge bit is used to

terminate a read sequence.

Stop Condition

A stop condition is defined as a LOW−to−HIGH transition

on SDATA while SCLK is HIGH.

www.onsemi.com

20

AP0201AT

Protocol

ETHERNET INTERFACE

The AP0201AT supports the following Ethernet

protocols.

Overview

AP0201AT’s Ethernet mode has complete support for

configuring the part and streaming video out. By default

IPv4 and IPv6 are enabled. The default MAC address and IP

address are in the table below. For a complete set of default

settings and configurable variables refer to the AP0201AT

Register Reference. AP0201AT supports time precision

protocols to synchronize several cameras.

• IP Protocols:

♦ IPv4 − Fully supported. ICMP, IGMP, ARP, UDP

and TCP

♦ IPv6 − Please talk to your design support engineer

• Command Protocols

♦ UDP − ON Semiconductor UDP−based Host

command protocol

♦ Some/IP

• Streaming Protocol:

Type

MAC

IPv4

IPv6

Default Address

2:00:00:00:00:01

192.168.1.5

♦ AVB (IEEE 1722) – The AP0201AT can be

configured to send H.264 or MJPEG video packets

over IEEE 1722 protocol or RTP protocol.

♦ IEEE 1722 is a layer 2 transport protocol. The

destination MAC address, VLAN number and

stream ID are configurable.

fe80::ff:fe00:0

AP0201AT also supports a UDP−based protocol with ON

Semiconductor host commands. Using this protocol all

registers and variables are accessible.

AP0201AT MAC supports MII, GMII and RMII

protocols. Video can be streamed in MJPEG or H.264 format

over RTP or AVB (IEEE 1722a) protocols.

♦ RTP − Real−time Transport Protocol: RTP is

designed for end−to−end transfer of streaming video.

destination ip address, ,received port and MAC

address are configurable.

Registers and variables can be modified using HCI access

commands over Ethernet or through the serial interface. For

initial settings of these variables, firmware will check NVM

before booting up. (Please refer to the network section of the

HCI document for a discussion of all Ethernet firmware and

hardware variables.)

• Video Compression Protocol:

♦ H.264 – profiles supported: constrained baseline

(intra frames only) and high10intra level required:

up to 5.0 Both Annex B and RFC6184 formatting

are supported.

♦ MJPEG – JPEG compression of YCbCr 4:2:0

images with standard headers or RFC2435 headers.

• Precision Time Protocol:

♦ IEEE 1588−2008 (PTP)

♦ Delay Mechanism

Features

• Ethernet hardware

♦ 100 Mb and 1 Gb Ethernet speed

♦ Configurable MAC

• Ipv4

− End−to−End (Multicast)

− Peer−to−Peer (Multicast)

♦ PTP Operational Mode

− Master

• DHCP for dynamic IP address configuration

• Network QoS and communication integrity check using

ON Semiconductor UDP based commands

• Network status

− Slave (default)

♦ Best Master Clock (BMC) Algorithm

♦ PTP Supported Messages

− Announce message

• Communication integrity check over

ON Semiconductor−UDP

− Sync and Follow_Up message

− Delay_Req and Delay_Resp messages

− Pdelay_req and Pdelay_Resp_Follow_Up

messages

• Support for patching firmware over Ethernet and serial

interface

• Support for dynamic variable updates

• Monitoring AP0201AT registers

− Management message

♦ IEEE 802.1as (gPTP)

• Configuration Protocols

• VLAN support: Video Ethernet packets (IEEE1772 or

RTP) can be sent with a user−specified VLAN ID.

• NVRAM

♦ DHCP4 − IP address, Subnet Mask, Domain Name,

and Host Name can be updated via DHCP4

♦ DHCP6

♦ Enabling and Disabling Protocols

♦ Updating variables in boot−time

♦ Setting unique MAC and IP address

• Custom Diagnostic Protocol − ON Semiconductor

• Persistent Storage of Runtime Configuration (Under

command protocol can be used to retrieve diagnostic

Review)

www.onsemi.com

21

AP0201AT

information from the hardware. Refer to the AP0201AT

Technical Note that describes the protocol in detail.

executed by on chip firmware and the results are reported

back. EEPROM or Flash memory is also available to store

commands for later execution.

Full details of the Host Command Interface can be found

in the AP0201AT Host Command Interface (HCI)

Specification document.

• Hybrid operation mode: While the AP201 is in Ethernet

mode, all the configurations including patches can be

applied using the serial connection. Nevertheless, the

video will stream out over Ethernet. This feature is

useful if customer uses a micro−controller and does not

want to connect a NVM(flash/eeprom) to the part.

• Metadata UDP packets: AP201AT sends out 4 metadata

UDP packets for every frame. These packets included 4

bytes if timestamp, 4 bytes of line number and sensor

specific data.

LICENSE AGREEMENTS

Portions of our 1588 support code were leveraged from

BSD under the following license:

Steven Kreuzer,

Martin Burnicki,

• Proxy Service: AP0201AT can open up to 4 UDP

sockets over the serial interface. The AP0201AT can

then send or receive packets over a user−specified port

using these sockets. If proxy service is enabled,

AP0201AT does not manipulate packet payload for

these sockets and is transparent for these sockets. There

are special set of host commands that customer can use

over the serial interface to open a socket, send data,

receive data and close sockets.

Jan Breuer,

Gael Mace,

Alexandre Van Kempen,

Inaqui Delgado,

Rick Ratzel,

National Instruments.

Steven Kreuzer,

Martin Burnicki,

For additional information, please refer to the technical

note TN−09−333: AP0200AT Ethernet Quick Start Guide.

Jan Breuer,

Gael Mace,

Alexandre Van Kempen

Williams

Metadata

In Ethernet mode AP0200AT sends out 4 lines of metadata

over Ethernet for every frame. Each line is carried in a

separate UDP packet. Costumer can specify the destination

port and IP address. By default, the destination IP address

and port are set to 255.255.255.255 and 50010.

The UDP packet’s payload consists of following data

bytes:

Redistribution and use in source and binary forms, with or

without modification, are permitted provided that the

following conditions are met:

1. Redistributions of source code must retain the

above copyright notice, this list of conditions and

the following disclaimer.

2. Redistributions in binary form must reproduce the

above copyright notice, this list of conditions and

the following disclaimer in the documentation

and/or other materials provided with the

distribution.

1. Four byte of Timestamp to match the frame.

2. Four byte of line number. AP0200AT sends line

numbers zero and one at the beginning of frame.

Line numbers two and three are sent at the end of

frame.

3. Metadata itself.

Supported PHYs

The AP0201AT is compatible with most 100 Mbs MII

PHYs. We have specifically tested with the following

automotive−qualified PHYs:

THIS SOFTWARE IS PROVIDED BY THE

COPYRIGHT HOLDERS AND CONTRIBUTORS ”AS

IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,

INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

WARRANTIES OF MERCHANTABILITY AND

FITNESS FOR A PARTICULAR PURPOSE ARE

DISCLAIMED. IN NO EVENT SHALL THE

COPYRIGHT OWNER OR CONTRIBUTORS BE

LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

DAMAGES (INCLUDING, BUT NOT LIMITED TO,

PROCUREMENT OF SUBSTITUTE GOODS OR

SERVICES;

1. BroadR Reach BCM89810, and

2. Micrel KMZ8051MNL. The AP0201AT is also

compatible with most RMII PHYs (please check

with your design support team for details).

The AP0201AT also supports 1Gb Ethernet operation and

has been tested with the Micrel KSZ9031MNX PHY.

The AP0201AT is also compatible with most RMII PHYs.

For all RMII, MII, and GMII PHYs not listed here, please

check with your support team for details.

HOST COMMAND INTERFACE

LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

INTERRUPTION) HOWEVER CAUSED AND ON ANY

THEORY OF LIABILITY, WHETHER IN CONTRACT,

The AP0201AT has a mechanism to write higher level

commands, the Host Command Interface (HCI). Once a

command has been written through the HCI, it will be

www.onsemi.com

22

AP0201AT

STRICT LIABILITY, OR TORT (INCLUDING

SPECIFICATIONS

NEGLIGENCE OR OTHERWISE) ARISING IN ANY

WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Caution: Stresses greater than those listed in Table 11

may cause permanent damage to the device. This is a stress

rating only, and functional operation of the device at these

or any other conditions above those indicated in the

operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

The views and conclusions contained in the software and

documentation are those of the authors and should not be

interpreted as representing official policies, either expressed

or implied, of the FreeBSD Project.

Table 11. ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

Min

−0.3

1.7

Max

4.95

4.2

Unit

V

Digital power (V _REG)

DD

Host I/O power (V IO_H)

V

DD

Sensor I/O power (V IO_S)

1.7

V

DD

PLL power (V _PLL)

1.1

1.8

V

DD

Digital core power (V

)

1.1

1.8

V

DD

OTPM power (V IO_OTPM)

2.25

2.6

4.95

4.2

V

DD

HiSPi power (V IO_PHY)

V

DD

DC Input Voltage

−0.3

−50

V

IO_*+0.3

150

V

DD

DC Output Voltage

Storage Temperature

V

DD

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Table 12. ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

Parameter

Supply input to on−chip regulator (V _REG)

Min

−0.3

1.71

1.14

2.66

2.38

−40

Typ

1.8

Max

1.89

3.46

2.94

1.26

2.94

3.47

105

Unit

V

DD

Host I/O voltage (V IO_H)

1.8/2.8/3.3

1.8/2.8

1.2

V

DD

Sensor I/O voltage (V IO_S)

V

DD

Core voltage (V

)

V

DD

PLL voltage (V _PLL)

1.2

V

DD

HiSPi PHY voltage (V _PHY)

2.8

V

DD

OTPM power supply (V IO_OTPM)

2.5/3.3

V

DD

Functional operating temperature (ambient − T )

°C

A

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

www.onsemi.com

23

AP0201AT

I/O TIMING

MII I/O Timing

TX_CLK

TXD

t

hold_txd

setup_txd

RX_CLK

RXD

t

hold_rxd

setup_rxd

Figure 13. MII I/O Timing Diagram

Table 13. MII I/O TIMING CHARACTERISTICS

Symbol

Parameter

Conditions

Min

Max

Unit

MHz

ns

Freq

TX_CLK and RX_CLK Input clocks

1.8 V to 3.3 V, 25 pF load

25−110 ppm

25+110 ppm

t

TXD[3:0], TX_ERR, TX_EN, setup to

TX_CLK input rise

15.0

setup_txd

t

TXD[3:0], TX_ERR, TX_EN hold from

TX_CLK input rise

1.8 V to 3.3 V, 25 pF load

1.8 V to 3.3 V

2.0

8.0

ns

hold_txd

t

RXD[3:0], RX_ERR, CRS_DV setup to

RX_CLK input rise

setup_rxd

t

RXD[3:0], RX_ERR, CRS_DV hold from

RX_CLK input rise

1.8 V to 3.3 V

hold_rxd

www.onsemi.com

24

AP0201AT

RMII I/O Timing

TX_CLK

TXD

t

hold_txd

setup_txd

RX_CLK

RXD

t

hold_rxd

setup_rxd

Figure 14. RMII I/O Timing Diagram

Table 14. RMII I/O TIMING CHARACTERISTICS

Symbol

Parameter

Conditions

Min

Max

Unit

MHz

ns

Freq

TX_CLK and RX_CLK Input clocks

1.8 V to 3.3 V, 25 pF load

50 − 110 ppm 50 + 110 ppm

t

TXD[1:0], TX_ERR, TX_EN setup to

TX_CLK input rise

4.0

setup_txd

t

TXD[1:0], TX_ERR, TX_EN hold from

TX_CLK input rise

1.8 V to 3.3 V, 25 pF load

1.8 V to 3.3 V

2.0

4.0

2.0

ns

hold_txd

t

RXD[1:0], RX_ERR, CRS_DV setup to

RX_CLK input rise

setup_rxd

t

RXD[1:0], RX_ERR, CRS_DV hold from

RX_CLK input rise

1.8 V to 3.3 V

hold_rxd

www.onsemi.com

25

AP0201AT

GMII I/O Timing

GTX_CLK

TXD

t

hold_txd

setup_txd

RX_CLK

RXD

t

hold_rxd

setup_rxd

Figure 15. GMII I/O Timing Diagram

Table 15. GMII I/O TIMING CHARACTERISTICS

Symbol

Freq

Parameter

Conditions

Min

Max

Unit

MHz

ns

GTX_CLK output frequency

2.5 V to 3.3 V, 10 pF load 125 − 110 ppm 125 + 110 ppm

Freq

TXD[7:0], TX_EN, TX_ERR setup to

GTX_CLK input rise

2.5 V to 3.3 V, 10 pF load

2.5 V to 3.3 V

2.5

0.5

2.3

0.3

t

TXD[7:0], TX_EN, TX_ERR hold from

GTX_CLK output rise

ns

setup_txd

t

RXD[7:0], RX_ERR, CRS_DV setup to

RX_CLK input rise

hold_txd

t

RXD[7:0], RX_ERR, CRS_DV hold from

RX_CLK input rise

2.5 V to 3.3 V

setup_rxd

ELECTRICAL CHARACTERISTICS

Table 16. DC ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Condition

Min

Max

Unit

Notes

V

IH

Input HIGH voltage

V

DD

IO_H or

−

V

5

DD

V

IO_S*0.8

V

Input LOW voltage

Input leakage current

Output HIGH voltage

Output LOW voltage

−

V

DD

IO_H or

V

mA

V

5

6

IL

DD

V

IO_S*0.2

10

I

IN

V

DD

= 0 V or V

=

IN

V

IO_H or V IO_S*

DD

V

OH

V

DD

IO_H or

IO_S*0.80

−

DD

V

OL

−

V

DD

IO_H or

IO_S*0.2

V

DD

V

5. V and V have min/max limitations specified by absolute ratings.

IL

IH

6. Excludes pins that have internal PU resistors.

www.onsemi.com

26

AP0201AT

Input Clocks

Table 17. INPUT CLOCKS

Clock

Min (MHz)

Typical (MHz)

Max (MHz)

Description

EXTCLK

10 − osc

20 − xtal

27

29

Primary system clock. Drives PLLs. Crystal frequency range is

20 − 29 MHz, otherwise 10 − 29 MHz.

PIXCLK_IN

HISPI_CLK

10

30

74.25

80

Clock for parallel input bus (from sensor).

Clock for HISPI image data receiver.

300

Output Clocks

Table 18. OUTPUT CLOCKS

Clock

MCLK

Min (MHz)

Typical (MHz)

27

Max (MHz)

29

Description

10

18

Primary clock to sensor. Equals EXTCLK.

GTX_CLK

74.25/25

80/125

Clock of parallel output bus.

If pad voltage is 1.8 V nominal, then max frequency is 80 MHz.

If 2.5 V or 3.3 V, then 125 MHz. See electrical specs.

SPI_CLK

1

20

SPI clock to nonvolatile external memory.

t_

FRAMESYNC

t_

FRAME_SYNC

TRIGGER_PROP

TRIGGER_OUT

FV_OUT

t_

FRMSYNC_FVH

Figure 16. Frame_Sync Diagram

Table 19. TRIGGER TIMING

Parameter

Name

Conditions

Min

Typ

Max

Unit

FRAME_SYNC to FV_OUT

t

8 lines + exposure

time + sensor delay

−

Lines

FRMSYNC_FVH

FRAME_SYNC to

TRIGGER_OUT

t

−

30

ns

TRIGGER_PROP

t

3

−

EXTCLK

cycles

FRAME_SYNC

FRAMESYNC

www.onsemi.com

27

AP0201AT

Table 20. STANDBY CURRENT CONSUMPTION

(Default Setup Conditions: f

= 27 MHz, V _REG = 1.8 V, V IO_H not included in measurement, V IO_S = 1.8 V,

EXTCLK

DD

V

DD

IO_OTPM = 2.8 V, V _PHY = 2.8 V, T = 105°C unless otherwise stated)

DD A

Parameter

Condition

Typ

1.50

0.19

1.20

0.18

0.00

7.46

3.50

Max

1.91

0.24

1.52

0.23

0.00

94.7

Unit

mA

mW

mA

IDD_REG

IDDIO_S

IDDIO_H

IDDIO_OTPM

IDDIO_PHY

Total Standby Power

t

= 27 MHz

EXTCLK

Table 21. INRUSH CURRENT

Supply

Voltage

Typ

140

90

Max

190

105

180

160

180

Unit

mA

V

DD

V

DD

V

DD

IO_H

IO_S

2.8/3.3

1.8

2.8

130

140

180

V

DD

IO_OTPM

2.8/3.3

V

DD

IO_PHY

Table 22. OPERATING CURRENT CONSUMPTION − SENSOR PARALLEL OUTPUT

(Default Setup Conditions: f

= 27 MHz, V _REG = 1.8 V, V IO_H not included in measurement, V IO_S = 1.8 V,

EXTCLK

DD DD DD

V

DD

IO_OTPM = 2.5 V, V _PHY = 2.5 V, T = 105°C unless otherwise noted)

DD A

Symbol

_REG

Conditions

MJPEG

H.264

Min

Typ

85

110

3

Max

108

140

4

Unit

mA

mW

V

DD

V

IO_S

DD

IO_H

DD

MJPEG

H.264

3

4

V

MJPEG

H.264

35

0.2

0

V

IO_OTPM

MJPEG

H.264

0.3

0

DD

V

DD

_PHY

MJPEG

H.264

0

Total power consumption

MJPEG

H.264

159

204

202

259

Table 23. OPERATING CURRENT CONSUMPTION − SENSOR HISPI OUTPUT

(Default Setup Conditions: f

= 27 MHz, V _REG = 1.8 V, V IO_H not included in measurement, V IO_S = 1.8 V,

EXTCLK

DD DD DD

V

DD

IO_OTPM = 2.5 V, V _PHY = 2.5 V, T = 105°C unless otherwise stated)

DD A

Symbol

IO_REG

Conditions

H.264

Min

Typ

110

3

Max

140

4

Unit

mA

mW

I

DD

I

IO_S

IO_H

H.264

DD

I

H.264

35

I

IO_OTPM

H.264

0.2

0.3

212

0.3

0.4

DD

I

_PHY

H.264

DD

Total power consumption

H.264

270

www.onsemi.com

28

AP0201AT

TWO−WIRE SERIAL REGISTER INTERFACE

The electrical characteristics of the master two−wire

serial interface (M_SCLK, M_SDATA) are shown in

Figure 17 and Table 24.

S

DATA

t

f

t

f

t

r

t

r

t

BUF

LOW

SU;DAT

HD;STA

S

CLK

t

SU;STO

HD;STA

SU;STA

t

HIGH

HD;DAT

S

Sr

P

S

Figure 17. Master Two Wire Serial Bus Timing Parameters (CCIM)

Table 24. MASTER TWO−WIRE SERIAL BUS CHARACTERISTICS (CCIM)

(Default Setup Conditions: f

otherwise stated)

= 27 MHz, V IO_H = V _OTPM = 2.8 V, V _REG = V IO_S = 1.8 V, T = 25°C unless

EXTCLK

DD

A

Standard Mode

Fast Mode

Min

0

Max

Min

Max

Parameter

Clock Frequency

Symbol

Unit

KHz

ms

M_S

f

100

0

400

CLK

SCL

Hold time (repeated) START condition.

After this period, the first clock pulse is generated.

t

4.0

0.6

HD;STA

LOW period of the M_S

clock

t

4.7

4.0

4.7

1.2

0.6

0

ms

CLK

LOW

HIGH period of the M_S

t

HIGH

CLK

Set−up time for a repeated START condition

t

SU;STA

HD;DAT

Data hold time

t

0

3.45

(Note 9)

0.9

(Note 9)

(Note 8)

Data set−up time

t

250

100

ns

SU;DAT

Rise time of both M_S

(10−90%)

and M_S

signals

t

r

1000

300

20+0.1Cb

(Note 10)

300

DATA

CLK

Fall time of both M_S

(10−90%)

and M_S

signals

t

f

20+0.1Cb

(Note 10)

ns

DATA

CLK

Set−up time for STOP condition

t

4.0

4.7

0.6

1.3

ms

SU;STO

Bus free time between a STOP and START

condition

t

BUF

Capacitive load for each bus line

Cb

400

3.3

30

400

3.3

30

pF

KW

Serial interface input pin capacitance

C

IN_SI

M_S

max load capacitance

C

LOAD_SD

DATA

pull−up resistor

R

1.5

4.7

1.5

4.7

SD

7. All values referred to VIHmin = 0.9 V IO and VILmax = 0.1 V IO levels. EXCLK = 27 MHz.

DD

8. A device must internally provide a hold time of at least 300 ns for the M_S

signal to bridge the undefined region of the falling edge of

DATA

M_S

.

CLK

9. The maximum t

has only to be met if the device does not stretch the LOW period (t

) of the M_S

signal.

HD;DAT

LOW

CLK

10.Cb = total capacitance of one bus line in pF.

www.onsemi.com

29

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

VFBGA100 7x7

CASE 138AH

ISSUE O

DATE 30 DEC 2014

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON93700F

VFBGA100 7X7

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Email Requests to: orderlit@onsemi.com

TECHNICAL SUPPORT

North American Technical Support:

Voice Mail: 1 800−282−9855 Toll Free USA/Canada

Phone: 011 421 33 790 2910

Europe, Middle East and Africa Technical Support:

Phone: 00421 33 790 2910

For additional information, please contact your local Sales Representative

ON Semiconductor Website: www.onsemi.com

◊

www.onsemi.com

1


型号：	AP0201AT
厂家：	ONSEMI
描述：	AP0201AT High-Dynamic Range (HDR) Image Signal Processor (ISP)
文件：	总31页 (文件大小：473K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AP0201AT [ONSEMI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E