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ASM5I2308AF-2-16-ST [ONSEMI]

2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, 0.150 INCH, ROHS COMPLIANT, SOIC-16;
ASM5I2308AF-2-16-ST
型号： ASM5I2308AF-2-16-ST
厂家： ONSEMI    ONSEMI
描述：

2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, 0.150 INCH, ROHS COMPLIANT, SOIC-16

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ASM5P2308A  
3.3 V Zero-Delay Buffer  
Description  
ASM5P2308A is a versatile, 3.3 V zero−delay buffer designed to  
distribute high−speed clocks. It is available in a 16−pin package. The  
part has an on−chip PLL which locks to an input clock presented on  
the REF pin. The PLL feedback is required to be driven to FBK pin,  
and can be obtained from one of the outputs. The input−to−output  
propagation delay is guaranteed to be less than 250 pS, and the  
output−to−outputskew is guaranteed to be less than 200 pS.  
The ASM5P2308A has two banks of four outputs each, which can  
be controlled by the select inputs as shown in the Select Input  
Decoding Table. If all the output clocks are not required, Bank B can  
be three−stated. The select input also allows the input clock to be  
directly applied to the outputs for chip and system testing purposes.  
Multiple ASM5P2308A devices can accept the same input clock  
and distribute it. In this case the skew between the outputs of the two  
devices is guaranteed to be less than 700 pS.  
http://onsemi.com  
SOIC−16  
S SUFFIX  
TSSOP−16  
T SUFFIX  
CASE 751BG  
CASE 948AN  
ASM5P2308A is available in five different configurations. Refer to  
ASM5P2308A Configurations Table. The ASM5P2308A−1 is the base  
part, where the output frequencies equal the reference clock input. The  
ASM5P2308A−1H is the high−drive version of the −1 and the rise and  
fall times on this device are faster.  
ASM5P2308A−2 allows the user to obtain 2x and 1x frequencies on  
each output bank. The exact configuration and output frequencies  
depends on which output drives the feedback pin. ASM5P2308A−3  
allows the user to obtain 4x and 2x frequencies on the outputs.  
ASM5P2308A−4 enables the user to obtain 2x clocks on all outputs.  
The ASM5P2308A−5H is a high−drive version with REF/2 output  
on both banks.  
PIN CONFIGURATION  
1
FBK  
REF  
CLKA1  
CLKA2  
CLKA4  
CLKA3  
V
V
DD  
DD  
GND  
GND  
CLKB1  
CLKB2  
S2  
CLKB4  
CLKB3  
S1  
ASM5P2308A is an extremely versatile part, and can be used in a  
variety of applications.  
(Top View)  
Features  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 10 of this data sheet.  
• Zero Input−output Propagation Delay, Adjustable by Capacitive Load  
on FBK Input  
• Multiple Configurations –  
Refer to ASM5P2308A Configurations Table  
• Input Frequency Range: 10 MHz to 133 MHz  
• Multiple Low−skew Outputs  
♦ Output−output Skew less than 200 pS  
♦ Device−device Skew less than 700 pS  
♦ Two Banks of Four Outputs Each,  
Three−state by Two Select Inputs  
• Less than 200 pS Cycle−to−Cycle Jitter (−1, −1H, −2, −3, −4, −5H)  
• 16−pin SOIC and TSSOP Packages  
• 3.3 V Operation  
• Commercial and Industrial Temperature Range  
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
August, 2011 − Rev. 3  
ASM5P2308A/D  
ASM5P2308A  
FBK  
/2  
MUX  
PLL  
/2  
REF  
CLKA1  
CLKA2  
CLKA3  
CLKA4  
Extra Divider (−5H)  
Extra Divider (−3, −4)  
S2  
S1  
Select  
Input  
Decoding  
/2  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
Extra Divider (−2, −3)  
Figure 1. Block Diagram  
Table 1. SELECT INPUT DECODING FOR ASM5P2308A  
S2  
0
S1  
0
Clock A1 − A4  
Three−state  
Driven  
Clock B1 − B4  
Three−state  
Three−state  
Driven  
Output Source  
PLL  
PLL Shut−Down  
Y
N
Y
N
0
1
PLL  
1
0
Driven (Note 1)  
Driven  
Reference  
PLL  
1
1
Driven  
1. Outputs are non−inverted on 2308A−2 and 2308A−3 in bypass mode, S2 = 1 and S1 = 0.  
Table 2. ASM5P2308A CONFIGURATIONS (This table is applicable when PLL is not Shut Down.)  
Device  
Feedback From  
Bank A or Bank B  
Bank A  
Bank A Frequency  
Reference  
Bank B Frequency  
Reference  
ASM5P2308A (−1, −1H)  
ASM5P2308A−2  
ASM5P2308A−2  
ASM5P2308A−3  
ASM5P2308A−3  
ASM5P2308A−4  
ASM5P2308A−5H  
Reference  
Reference /2  
Bank B  
2 X Reference  
2 X Reference  
4 X Reference  
2 X Reference  
Reference /2  
Reference  
Bank A  
Reference or Reference (Note 2)  
2 X Reference  
Bank B  
Bank A or Bank B  
Bank A or Bank B  
2 X Reference  
Reference /2  
2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P2308A−2.  
http://onsemi.com  
2
 
ASM5P2308A  
Zero Delay and Skew Control  
All outputs should be uniformly loaded to achieve Zero Delay between input and output.  
1500  
1000  
500  
0
5
10  
15  
20  
25 30  
−30 −25  
−20  
−15  
−10  
−5  
0
−500  
−1000  
−1500  
Figure 2. Output Load Difference: FBK Load − CLKA/CLKB Load (pF)  
To close the feedback loop of the ASM5P2308A, the FBK  
can be driven from any of the eight available clock outputs.  
The output driving the FBK pin will be driving a total load  
of 7 pF plus any additional load that it drives. The relative  
loading of this output (with respect to the remaining outputs)  
can adjust the input−output delay. This is shown in the above  
graph.  
For applications requiring zero input−output delay, all  
outputs including the one providing feedback should be  
equally loaded. If input−output delay adjustments are  
required, use the above graph to calculate loading  
differences between the feedback output and remaining  
outputs. For zero output−output skew, be sure to load outputs  
equally.  
Table 3. PIN DESCRIPTION FOR ASM5P2308A  
Pin #  
Pin Name  
Description  
1
REF (Note 3)  
CLKA1 (Note 4)  
CLKA2 (Note 4)  
Input reference clock frequency, 5 V tolerant input  
2
Buffered clock output, bank A  
Buffered clock output, bank A  
3.3 V supply  
3
4
V
DD  
5
GND  
Ground  
6
CLKB1 (Note 4)  
CLKB2 (Note 4)  
S2 (Note 5)  
Buffered clock output, bank B  
Buffered clock output, bank B  
Select input, bit 2  
7
8
9
S1 (Note 5)  
Select input, bit 1  
10  
CLKB3 (Note 4)  
CLKB4 (Note 4)  
GND  
Buffered clock output, bank B  
Buffered clock output, bank B  
Ground  
11  
12  
13  
V
DD  
3.3 V supply  
14  
CLKA3 (Note 4)  
CLKA4 (Note 4)  
FBK  
Buffered clock output, bank A  
Buffered clock output, bank A  
PLL feedback input  
15  
16  
3. Weak pull−down.  
4. Weak pull−down on all outputs.  
5. Weak pull−up on these inputs.  
http://onsemi.com  
3
 
ASM5P2308A  
Table 4. ABSOLUTE MAXIMUM RATINGS  
Parameter  
Min  
−0.5  
−0.5  
−0.5  
−65  
Max  
Unit  
V
Supply Voltage to Ground Potential  
DC Input Voltage (Except REF)  
DC Input Voltage (REF)  
+4.6  
V
+ 0.5  
V
DD  
7
V
Storage Temperature  
+150  
260  
°C  
°C  
°C  
V
Max. Soldering Temperature (10 sec)  
Junction Temperature  
150  
Static Discharge Voltage (As per JEDEC STD22− A114−B)  
2000  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
Table 5. OPERATING CONDITIONS  
Parameter  
Description  
Min  
3.0  
0
Max  
3.6  
70  
85  
30  
15  
7
Unit  
V
V
DD  
Supply Voltage  
T
A
Operating Temperature  
(Ambient Temperature)  
Commercial temperature  
Industrial temperature  
°C  
−40  
C
Load Capacitance, below 100 MHz  
pF  
pF  
pF  
L
L
C
Load Capacitance, from 100 MHz to 133 MHz  
Input Capacitance (Note 6)  
C
IN  
6. Applies to both Ref Clock and FBK.  
Table 6. ELECTRICAL CHARACTERISTICS  
Parameter  
Description  
Input LOW Voltage  
Input HIGH Voltage  
Input LOW Current  
Input HIGH Current  
Test Conditions  
Min  
Max  
Unit  
V
0.8  
V
V
IL  
IH  
IL  
V
2.2  
I
V
V
= 0 V  
50  
100  
0.4  
mA  
mA  
V
IN  
I
IH  
= V  
DD  
IN  
V
Output LOW Voltage  
(Note 7)  
I
I
= 8 mA (−1, −2, −3, −4)  
= 12 mA (−1H, −5H)  
OL  
OH  
DD  
OL  
OL  
V
Output HIGH Voltage  
(Note 7)  
I
I
= −8 mA (−1, −2, −3, −4)  
= −12 mA (−1H, −5H)  
2.4  
V
OH  
OH  
I
Supply Current  
(Note 8)  
Unloaded outputs at 100 MHz,  
Select inputs at V or GND  
Commercial temp.  
40  
45  
30  
35  
mA  
DD  
Industrial temp.  
Commercial temp.  
Industrial temp.  
(−1, −1H, −2,−3,−4)  
Unloaded outputs; 100 MHz  
REF, Select inputs at V or  
DD  
GND (−5H)  
Unloaded outputs at 66 MHz  
Commercial temp.  
Industrial temp.  
Commercial temp.  
Industrial temp.  
32  
34  
18  
20  
Unloaded outputs at 33 MHz  
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.  
8. Supply Currents are measured for PLL−Driven Mode (S2 = 1, S1 = 1).  
http://onsemi.com  
4
 
ASM5P2308A  
Table 7. SWITCHING CHARACTERISTICS (For all measurements use Test Circuit #1.) (Note 9)  
Parameter  
Test Conditions  
Min  
10  
12  
15  
20  
5
Typ  
Max  
100  
100  
100  
100  
66.67  
133  
133  
133  
133  
60  
Unit  
Output Frequency  
(Refer to ASM5P2308A  
Configurations Table)  
30 pF load  
( −1, −1H)  
MHz  
(−2)  
(−3)  
(−4)  
(−5H)  
15 pF load  
( −1, −1H)  
10  
12  
15  
20  
40  
MHz  
(−2)  
(−3)  
(−4)  
Duty Cycle (Note 10)  
(−1, −2, −3, −4, −1H, −5H)  
Measured at 1.4 V, F  
Measured at 1.4 V, F  
≤ 66.66 MHz, 30 pF load  
50  
50  
%
%
OUT  
Duty Cycle (Note 10)  
(−1, −2, −3, −4, −1H, −5H)  
≤ 50 MHz, 15 pF load  
45  
55  
OUT  
Output Rise Time (Note 10)  
Measured between 0.8 V  
and 2.0 V, 30 pF load  
Commercial temp.  
Industrial temp.  
2.2  
2.5  
1.5  
nS  
(−1, −2, −3, −4)  
Output Rise Time (Note 10)  
(−1, −2, −3, −4)  
Measured between 0.8 V  
and 2.0 V, 15 pF load  
Commercial temp.,  
Industrial temp.  
nS  
nS  
nS  
Output Rise Time (Note 10)  
(−1H, −5H)  
Measured between 0.8 V  
and 2.0 V, 30 pF load  
1.5  
2
Output Fall Time (Note 10)  
(−1, −2, −3, −4)  
Measured between 2.0 V  
and 0.8 V, 30 pF load  
Commercial temp.  
Industrial temp.  
2.2  
2.5  
1.5  
Output Fall Time (Note 10)  
(−1, −2, −3, −4)  
Measured between 2.0 V  
and 0.8 V, 15 pF load  
Commercial temp.,  
Industrial temp.  
nS  
nS  
pS  
Output Fall Time (Note 10)  
(−1H, −5H)  
Measured between 2.0 V  
and 0.8 V, 30 pF load  
1.25  
1.5  
Output−to−output skew on same bank (Note 10)  
(−1, −2, −3, −4)  
All outputs equally loaded  
200  
Output−to−output skew (Note 10) (−1H, −5H)  
All outputs equally loaded  
All outputs equally loaded  
200  
200  
pS  
pS  
Output bank A −to− output Bank B skew (Note 10)  
(−1, −4, −5H)  
Output bank A −to− output  
All outputs equally loaded  
400  
250  
700  
pS  
pS  
Bank B skew (Note 10) (−2, −3)  
Delay, REF Rising Edge to FBK Measured at V /2  
Rising Edge (Notes 10, 11)  
0
0
DD  
Device−to−Device Skew  
(Note 10)  
Measured at V /2 on the FBK pins of the device  
DD  
Cycle−to−Cycle Jitter (Note 10) Measured at 66.67 MHz, loaded outputs, 15 pF load  
200  
200  
125  
(−1, −1H, −4, −5H)  
Measured at 66.67 MHz, loaded outputs, 30 pF load  
Measured at 133.3 MHz, loaded outputs, 15 pF load  
(Note 12)  
Cycle−to−Cycle Jitter (Note 10) Measured at 66.67 MHz, loaded outputs, 15 pF load  
400  
1.0  
(−2, −3)  
Measured at 66.67 MHz, loaded outputs, 30 pF load  
PLL Lock Time (Note 10)  
Stable power supply, valid clock presented on REF and  
FBK pins  
mS  
9. All parameters are specified at Commercial and Industrial temperature unless stated otherwise.  
10.Parameter is guaranteed by design and characterization. Not 100% tested in production.  
11. Refer to Test Circuit #2 *Not applicable for (−1, −2, −1H, −2H).  
12.Not applicable for −5H.  
http://onsemi.com  
5
 
ASM5P2308A  
Switching Waveforms  
t
1
t
2
1.4 V  
1.4 V  
1.4 V  
OUTPUT  
Figure 3. Duty Cycle Timing  
2 V  
2 V  
0.8 V  
VDD  
0 V  
0.8 V  
OUTPUT  
t
3
t
4
Figure 4. All Outputs Rise/Fall Time  
1.4 V  
OUTPUT  
1.4 V  
OUTPUT  
t
5
Figure 5. Output−Output Skew  
V
DD  
/2  
INPUT  
FBK  
V
DD  
/2  
t
6
Figure 6. Input−Output Propagation Delay  
V
DD  
/2  
FBK, Device1  
V
DD  
/2  
FBK, Device2  
t
7
Figure 7. Device−Device Skew  
http://onsemi.com  
6
ASM5P2308A  
TEST CIRCUIT #1  
22 W  
22 W  
FBK  
+3.3 V  
CLK A / CLK B  
2
C
C
V
DD  
LOAD  
ASM5P2308A  
0.1 mF  
CLK A / CLK B  
GND  
2
LOAD  
TEST CIRCUIT #2  
FBK  
22 W  
22 W  
CLK A / CLK B  
CLK A / CLK B  
+3.3 V  
2
V
DD  
0.1 mF  
ASM5P2308A  
GND  
2
8.2 pF (Note 13)  
Figure 8. Test Circuits  
13.Refer to Test Circuit #2 *Not applicable for (-1, -2, -1H, -2H).  
http://onsemi.com  
7
 
ASM5P2308A  
PACKAGE DIMENSIONS  
SOIC−16, 150 mils  
CASE 751BG−01  
ISSUE O  
SYMBOL  
MIN  
NOM  
MAX  
1.35  
A
A1  
b
1.75  
0.25  
0.51  
0.25  
0.10  
0.33  
0.19  
c
D
E
E1  
e
9.80  
5.80  
3.80  
9.90  
6.00  
10.00  
6.20  
4.00  
E1  
E
3.90  
1.27 BSC  
h
0.25  
0.40  
0º  
0.50  
1.27  
8º  
L
θ
PIN#1 IDENTIFICATION  
TOP VIEW  
D
h
q
A
c
e
b
L
A1  
END VIEW  
SIDE VIEW  
Notes:  
(1) All dimensions are in millimeters. Angles in degrees.  
(2) Complies with JEDEC MS-012.  
http://onsemi.com  
8
ASM5P2308A  
PACKAGE DIMENSIONS  
TSSOP16, 4.4x5  
CASE 948AN−01  
ISSUE O  
b
SYMBOL  
MIN  
NOM  
MAX  
A
A1  
A2  
b
1.10  
0.15  
0.95  
0.30  
0.20  
5.10  
6.50  
4.50  
0.05  
0.85  
0.19  
0.13  
4.90  
6.30  
4.30  
E1  
E
c
D
E
E1  
e
0.65 BSC  
1.00 REF  
L
L1  
0.45  
0.75  
0º  
8º  
θ
e
PIN#1  
IDENTIFICATION  
TOP VIEW  
D
c
A2  
A1  
A
θ1  
L1  
L
SIDE VIEW  
END VIEW  
Notes:  
(1) All dimensions are in millimeters. Angles in degrees.  
(2) Complies with JEDEC MO-153.  
http://onsemi.com  
9
ASM5P2308A  
Table 8. ORDERING INFORMATION  
Part Number  
Marking  
Package Type  
Temperature  
ASM5P2308AF−1−16−ST  
ASM5I2308AF−1−16−ST  
ASM5P2308AF−1−16−SR  
ASM5I2308AF−1−16−SR  
ASM5P2308AF−1−16−TT  
ASM5I2308AF−1−16−TT  
ASM5P2308AF−1−16−TR  
ASM5I2308AF−1−16−TR  
P5P2308AF−1H16ST  
5P2308AF−1  
5I2308AF−1  
5P2308AF−1  
5I2308AF−1  
5P2308AF−1  
5I2308AF−1  
5P2308AF−1  
5I2308AF−1  
5P2308AF−1H  
5I2308AF−1H  
5P2308AF−1H  
5I2308AF−1H  
5P2308AF−1H  
5I2308AF−1H  
5P2308AF−1H  
5I2308AF−1H  
5P2308AF−2  
5I2308AF−2  
5P2308AF−2  
5I2308AF−2  
5P2308AF−2  
5I2308AF−2  
5P2308AF−2  
5I2308AF−2  
5P2308AF−3  
5I2308AF−3  
5P2308AF−3  
5I2308AF−3  
5P2308AF−3  
5I2308AF−3  
5P2308AF−3  
5I2308AF−3  
5P2308AF−4  
5I2308AF−4  
5P2308AF−4  
5I2308AF−4  
5P2308AF−4  
5I2308AF−4  
5P2308AF−4  
5I2308AF−4  
5P2308AF−5H  
5I2308AF−5H  
5P2308AF−5H  
5I2308AF−5H  
5P2308AF−5H  
5I2308AF−5H  
5P2308AF−5H  
5I2308AF−5H  
16−pin 150−mil SOIC−TUBE, Pb free  
Commercial  
Industrial  
16−pin 150−mil SOIC−TUBE, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TUBE, Pb free  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
ASM5I2308AF−1H−16−ST  
P5P2308AF−1H16SR  
16−pin 150−mil SOIC−TUBE, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TUBE, Pb free  
Commercial  
Industrial  
ASM5I2308AF−1H−16−SR  
ASM5P2308AF−1H−16−TT  
ASM5I2308AF−1H−16−TT  
P5P2308AF−1H16TR  
Commercial  
Industrial  
Commercial  
Industrial  
ASM5I2308AF−1H−16−TR  
P5P2308AF−2−16ST  
Commercial  
Industrial  
ASM5I2308AF−2−16−ST  
P5P2308AF−216SR  
16−pin 150−mil SOIC− TUBE, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TUBE, Pb free  
Commercial  
Industrial  
ASM5I2308AF−2−16−SR  
ASM5P2308AF−2−16−TT  
P5I2308AF−216TT  
Commercial  
Industrial  
P5P2308AF−216TR  
Commercial  
Industrial  
ASM5I2308AF−2−16−TR  
ASM5P2308AF−3−16−ST  
ASM5I2308AF−3−16−ST  
ASM5P2308AF−3−16−SR  
ASM5I2308AF−3−16−SR  
ASM5P2308AF−3−16−TT  
ASM5I2308AF−3−16−TT  
P5P2308AF−3−16TR  
Commercial  
Industrial  
16−pin 150−mil SOIC− TUBE, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TUBE, Pb free  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
ASM5I2308AF−3−16−TR  
ASM5P2308AF−4−16−ST  
ASM5I2308AF−4−16−ST  
ASM5P2308AF−4−16−SR  
ASM5I2308AF−4−16−SR  
ASM5P2308AF−4−16−TT  
ASM5I2308AF−4−16−TT  
ASM5P2308AF−4−16−TR  
ASM5I2308AF−4−16−TR  
ASM5P2308AF−5H−16−ST  
ASM5I2308AF−5H−16−ST  
ASM5P2308AF−5H−16−SR  
ASM5I2308AF−5H−16−SR  
ASM5P2308AF−5H−16−TT  
ASM5I2308AF−5H−16−TT  
ASM5P2308AF−5H−16−TR  
ASM5I2308AF−5H−16−TR  
Commercial  
Industrial  
16−pin 150−mil SOIC− TUBE, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TUBE, Pb free  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
16−pin 150−mil SOIC− TUBE, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−pin 150−mil SOIC−TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TUBE, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
http://onsemi.com  
10  
ASM5P2308A  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
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Order Literature: http://www.onsemi.com/orderlit  
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada  
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For additional information, please contact your local  
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ASM5P2308A/D  

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