BC307BRLRM_技术文档

SEMICONDUCTOR TECHNICAL DATA

PNP Silicon

COLLECTOR

1

2

BASE

3

EMITTER

1

2

3

CASE 29–04, STYLE 17

TO–92 (TO–226AA)

MAXIMUM RATINGS

Rating

Collector–Emitter Voltage

Collector–Base Voltage

Emitter–Base Voltage

Symbol BC307, B, C

BC308C

–25

Unit

Vdc

V

CEO

V

CBO

V

EBO

–45

–50

–30

Vdc

–5.0

Vdc

Collector Current — Continuous

I

C

–100

mAdc

Total Device Dissipation @ T = 25°C

Derate above 25°C

P

D

350

2.8

mW

mW/°C

A

Total Device Dissipation @ T = 25°C

Derate above 25°C

P

D

1.0

8.0

Watts

mW/°C

C

Operating and Storage Junction

Temperature Range

T , T

–55 to +150

°C

J

stg

THERMAL CHARACTERISTICS

Characteristic

Symbol

Max

357

125

Unit

°C/W

Thermal Resistance, Junction to Ambient

Thermal Resistance, Junction to Case

R

JA

JC

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

A

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Collector–Emitter Breakdown Voltage

(I = –2.0 mAdc, I = 0)

BC307,B,C

BC308C

V

–45

–25

—

Vdc

(BR)CEO

C

B

Emitter–Base Breakdown Voltage

(I = –100 Adc, I = 0)

BC307,B,C

BC308C

–5.0

—

(BR)EBO

E

C

Collector–Emitter Leakage Current

I

CES

(V

CES

(V

CES

(V

CES

(V

CES

= –50 V, V

= –30 V, V

= –50 V, V

= –30 V, V

= 0)

BC307,B,C

BC308C

BC307,B,C

BC308C

—

–0.2

–15

–4.0

nAdc

BE

= 0) T = 125°C

µA

A

REV 1

2–88

Motorola Small–Signal Transistors, FETs and Diodes Device Data

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)

A

Characteristic

Symbol

Min

Typ

Max

Unit

ON CHARACTERISTICS

DC Current Gain

(I = –10 µAdc, V

C CE

h

FE

—

= –5.0 Vdc)

BC307B

BC307C/308C

—

150

270

—

(I = –2.0 mAdc, V

C

= –5.0 Vdc)

BC307

BC307B/308B

BC307C/308C

120

200

420

—

290

500

800

460

800

CE

(I = –100 mAdc, V

C CE

= –5.0 Vdc)

BC307B

BC307C/308C

—

180

300

—

Collector–Emitter Saturation Voltage

(I = –10 mAdc, I = –0.5 mAdc)

V

Vdc

CE(sat)

—

–0.10

–0.30

–0.25

–0.3

–0.6

—

C

B

(I = –10 mAdc, I = see Note 1)

C

B

(I = –100 mAdc, I = –5.0 mAdc)

Base–Emitter Saturation Voltage

(I = –10 mAdc, I = –0.5 mAdc)

Vdc

BE(sat)

—

–0.7

–1.0

—

C

B

(I = –100 mAdc, I = –5.0 mAdc)

Base–Emitter On Voltage

(I = –2.0 mAdc, V = –5.0 Vdc)

V

–0.55

–0.62

–0.7

BE(on)

C

CE

DYNAMIC CHARACTERISTICS

Current–Gain — Bandwidth Product

f

T

MHz

(I = –10 mAdc, V

= –5.0 Vdc, f = 100 MHz)

CE

BC307,B,C

BC308C

—

280

320

—

C

Common Base Capacitance

(V = –10 Vdc, I = 0, f = 1.0 MHz)

C

—

6.0

pF

dB

cbo

CB

Noise Figure

C

NF

(I = –0.2 mAdc, V

C

= –5.0 Vdc, R = 2.0 kΩ,

S

CE

f = 1.0 kHz)

BC307,B,C

BC308C

—

2.0

10

(I = –0.2 mAdc, V

= –5.0 Vdc, R = 2.0 kΩ,

S

C

CE

f = 1.0 kHz, f = 200 Hz)

2.0

1. I = –10 mAdc on the constant base current characteristic, which yields the point I = –11 mAdc, V

= –1.0 V.

C

CE

Motorola Small–Signal Transistors, FETs and Diodes Device Data

2–89

TYPICAL CHARACTERISTICS

2.0

1.5

–1.0

T = 25°C

A

V

= –10 V

–0.9

–0.8

–0.7

–0.6

–0.5

–0.4

CE

V

@ I /I = 10

BE(sat) C B

T = 25°C

A

1.0

V

BE(on)

@ V = –10 V

CE

0.7

0.5

–0.3

–0.2

–0.1

0

0.3

0.2

V

@ I /I = 10

CE(sat) C B

–0.2 –0.5 –1.0 –2.0 –5.0 –10 –20

–50 –100 –200

–0.1 –0.2

–0.5 –1.0 –2.0

–5.0 –10 –20

–50 –100

I , COLLECTOR CURRENT (mAdc)

C

I , COLLECTOR CURRENT (mAdc)

C

Figure 1. Normalized DC Current Gain

Figure 2. “Saturation” and “On” Voltages

10

7.0

5.0

400

300

C

ib

200

150

V

= –10 V

T = 25°C

A

CE

T = 25°C

A

100

80

3.0

2.0

C

ob

60

40

30

20

–0.5

1.0

–1.0

–2.0 –3.0 –5.0

–10

–20 –30 –50

–0.4 –0.6 –1.0

–2.0

–4.0 –6.0 –10

–20 –30 –40

I , COLLECTOR CURRENT (mAdc)

C

V , REVERSE VOLTAGE (VOLTS)

R

Figure 3. Current–Gain — Bandwidth Product

Figure 4. Capacitances

1.0

150

140

0.5

0.3

V

= –10 V

CE

f = 1.0 kHz

V

= –10 V

CE

f = 1.0 kHz

T = 25°C

A

T = 25°C

A

130

120

110

100

0.1

0.05

0.03

0.01

–0.1

–0.2

–0.5

–1.0

–2.0

–5.0

–10

–0.1

–0.2 –0.3 –0.5

–1.0

–2.0 –3.0 –5.0

–10

I , COLLECTOR CURRENT (mAdc)

C

I , COLLECTOR CURRENT (mAdc)

C

Figure 5. Output Admittance

Figure 6. Base Spreading Resistance

2–90

Motorola Small–Signal Transistors, FETs and Diodes Device Data

EMBOSSED TAPE AND REEL

SOT-23, SC-59, SC-70/SOT-323, SC–90/SOT–416, SOT-223 and SO-16 packages are available only in

Tape and Reel. Use the appropriate suffix indicated below to order any of the SOT-23, SC-59,

SC-70/SOT-323, SOT-223 and SO-16 packages. (See Section 6 on Packaging for additional information).

SOT-23:

SC-59:

SC-70/

available in 8 mm Tape and Reel

Use the device title (which already includes the “T1” suffix) to order the 7 inch/3000 unit reel.

Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/10,000 unit reel.

available in 8 mm Tape and Reel

Use the device title (which already includes the “T1” suffix) to order the 7 inch/3000 unit reel.

Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/10,000 unit reel.

available in 8 mm Tape and Reel

SOT-323: Use the device title (which already includes the “T1” suffix) to order the 7 inch/3000 unit reel.

Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/10,000 unit reel.

SOT-223: available in 12 mm Tape and Reel

Use the device title (which already includes the “T1” suffix) to order the 7 inch/1000 unit reel.

Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/4000 unit reel.

SO-16:

available in 16 mm Tape and Reel

Add an “R1” suffix to the device title to order the 7 inch/500 unit reel.

Add an “R2” suffix to the device title to order the 13 inch/2500 unit reel.

RADIAL TAPE IN FAN FOLD BOX OR REEL

TO-92 packages are available in both bulk shipments and in Radial Tape in Fan Fold Boxes or Reels.

Fan Fold Boxes and Radial Tape Reel are the best methods for capturing devices for automatic insertion in

printed circuit boards.

TO-92:

available in Fan Fold Box

Add an “RLR” suffix and the appropriate Style code* to the device title to order the Fan Fold box.

available in 365 mm Radial Tape Reel

Add an “RLR” suffix and the appropriate Style code* to the device title to order the Radial Tape

Reel.

*Refer to Section 6 on Packaging for Style code characters and additional information on ordering

*requirements.

DEVICE MARKINGS/DATE CODE CHARACTERS

SOT-23, SC-59, SC-70/SOT-323, and the SC–90/SOT–416 packages have a device marking and a date

code etched on the device. The generic example below depicts both the device marking and a representa-

tion of the date code that appears on the SC-70/SOT-323, SC-59 and SOT-23 packages.

D

ABC

The “D” represents a smaller alpha digit Date Code. The Date Code indicates the actual month in which the

part was manufactured.

2–2

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Tape and Reel Specifications

and Packaging Specifications

Embossed Tape and Reel is used to facilitate automatic pick and place equipment feed requirements. The tape is used as the

shipping container for various products and requires a minimum of handling. The antistatic/conductive tape provides a secure

cavity for the product when sealed with the “peel–back” cover tape.

• Two Reel Sizes Available (7″ and 13″)

• Used for Automatic Pick and Place Feed Systems

• Minimizes Product Handling

• SOD–123, SC–59, SC–70/SOT–323, SC–70ML/SOT–363,

SOT–23, TSOP–6, in 8 mm Tape

• SOT–223 in 12 mm Tape

• EIA 481, –1, –2

• SO–14, SO–16 in 16 mm Tape

Usethestandarddevicetitleandaddtherequiredsuffixaslistedintheoptiontableonthefollowingpage. Notethattheindividual

reels have a finite number of devices depending on the type of product contained in the tape. Also note the minimum lot size is

one full reel for each line item, and orders are required to be in increments of the single reel quantity.

SC–70ML/SOT–363, TSOP–6

T1 ORIENTATION

SC–59, SC–70/SOT–323, SOT–23

SOD–123

8 mm

SC–70ML/SOT–363

SOT–223

SO–14, 16

DIRECTION

OF FEED

T2 ORIENTATION

12 mm

16 mm

8 mm

EMBOSSED TAPE AND REEL ORDERING INFORMATION

Devices Per Reel

and Minimum

Order Quantity

Tape Width

(mm)

Pitch

(inch)

Reel Size

mm (inch)

Device

Suffix

mm

Package

SC–59

8

4.0 ± 0.1 (.157 ± .004)

178

(7)

3,000

T1

SC–70/SOT–323

8

178

330

(7)

(13)

3,000

10,000

T1

T3

SO–14

SO–16

16

8.0 ± 0.1 (.315 ± .004)

4.0 ± 0.1 (.157 ± .004)

8.0 ± 0.1 (.315 ± .004)

4.0 ± 0.1 (.157 ± .004)

178

330

(7)

(13)

500

2,500

R1

R2

16

178

330

(7)

(13)

500

2,500

R1

R2

SOD–123

8

178

330

(7)

(13)

3,000

10,000

T1

T3

SOT–23

8

178

330

(7)

(13)

3,000

10,000

T1

T3

SOT–223

12

178

330

(7)

(13)

1,000

4,000

T1

T3

SC–70ML/SOT–363

TSOP–6

8

178

(7)

3,000

T1

T2

8

178

(7)

3,000

T1

Tape and Reel Specifications

6–2

Motorola Small–Signal Transistors, FETs and Diodes Device Data

EMBOSSED TAPE AND REEL DATA FOR DISCRETES

CARRIER TAPE SPECIFICATIONS

10 Pitches Cumulative Tolerance on Tape

P

0

± 0.2 mm

(± 0.008″)

K

t

P

2

D

E

F

Top Cover

Tape

A

0

W

K

0

B

0

B

1

See

Note 1

P

D

1

Center Lines

of Cavity

Embossment

For Components

2.0 mm x 1.2 mm and Larger

For Machine Reference Only

Including Draft and RADII

User Direction of Feed

Concentric Around B

0

* Top Cover Tape

Thickness (t )

0.10 mm

1

Bar Code Label

R Min

(.004″) Max.

Tape and Components

Shall Pass Around Radius “R”

Without Damage

Bending Radius

Embossed Carrier

100 mm

(3.937″)

Embossment

10°

Maximum Component Rotation

1 mm Max

Typical Component

Cavity Center Line

Tape

1 mm

(.039″) Max

250 mm

(9.843″)

Typical Component

Center Line

Camber (Top View)

Allowable Camber To Be 1 mm/100 mm Nonaccumulative Over 250 mm

DIMENSIONS

Tape

Size

B

Max

D

E

F

K

P

2

R Min

T Max

W Max

1

0

8 mm

4.55 mm

(.179″)

1.0 Min

(.039″)

3.5±0.05 mm

(.138±.002″)

2.4 mm Max

(.094″)

25 mm

(.98″)

8.3 mm

(.327″)

1.5+0.1 mm

–0.0

1.75±0.1 mm

(.069±.004″)

4.0±0.1 mm

(.157±.004″)

2.0±0.1 mm

(.079±.002″)

0.6 mm

(.024″)

(.059+.004″

–0.0)

12 mm

16 mm

24 mm

8.2 mm

(.323″)

5.5±0.05 mm

(.217±.002″)

6.4 mm Max

(.252″)

12±.30 mm

(.470±.012″)

1.5 mm Min

(.060″)

30 mm

(1.18″)

12.1 mm

(.476″)

7.5±0.10 mm

(.295±.004″)

7.9 mm Max

(.311″)

16.3 mm

(.642″)

20.1 mm

(.791″)

11.5±0.1 mm

(.453±.004″)

11.9 mm Max

(.468″)

24.3 mm

(.957″)

Metric dimensions govern — English are in parentheses for reference only.

NOTE 1: A , B , and K are determined by component size. The clearance between the components and the cavity must be within .05 mm min. to .50 mm max.,

0

NOTE 1: the component cannot rotate more than 10° within the determined cavity.

NOTE 2: If B exceeds 4.2 mm (.165) for 8 mm embossed tape, the tape may not feed through all tape feeders.

1

NOTE 3: Pitch information is contained in the Embossed Tape and Reel Ordering Information on pg. 5.12–3.

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Tape and Reel Specifications

6–3

EMBOSSED TAPE AND REEL DATA FOR DISCRETES

T Max

Outside Dimension

Measured at Edge

1.5 mm Min

(.06″)

13.0 mm ± 0.5 mm

(.512″ ± .002″)

A

20.2 mm Min

(.795″)

50 mm Min

(1.969″)

Full Radius

Inside Dimension

G

Measured Near Hub

Size

A Max

G

T Max

8 mm

330 mm

8.4 mm + 1.5 mm, –0.0

14.4 mm

(12.992″)

(.33″ + .059″, –0.00)

(.56″)

12 mm

16 mm

24 mm

330 mm

(12.992″)

12.4 mm + 2.0 mm, –0.0

(.49″ + .079″, –0.00)

18.4 mm

(.72″)

360 mm

(14.173″)

16.4 mm + 2.0 mm, –0.0

(.646″ + .078″, –0.00)

22.4 mm

(.882″)

360 mm

24.4 mm + 2.0 mm, –0.0

30.4 mm

(14.173″)

(.961″ + .070″, –0.00)

(1.197″)

Reel Dimensions

Metric Dimensions Govern — English are in parentheses for reference only

Tape and Reel Specifications

6–4

Motorola Small–Signal Transistors, FETs and Diodes Device Data

TO–92 EIA, IEC, EIAJ

Radial Tape in Fan Fold

Box or On Reel

TO–92

RADIAL

TAPE IN

FAN FOLD

BOX OR

ON REEL

Radial tape in fan fold box or on reel of the reliable TO–92 package are

the best methods of capturing devices for automatic insertion in printed

circuit boards. These methods of taping are compatible with various

equipment for active and passive component insertion.

• Available in Fan Fold Box

• Available on 365 mm Reels

• Accommodates All Standard Inserters

• Allows Flexible Circuit Board Layout

• 2.5 mm Pin Spacing for Soldering

• EIA–468, IEC 286–2, EIAJ RC1008B

Ordering Notes:

When ordering radial tape in fan fold box or on reel, specify the style per

Figures 3 through 8. Add the suffix “RLR” and “Style” to the device title, i.e.

MPS3904RLRA. This will be a standard MPS3904 radial taped and

supplied on a reel per Figure 9.

Fan Fold Box Information — Order in increments of 2000.

Reel Information — Order in increments of 2000.

US/European Suffix Conversions

US

EUROPE

RL

RLRA

RLRE

RLRM

RL1

ZL1

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Packaging Specifications

6–5

TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL

H2A

H2B

H

W2

H4

H5

T1

L1

H1

W1

W

L

T

T2

F1

F2

D

P2

P1

P2

P

Figure 1. Device Positioning on Tape

Specification

Millimeter

Inches

Symbol

D

Item

Min

Max

Min

Max

0.1496

0.015

0.0945

.059

0.1653

3.8

4.2

Tape Feedhole Diameter

D2

F1, F2

H

0.020

0.110

.156

0.38

2.4

1.5

8.5

0

0.51

2.8

Component Lead Thickness Dimension

Component Lead Pitch

4.0

Bottom of Component to Seating Plane

Feedhole Location

H1

H2A

H2B

H4

H5

L

0.3346

0

0.3741

0.039

0.051

0.768

0.649

0.433

—

9.5

1.0

Deflection Left or Right

0

1.0

Deflection Front or Rear

0.7086

0.610

0.3346

0.09842

0.4921

0.2342

0.1397

0.06

18

19.5

16.5

11

Feedhole to Bottom of Component

Feedhole to Seating Plane

Defective Unit Clipped Dimension

Lead Wire Enclosure

15.5

8.5

2.5

12.5

5.95

3.55

0.15

—

L1

—

P

0.5079

0.2658

0.1556

0.08

12.9

6.75

3.95

0.20

1.44

0.65

19

Feedhole Pitch

P1

Feedhole Center to Center Lead

First Lead Spacing Dimension

Adhesive Tape Thickness

Overall Taped Package Thickness

Carrier Strip Thickness

P2

T

T1

—

0.0567

0.027

0.7481

0.2841

0.01968

T2

0.014

0.6889

0.2165

.0059

0.35

17.5

5.5

.15

W

Carrier Strip Width

W1

W2

6.3

Adhesive Tape Width

0.5

Adhesive Tape Position

NOTES:

1. Maximum alignment deviation between leads not to be greater than 0.2 mm.

2. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 11 mm.

3. Component lead to tape adhesion must meet the pull test requirements established in Figures 5, 6 and 7.

4. Maximum non–cumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches.

5. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive.

6. No more than 1 consecutive missing component is permitted.

7. A tape trailer and leader, having at least three feed holes is required before the first and after the last component.

8. Splices will not interfere with the sprocket feed holes.

Packaging Specifications

6–6

Motorola Small–Signal Transistors, FETs and Diodes Device Data

TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL

FAN FOLD BOX STYLES

ADHESIVE TAPE ON

TOP SIDE

ADHESIVE TAPE ON

TOP SIDE

330 mm

13”

MAX

FLAT SIDE

ROUNDED SIDE

CARRIER

STRIP

CARRIER

STRIP

252 mm

9.92”

MAX

FLAT SIDE OF TRANSISTOR

AND ADHESIVE TAPE VISIBLE.

ROUNDED SIDE OF TRANSISTOR AND

ADHESIVE TAPE VISIBLE.

58 mm

2.28”

MAX

Style M fan fold box is equivalent to styles E and F of

reel pack dependent on feed orientation from box.

Style P fan fold box is equivalent to styles A and B of

reel pack dependent on feed orientation from box.

Figure 2. Style M

Figure 3. Style P

Figure 4. Fan Fold Box Dimensions

ADHESION PULL TESTS

500 GRAM PULL FORCE

70 GRAM

PULL FORCE

100 GRAM

PULL FORCE

16 mm

HOLDING

FIXTURE

HOLDING

FIXTURE

HOLDING

FIXTURE

There shall be no deviation in the leads and

no component leads shall be pulled free of

the tape with a 500 gram load applied to the

component body for 3 ± 1 second.

The component shall not pull free with a 300 gram

load applied to the leads for 3 ± 1 second.

The component shall not pull free with a 70 gram

load applied to the leads for 3 ± 1 second.

Figure 5. Test #1

Figure 6. Test #2

Figure 7. Test #3

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Packaging Specifications

6–7

TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL

REEL STYLES

CORE DIA.

82mm ± 1mm

ARBOR HOLE DIA.

30.5mm ± 0.25mm

MARKING NOTE

HUB RECESS

76.2mm ± 1mm

RECESS DEPTH

9.5mm MIN

365mm + 3, – 0mm

38.1mm ± 1mm

48 mm

MAX

Material used must not cause deterioration of components or degrade lead solderability

Figure 8. Reel Specifications

ADHESIVE TAPE ON REVERSE SIDE

CARRIER STRIP

ROUNDED

CARRIER STRIP

FLAT SIDE

SIDE

ADHESIVE TAPE

FEED

Rounded side of transistor and adhesive tape visible.

Flat side of transistor and carrier strip visible

(adhesive tape on reverse side).

Figure 9. Style A

Figure 10. Style B

ADHESIVE TAPE ON REVERSE SIDE

CARRIER STRIP

ROUNDED

SIDE

CARRIER STRIP

FLAT SIDE

ADHESIVE TAPE

FEED

Flat side of transistor and adhesive tape visible.

Rounded side of transistor and carrier strip visible

(adhesive tape on reverse side).

Figure 11. Style E

Figure 12. Style F

Packaging Specifications

6–8

Motorola Small–Signal Transistors, FETs and Diodes Device Data

INFORMATION FOR USING SURFACE MOUNT PACKAGES

RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total

design. The footprint for the semiconductor packages must

be the correct size to ensure proper solder connection inter-

face between the board and the package. With the correct

pad geometry, the packages will self align when subjected to

a solder reflow process.

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a func-

tion of the drain/collector pad size. These can vary from the

minimum pad size for soldering to a pad size given for

maximum power dissipation. Power dissipation for a surface

Although the power dissipation can almost be doubled with

this method, area is taken up on the printed circuit board

which can defeat the purpose of using surface mount

technology. For example, a graph of R

area is shown in Figure 1.

versus drain pad

θJA

mount device is determined by T

junction temperature of the die, R

, the maximum rated

, the thermal resistance

J(max)

θJA

from the device junction to ambient, and the operating

temperature, T . Using the values provided on the data

Another alternative would be to use a ceramic substrate or

an aluminum core board such as Thermal Clad . Using a

board material such as Thermal Clad, an aluminum core

board, the power dissipation can be doubled using the same

footprint.

A

sheet, P can be calculated as follows:

D

T

– T

A

θJA

J(max)

P

=

D

R

160

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values into

Board Material = 0.0625″

G–10/FR–4, 2 oz Copper

T = 25°C

A

140

120

the equation for an ambient temperature T of 25°C, one can

A

calculate the power dissipation of the device. For example,

0.8 Watts

for a SOT–223 device, P is calculated as follows.

D

150°C – 25°C

156°C/W

1.5 Watts

= 800 milliwatts

P

=

1.25 Watts*

D

100

80

The 156°C/W for the SOT–223 package assumes the use

of the recommended footprint on a glass epoxy printed circuit

board to achieve a power dissipation of 800 milliwatts. There

are other alternatives to achieving higher power dissipation

from the surface mount packages. One is to increase the

area of the drain/collector pad. By increasing the area of the

drain/collector pad, the power dissipation can be increased.

*Mounted on the DPAK footprint

0.2 0.4

0.0

0.6

A, AREA (SQUARE INCHES)

0.8

1.0

Figure 1. Thermal Resistance versus Drain Pad

Area for the SOT–223 Package (Typical)

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed

circuit board, solder paste must be applied to the pads.

Solder stencils are used to screen the optimum amount.

These stencils are typically 0.008 inches thick and may be

made of brass or stainless steel. For packages such as the

SOT–23, SC–59, SC–70/SOT–323, SC–90/SOT–416,

SOD–123, SOT–223, SOT–363, SO–14, SO–16, and

TSOP–6 packages, the stencil opening should be the same

as the pad size or a 1:1 registration.

Surface Mount Information

7–10

Motorola Small–Signal Transistors, FETs and Diodes Device Data

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated

to a high temperature, failure to complete soldering within a

short time could result in device failure. Therefore, the

following items should always be observed in order to mini-

mize the thermal stress to which the devices are subjected.

• Always preheat the device.

• The soldering temperature and time should not exceed

260°C for more than 10 seconds.

• When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.

Gradual cooling should be used since the use of forced

cooling will increase the temperature gradient and will

result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied during

cooling.

• The delta temperature between the preheat and soldering

should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering method,

the difference should be a maximum of 10°C.

* Soldering a device without preheating can cause excessive

thermal shock and stress which can result in damage to the

device.

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control

settings that will give the desired heat pattern. The operator

must set temperatures for several heating zones and a figure

for belt speed. Taken together, these control settings make

up a heating “profile” for that particular circuit board. On

machines controlled by a computer, the computer remem-

bers these profiles from one operating session to the next.

Figure 2 shows a typical heating profile for use when

soldering a surface mount device to a printed circuit board.

This profile will vary among soldering systems, but it is a

good starting point. Factors that can affect the profile include

the type of soldering system in use, density and types of

components on the board, type of solder used, and the type

of board or substrate material being used. This profile shows

temperature versus time. The line on the graph shows the

actual temperature that might be experienced on the surface

of a test board at or near a central solder joint. The two

profiles are based on a high density and a low density board.

The Vitronics SMD310 convection/infrared reflow soldering

system was used to generate this profile. The type of solder

used was 62/36/2 Tin Lead Silver with a melting point

between 177–189°C. When this type of furnace is used for

solder reflow work, the circuit boards and solder joints tend to

heat first. The components on the board are then heated by

conduction. The circuit board, because it has a large surface

area, absorbs the thermal energy more efficiently, then

distributes this energy to the components. Because of this

effect, the main body of a component may be up to 30

degrees cooler than the adjacent solder joints.

STEP 5

STEP 6

VENT

STEP 7

COOLING

STEP 1

STEP 4

STEP 2

VENT

“SOAK”

STEP 3

HEATING

ZONES 4 & 7

“SPIKE”

PREHEAT

ZONE 1

“RAMP”

HEATING

ZONES 3 & 6

“SOAK”

HEATING

ZONES 2 & 5

“RAMP”

205° TO 219°C

PEAK AT

SOLDER JOINT

200°C

170°C

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

160°C

150°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

100°C

140°C

MASS OF ASSEMBLY)

100°C

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

50°C

TIME (3 TO 7 MINUTES TOTAL)

T

MAX

Figure 2. Typical Solder Heating Profile

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Surface Mount Information

7–11

Footprints for Soldering

0.037

0.95

0.037

0.95

0.037

0.95

0.037

0.95

0.094

2.4

0.079

2.0

0.039

1.0

0.035

0.9

inches

mm

0.031

0.8

inches

0.031

0.8

mm

SC–59

SOT–23

0.025

0.65

0.025

0.65

0.5 min. (3x)

0.075

1.9

0.035

0.9

0.028

0.7

1.4

inches

mm

SC–70/SOT–323

SOT 416/SC–90

0.15

3.8

0.060

1.52

0.079

2.0

0.275

7.0

0.155

4.0

0.248

6.3

0.091

2.3

0.091

2.3

0.079

2.0

0.024

0.6

0.050

1.270

inches

mm

0.059

1.5

0.059

1.5

0.059

1.5

inches

mm

SOT–223

SO–14, SO–16

Surface Mount Information

7–12

Motorola Small–Signal Transistors, FETs and Diodes Device Data

0.5 mm (min)

0.91

0.036

1.22

0.048

2.36

0.093

4.19

mm

inches

0.165

1.9 mm

SOD–123

SOT–363

(SC–70 6 LEAD)

0.094

2.4

0.037

0.95

0.074

1.9

0.037

0.95

0.028

0.7

0.039

1.0

inches

mm

TSOP–6

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Surface Mount Information

7–13

Package Outline Dimensions

Dimensions are in inches unless otherwise noted.

NOTES:

A

B

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND DIMENSION R

IS UNCONTROLLED.

R

4. DIMENSION F APPLIES BETWEEN P AND L.

DIMENSION D AND J APPLY BETWEEN L AND K

MINIMUM. LEAD DIMENSION IS UNCONTROLLED

IN P AND BEYOND DIMENSION K MINIMUM.

P

L

F

SEATING

PLANE

K

INCHES

DIM MIN MAX

MILLIMETERS

MIN

4.45

4.32

3.18

0.41

1.15

2.42

0.39

MAX

5.20

5.33

4.19

0.55

0.48

1.39

2.66

0.50

–––

A

B

C

D

F

G

H

J

K

L

N

P

0.175

0.170

0.125

0.016

0.045

0.095

0.015

0.500

0.250

0.080

–––

0.205

0.210

0.165

0.022

0.019

0.055

0.105

0.020

D

X X

G

H

J

V

C

––– 12.70

SECTION X–X

–––

0.105

0.100

–––

6.35

2.04

–––

2.93

3.43

–––

1

2.66

2.54

–––

N

R

V

0.115

0.135

–––

STYLE 2:

STYLE 1:

PIN 1. EMITTER

STYLE 3:

STYLE 4:

PIN 1. CATHODE

STYLE 5:

PIN 1. DRAIN

STYLE 7:

PIN 1. SOURCE

PIN 1. BASE

2. EMITTER

3. COLLECTOR

PIN 1. ANODE

2. ANODE

3. CATHODE

2. BASE

3. COLLECTOR

2. CATHODE

3. ANODE

2. SOURCE

3. GATE

2. DRAIN

3. GATE

STYLE 14:

STYLE 15:

STYLE 17:

STYLE 21:

STYLE 22:

STYLE 30:

PIN 1. EMITTER

2. COLLECTOR

3. BASE

PIN 1. ANODE 1

2. CATHODE

3. ANODE 2

PIN 1. COLLECTOR

2. BASE

3. EMITTER

PIN 1. COLLECTOR

2. EMITTER

3. BASE

PIN 1. SOURCE

2. GATE

3. DRAIN

PIN 1. DRAIN

2. GATE

3. SOURCE

CASE 029–04

(TO–226AA) TO–92

PLASTIC

A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND DIMENSION R

IS UNCONTROLLED.

4. DIMENSION F APPLIES BETWEEN P AND L.

DIMENSIONS D AND J APPLY BETWEEN L AND K

MIMIMUM. LEAD DIMENSION IS UNCONTROLLED

IN P AND BEYOND DIMENSION K MINIMUM.

B

R

SEATING

PLANE

P

L

F

K

INCHES

DIM MIN MAX

MILLIMETERS

MIN

4.44

7.37

3.18

0.46

0.41

1.15

2.42

0.46

MAX

5.21

7.87

4.19

0.56

0.48

1.39

2.66

0.61

–––

A

B

C

D

F

G

H

J

K

L

N

P

R

V

0.175

0.290

0.125

0.018

0.016

0.045

0.095

0.018

0.500

0.250

0.080

–––

0.205

0.310

0.165

0.022

0.019

0.055

0.105

0.024

X X

G

D

H

J

V

––– 12.70

–––

0.105

0.100

–––

6.35

2.04

–––

3.43

–––

SECTION X–X

2.66

2.54

–––

C

1

2

3

N

0.135

N

–––

STYLE 1:

PIN 1. EMITTER

STYLE 14:

PIN 1. EMITTER

STYLE 22:

PIN 1. SOURCE

2. BASE

3. COLLECTOR

2. COLLECTOR

3. BASE

2. GATE

3. DRAIN

CASE 029–05

(TO–226AE) TO–92

1–WATT PLASTIC

Package Outline Dimensions

8–2

Motorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

B

NOTES:

1. PACKAGE CONTOUR OPTIONAL WITHIN DIA B

AND LENGTH A. HEAT SLUGS, IF ANY, SHALL BE

INCLUDED WITHIN THIS CYLINDER, BUT SHALL

NOT BE SUBJECT TO THE MIN LIMIT OF DIA B.

2. LEAD DIA NOT CONTROLLED IN ZONES F, TO

ALLOW FOR FLASH, LEAD FINISH BUILDUP,

AND MINOR IRREGULARITIES OTHER THAN

HEAT SLUGS.

D

K

F

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

A

B

D

F

5.84

2.16

0.46

–––

7.62 0.230 0.300

2.72 0.085 0.107

0.56 0.018 0.022

F

1.27

––– 0.050

K

25.40 38.10 1.000 1.500

K

All JEDEC dimensions and notes apply.

CASE 51–02

(DO–204AA)

DO–7

A

B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND ZONE R IS

UNCONTROLLED.

4. DIMENSION F APPLIES BETWEEN P AND L.

DIMENSIONS D AND J APPLY BETWEEN L AND K

MINIMUM. LEAD DIMENSION IS UNCONTROLLED

IN P AND BEYOND DIM K MINIMUM.

R

SEATING

PLANE

D

L

P

F

J

K

INCHES

DIM MIN MAX

MILLIMETERS

MIN

4.45

4.32

3.18

0.41

MAX

5.21

5.33

4.49

0.56

0.482

A

B

C

D

F

0.175

0.170

0.125

0.016

0.205

0.210

0.165

0.022

SECTION X–X

X X

D

G

H

0.019 0.407

G

H

J

K

L

N

P

0.050 BSC

0.100 BSC

0.014 0.016

––– 12.70

1.27 BSC

3.54 BSC

0.36

0.41

–––

2.66

1.27

–––

0.500

0.250

0.080

–––

V

–––

0.105

0.050

–––

6.35

2.03

–––

2.93

3.43

C

R

V

0.115

0.135

–––

1

2

N

STYLE 1:

PIN 1. ANODE

2. CATHODE

CASE 182–02

(T0–226AC) TO–92

PLASTIC

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Package Outline Dimensions

8–3

PACKAGE OUTLINE DIMENSIONS (continued)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIUMUM LEAD THICKNESS INCLUDES

LEAD FINISH THICKNESS. MINIMUM LEAD

THICKNESS IS THE MINIMUM THICKNESS OF

BASE MATERIAL.

A

L

3

INCHES

DIM MIN MAX

MILLIMETERS

S

C

B

MIN

2.80

1.20

0.89

0.37

1.78

MAX

3.04

1.40

1.11

0.50

2.04

1

2

A

B

C

D

G

H

J

0.1102 0.1197

0.0472 0.0551

0.0350 0.0440

0.0150 0.0200

0.0701 0.0807

V

G

0.0005 0.0040 0.013 0.100

0.0034 0.0070 0.085 0.177

K

L

S

0.0140 0.0285

0.0350 0.0401

0.0830 0.1039

0.0177 0.0236

0.35

0.89

2.10

0.45

0.69

1.02

2.64

0.60

H

J

D

V

K

STYLE 10:

STYLE 11:

PIN 1. ANODE

STYLE 6:

PIN 1. BASE

2. EMITTER

STYLE 8:

STYLE 9:

PIN 1. ANODE

PIN 1. DRAIN

2. SOURCE

3. GATE

PIN 1. ANODE

2. NO CONNECTION

3. CATHODE

2. CATHODE

3. CATHODE–ANODE

2. ANODE

3. CATHODE

3. COLLECTOR

STYLE 12:

STYLE 18:

PIN 1. NO CONNECTION

STYLE 19:

PIN 1. CATHODE

STYLE 21:

PIN 1. GATE

2. SOURCE

3. DRAIN

PIN 1. CATHODE

2. CATHODE

3. ANODE

2. CATHODE

3. ANODE

2. ANODE

3. CATHODE–ANODE

CASE 318–08

(TO–236AB) SOT–23

PLASTIC

A

L

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

3

S

B

A

B

C

D

G

H

J

2.70

1.30

1.00

0.35

1.70

0.013

0.09

0.20

1.25

2.50

3.10 0.1063 0.1220

1.70 0.0512 0.0669

1.30 0.0394 0.0511

0.50 0.0138 0.0196

2.10 0.0670 0.0826

0.100 0.0005 0.0040

0.18 0.0034 0.0070

0.60 0.0079 0.0236

1.65 0.0493 0.0649

3.00 0.0985 0.1181

2

1

D

G

K

L

S

J

C

K

H

STYLE 4:

PIN 1. N.C.

STYLE 5:

STYLE 1:

PIN 1. EMITTER

2. BASE

STYLE 2:

PIN 1. N.C.

2. ANODE

3. CATHODE

STYLE 3:

PIN 1. ANODE

PIN 1. CATHODE

2. CATHODE

3. ANODE

2. CATHODE

3. ANODE

2. ANODE

3. CATHODE

3. COLLECTOR

CASE 318D–04

SC–59

Package Outline Dimensions

8–4

Motorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

A

F

NOTES:

3. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

4. CONTROLLING DIMENSION: INCH.

4

INCHES

DIM MIN MAX

MILLIMETERS

S

B

MIN

6.30

3.30

1.50

0.60

2.90

2.20

MAX

6.70

3.70

1.75

0.89

3.20

2.40

0.100

0.35

2.00

1.05

10

1

2

3

A

B

C

D

F

G

H

J

K

L

M

S

0.249

0.130

0.060

0.024

0.115

0.087

0.263

0.145

0.068

0.035

0.126

0.094

D

L

0.0008 0.0040 0.020

G

0.009

0.060

0.033

0

0.014

0.078

0.041

10

0.24

1.50

0.85

0

J

C

0.08 (0003)

0.264

0.287

6.70

7.30

M

H

K

STYLE 1:

PIN 1. BASE

STYLE 2:

PIN 1. ANODE

STYLE 3:

PIN 1. GATE

2. DRAIN

2. COLLECTOR

3. EMITTER

4. COLLECTOR

2. CATHODE

3. NC

4. CATHODE

3. SOURCE

4. DRAIN

CASE 318E–04

SOT–223

A

NOTES:

L

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD THICKNESS

IS THE MINIMUM THICKNESS OF BASE

MATERIAL.

6

5

2

4

B

S

1

3

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

D

A

B

C

D

G

H

J

K

L

M

S

2.90

1.30

0.90

0.25

0.85

0.013

0.10

0.20

1.25

0

3.10 0.1142 0.1220

1.70 0.0512 0.0669

1.10 0.0354 0.0433

0.50 0.0098 0.0197

1.05 0.0335 0.0413

0.100 0.0005 0.0040

0.26 0.0040 0.0102

0.60 0.0079 0.0236

1.55 0.0493 0.0610

G

M

J

C

0.05 (0.002)

K

10

0

10

H

2.50

3.00 0.0985 0.1181

STYLE 1:

PIN 1. DRAIN

2. DRAIN

3. GATE

4. SOURCE

5. DRAIN

6. DRAIN

CASE 318G–02

TSOP–6

PLASTIC

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Package Outline Dimensions

8–5

PACKAGE OUTLINE DIMENSIONS (continued)

A

L

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

3

2. CONTROLLING DIMENSION: INCH.

B

S

INCHES

DIM MIN MAX

MILLIMETERS

1

2

MIN

1.80

1.15

0.90

0.30

1.20

0.00

0.10

0.425 REF

0.650 BSC

0.700 REF

0.80

2.00

0.30

MAX

2.20

1.35

1.25

0.40

1.40

0.10

0.25

A

B

C

D

G

H

J

K

L

N

R

S

0.071 0.087

0.045 0.053

0.035 0.049

0.012 0.016

0.047 0.055

0.000 0.004

0.004 0.010

0.017 REF

D

V

G

0.026 BSC

R

J

N

C

0.028 REF

0.031 0.039

0.079 0.087

0.012 0.016

1.00

2.20

0.40

0.05 (0.002)

V

K

H

STYLE 2:

PIN 1. ANODE

2. N.C.

STYLE 3:

PIN 1. BASE

2. EMITTER

STYLE 4:

STYLE 5:

PIN 1. ANODE

PIN 1. CATHODE

2. CATHODE

3. ANODE

2. ANODE

3. CATHODE

3. COLLECTOR

STYLE 7:

STYLE 9:

PIN 1. ANODE

STYLE 10:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

PIN 1. CATHODE

2. ANODE

3. ANODE–CATHODE

2. CATHODE

3. CATHODE–ANODE

CASE 419–02

SC–70/SOT–323

A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

G

V

INCHES

DIM MIN MAX

MILLIMETERS

MIN

1.80

1.15

0.80

0.10

MAX

2.20

1.35

1.10

0.30

A

B

C

D

G

H

J

K

N

S

0.071 0.087

0.045 0.053

0.031 0.043

0.004 0.012

0.026 BSC

6

5

4

3

S

–B–

0.65 BSC

1

2

–––

0.004

–––

0.10

0.25

0.30

0.004 0.010

0.004 0.012

0.008 REF

0.079 0.087

0.012 0.016

0.20 REF

2.00

0.30

2.20

0.40

M

0.2 (0.008)

B

D6 PL

V

STYLE 1:

PIN 1. EMITTER 2

N

2. BASE 2

3. COLLECTOR 1

4. EMITTER 1

5. BASE 1

J

6. COLLECTOR 2

C

STYLE 6:

PIN 1. ANODE 2

2. N/C

3. CATHODE 1

4. ANODE 1

5. N/C

K

H

6. CATHODE 2

CASE 419B-01

SOT–363

Package Outline Dimensions

8–6

Motorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

A

C

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

H

1

INCHES

DIM MIN MAX

MILLIMETERS

MIN

1.40

2.55

0.95

0.50

0.25

0.00

–––

MAX

1.80

2.85

1.35

0.70

–––

0.10

0.15

3.85

A

B

C

D

E

H

J

0.055

0.100

0.037

0.020

0.004

0.000

–––

0.071

0.112

0.053

0.028

–––

0.004

0.006

0.152

K

B

K

0.140

3.55

E

2

STYLE 1:

PIN 1. CATHODE

2. ANODE

J

D

CASE 425–04

SOD–123

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

–A–

S

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

2

A

B

C

D

G

H

J

K

L

S

0.70

1.40

0.60

0.15

0.80 0.028 0.031

1.80 0.055 0.071

0.90 0.024 0.035

0.30 0.006 0.012

3

G

–B–

1

D 3 PL

0.20 (0.008)

1.00 BSC

0.039 BSC

M

B

–––

0.10

1.45

0.10

––– 0.004

0.20 (0.008) A

0.25 0.004 0.010

1.75 0.057 0.069

0.20 0.004 0.008

K

0.50 BSC

0.020 BSC

STYLE 1:

J

PIN 1. BASE

2. EMITTER

3. COLLECTOR

C

STYLE 4:

L

H

PIN 1. CATHODE

2. CATHODE

3. ANODE

CASE 463–01

SOT–416/SC–90

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Package Outline Dimensions

8–7

PACKAGE OUTLINE DIMENSIONS (continued)

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

14

1

8

7

B

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

4. ROUNDED CORNERS OPTIONAL.

A

F

INCHES

DIM MIN MAX

0.770 18.16

MILLIMETERS

MIN

MAX

19.56

6.60

4.69

0.53

1.78

A

B

C

D

F

0.715

0.240

0.145

0.015

0.040

L

0.260

0.185

0.021

0.070

6.10

3.69

0.38

1.02

C

G

H

J

K

L

0.100 BSC

2.54 BSC

0.052

0.008

0.115

0.095

0.015

0.135

1.32

0.20

2.92

2.41

0.38

3.43

J

N

SEATING

PLANE

K

0.300 BSC

7.62 BSC

H

G

D

M

N

0

10

0.039

0

0.39

10

1.01

0.015

CASE 646–06

14–PIN DIP

PLASTIC

NOTES:

–A–

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

16

9

8

B

S

1

INCHES

DIM MIN MAX

0.740 0.770 18.80 19.55

MILLIMETERS

MIN MAX

F

A

B

C

D

F

C

L

0.250 0.270

0.145 0.175

0.015 0.021

6.35

3.69

0.39

1.02

6.85

4.44

0.53

1.77

0.040

0.70

SEATING

PLANE

–T–

G

H

J

K

L

M

S

0.100 BSC

0.050 BSC

0.008 0.015

2.54 BSC

1.27 BSC

K

M

0.21

0.38

3.30

7.74

10

H

J

0.110

0.295 0.305

10

0.020 0.040

0.130

2.80

7.50

0

G

D 16 PL

0

0.51

1.01

M

0.25 (0.010)

T A

CASE 648–08

16–PIN DIP

PLASTIC

Package Outline Dimensions

8–8

Motorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

–A–

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

14

1

8

7

–B–

P 7 PL

M

0.25 (0.010)

B

MILLIMETERS

DIM MIN MAX

INCHES

G

MIN

MAX

0.344

0.157

0.068

0.019

0.049

F

R X 45

C

A

B

C

D

F

8.55

3.80

1.35

0.35

0.40

8.75 0.337

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

–T–

SEATING

PLANE

J

M

G

J

K

M

P

1.27 BSC

0.050 BSC

K

D 14 PL

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

M

S

0.25 (0.010)

T B

A

7

0

5.80

0.25

6.20 0.228

0.50 0.010

0.244

0.019

R

CASE 751A–03

SO–14

PLASTIC

–A–

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

16

9

8

–B–

P 8 PL

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

M

S

0.25 (0.010)

B

1

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

G

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.393

0.157

0.068

0.019

0.049

F

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

10.00 0.386

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

R X 45

K

C

G

J

K

M

P

1.27 BSC

0.050 BSC

–T–

SEATING

PLANE

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

J

M

D

16 PL

7

0

5.80

0.25

6.20 0.229

0.50 0.010

0.244

0.019

M

S

0.25 (0.010)

T B

A

R

CASE 751B–05

SO–16

PLASTIC

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Package Outline Dimensions

8–9

where:

λ = failure rate

OUTGOING QUALITY

χ2 = chi–square function

The Average Outgoing Quality (AOQ) refers to the number

of devices per million that are outside the specification limits

at the time of shipment. Motorola has established Six Sigma

goals to improve its outgoing quality and will continue its ”error

free performance” focus to achieve its goal of zero parts per

million(PPM)outgoingquality. Motorola’spresentqualitylevel

has lead to vendor certification programs with many of its

customers. These programs ensure a level of quality which

allows the customer either to reduce or eliminate the need for

incoming inspections.

α = (100 – confidence level) / 100

d.f. = degrees of freedom = 2r + 2

r = number of failures

t = device hours

Chi–square values for 60% and 90% confidence intervals for

up to 12 failures are shown in Table 1–1.

Table 1–1 – Chi–Square Table

Chi–Square Distribution Function

60% Confidence Level

90% Confidence Level

AVERAGE OUTGOING QUALITY (AOQ)

CALCULATION

No. Fails

χ2 Quantity

No. Fails

χ2 Quantity

0

1

2

3

4

5

6

7

8

1.833

4.045

6.211

0

1

2

3

4

5

6

7

8

4.605

7.779

AOQ = (Process Average) (Probability of Acceptance)

6

10.645

13.362

15.987

18.549

21.064

23.542

25.989

28.412

30.813

33.196

35.563

(10 ) (PPM)

8.351

Total Projected Reject Devices

Process Average =

10.473

12.584

14.685

16.780

18.868

20.951

23.031

25.106

27.179

Total Number of Devices

Defects in Sample

Projected Reject Devices =

Lot Size

Sample Size

Total Number of Devices = Sum of units in each submitted lot

9

Number of Lots Rejected

Probability of Acceptance = 1 ±

10

11

12

10

11

12

Number of Lots Tested

6

10 = Conversion to parts per million (PPM)

The failure rate of semiconductor devices is inherently low.

As a result, the industry uses a technique called accelerated

testing to assess the reliability of semiconductors. During

accelerated tests, elevated stresses are used to produce, in

a short period, the same failure mechanisms as would be

observed under normal use conditions. The objective of this

testing is to identify these failure mechanisms and eliminate

them as a cause of failure during the useful life of the product.

Temperature, relative humidity, and voltage are the most

frequently used stresses during accelerated testing. Their

relationshiptofailurerateshasbeenshowntofollowanEyring

type of equation of the form:

RELIABILITY DATA ANALYSIS

Reliability is the probability that a semiconductor device will

perform its specified function in a given environment for a

specified period. In other words, reliability is quality over time

and environmental conditions. The most frequently used

reliability measure for semiconductor devices is the failure

rate ( λ ). The failure rate is obtained by dividing the number

of failures observed by the product of the number of devices

on test and the interval in hours, usually expressed as percent

per thousand hours or failures per billion device hours (FITS).

This is called a point estimate because it is obtained from

observations on a portion (sample) of the population of

devices.

To project from the sample to the population in general, one

must establish confidence intervals. The application of

confidence intervals is a statement of how ‘‘confident’’ one is

that the sample failure rate approximates that for the

population. To obtain failure rates at different confidence

levels, it is necessary to make use of specific probability

distributions. The chi–square (χ2) distribution that relates

observed and expected frequencies of an event is frequently

used to establish confidence intervals. The relationship

between failure rate and the chi–square distribution is as

follows:

λ = A exp(φkT) • exp(B/RH) • exp(CE)

Where A, B, C, φ, and k are constants, more specifically B,

C, and φ are numbers representing the apparent energy at

which various failure mechanisms occur. These are called

activation energies. ‘‘T’’ is the temperature, ‘‘RH’’ is the

relative humidity, and ‘‘E’’ is the electric field. The most familiar

form of this equation (shown on following page) deals with the

first exponential term that shows an Arrhenius type

relationship of the failure rate versus the junction temperature

of semiconductors. The junction temperature is related to the

ambient temperature through the thermal resistance and

power dissipation. Thus, we can test devices near their

maximum junction temperatures, analyze the failures to

assure that they are the types that are accelerated by

temperature and then by applying known acceleration factors,

estimate the failure rates for lower junction.

χ2 (α, d. f.)

The table on the following page shows observed activation

energies with references.

λ =

2t

Reliability and Quality Assurance

9–12

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Table 1–2 – Time Dependent Failure Mechanisms in Semiconductor Devices

(Applicable to Discrete and Integrated Circuits)

Typical

Device

Association

Relevant

Factors

Accelerating

Factors

Activation

Energy in eV

Process

Model

Reference

Silicon Oxide

Silicon–Silicon

Oxide Interface

Surface Charges

Inversion, Accumulation E/V, T

Mobile Ions

T, V

1.0

Fitch, et al.

Peck

1A

2

Oxide Pinholes

E/V, T

E, T

J, T

0.7–1.0 (Bipolar)

1.0 (Bipolar)

1984 WRS

Hokari, et al.

18

5

Dielectric Breakdown

(TDDB)

0.3–0.4 (MOS)

0.3 (MOS)

Domangue, et al.

Crook, D.L.

3

4

Charge Loss

0.8 (MOS)

EPROM

Gear, G.

11

6

Metallization

Electromigration

T, J

1.0 Large grain Al

(glassivated)

Nanda, et al.

Black, J.R.

Lycoudes, N.E.

Grain Size

Doping

0.5

7

Small grain Al

0.7 Cu–Al/Cu–Si–Al

(sputtered)

12

8

Corrosion

Chemical

Galvanic

Contamination H, E/V, T

0.6–0.7

(for electrolysis)

E/V may have

thresholds

Electrolytic

Bond and Other

Intermetallic

T, Impurities

T

1.0 (Au/Al)

Fitch, W.T

9

Mechanical Interfaces Growth

Bond Strength

Various Water Fab,

Assembly, and

Silicon Defects

Metal Scratches

Mask Defects, etc.

Silicon Defects

T, V

0.5–0.7 eV

0.5 eV

Howes, et al.

MMPD

10

13

V = voltage; E = electric field; T = temperature; J = current density; H = humidity

NO. REFERENCE

1A

1.0 eV activation for leakage type failures.

6

7

8

9

1.0 eV for large grain Al–Si (compared to line width).

Fitch, W.T.; Greer, P.; Lycoudes, N.; ‘‘Data to Support 0.001%/1000

Hours for Plastic I/C’s.’’ Case study on linear product shows 0.914 eV

activation energy which is within experimental error of 0.9 to 1.3 eV

activation energies for reversible leakage (inversion) failures reported

in the literature.

Nanda, Vangard, Gj–P; Black, J.R.; ‘‘Electromigration of Al–Si Alloy

Films’’, 1978 Reliability Physics Symposium.

0.5 eV Al, 0.7 eV Cu–Al small grain (compared to line width).

Black, J.R.; ‘‘Current Limitation of Thin Film Conductor’’ 1982 Reli-

ability Physics Symposium.

1B

0.7 To 1.0 eV for oxide defect failures for bipolar structures. This is

under investigation subsequent to information obtained from 1984

Wafer Reliability Symposium, especially for bipolar capacitors with

silicon nitride as dielectric.

0.65 eV for corrosion mechanism.

Lycoudes, N.E.; ‘‘The Reliability of Plastic Microcircuits in Moist

Environments’’, 1978 Solid State Technology.

2

3

4

1.0 eV activation for leakage type failures.

1.0 eV for open wires or high resistance bonds at the pad bond

due to Au–Al intermetallics.

Peck, D.S.; ‘‘New Concerns About Integrated Circuit Reliability’’ 1978

Reliability Physics Symposium.

Fitch, W.T.; ‘‘Operating Life vs Junction Temperatures for Plastic

Encapsulated I/C (1.5 mil Au wire)’’, unpublished report.

0.36 eV for dielectric breakdown for MOS gate structures.

Domangue, E.; Rivera, R.; Shedard, C.; ‘‘Reliability Prediction Using

Large MOS Capacitors’’, 1984 Reliability Physics Symposium.

10

11

0.7 eV for assembly related defects.

Howes, M.G.; Morgan, D.V.; ‘‘Reliability and Degradation, Semi-

conductor Devices and CIrcuits’’ John Wiley and Sons, 1981.

0.3 eV for dielectric breakdown.

Crook, D.L.; ‘‘Method of Determining Reliability Screens for Time

Dependent Dielectric Breakdown’’, 1979 Reliability Physics

Symposium.

Gear, G.; ‘‘FAMOUS PROM Reliability Studies’’, 1976 Reliability

Physics Symposium.

12

13

Black, J.R.: unpublished report.

5

1.0 eV for dielectric breakdown.

Hokari, Y.; et al.; IEDM Technical Digest, 1982.

Motorola Memory Products Division; unpublished report.

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Reliability and Quality Assurance

9–13

fixedpowerdissipation.)Bothsystemairflowandthepackage

mounting technique affect the θ thermal resistance term.

THERMAL RESISTANCE

CA

is essentially independent of air flow and external

Circuit performance and long–term circuit reliabiity are

affected by die temperature. Normally, both are improved by

keeping the junction temperatures low.

θ

JC

mounting method, but is sensitive to package material, die

bonding method, and die area.

Electrical power dissipated in any semiconductor device is

a source of heat. This heat source increases the temperature

of the die about some reference point, normally the ambient

temperature of 25°C in still air. The temperature increase,

then, depends on the amount of power dissipated in the circuit

and on the net thermal resistance between the heat source

and the reference point.

For applications where the case is held at essentially a fixed

temperature by mounting on a large or temperature controlled

heat sink, the estimated junction temperature is calculated by:

T = T + P (θ )

(3)

J

C

D

JC

where T = maximum case temperature and the other

C

parameters are as previously defined.

The temperature at the junction depends on the packaging

and mounting system’s ability to remove heat generated in the

circuit from the junction region to the ambient environment.

The basic formula for converting power dissipation to

estimated junction temperature is:

AIR FLOW

Air flow over the packages (due to a decrease in θ

)

JC

reduces the thermal resistance of the package, therefore

permitting a corresponding increase in power dissipation

without exceeding the maximum permissible operating

junction temperature.

T = T + P (θ

+ θ )

CA

(1)

J

A

D

JC

or

For thermal resistance values for specific packages, see

the Motorola Data Book or Design Manual for the appropriate

device family or contact your local Motorola sales office.

T = T + P (θ )

JA

(2)

J

A

D

where:

T

A

D

= maximum junction temperature

= maximum ambient temperature

= calculated maximum power dissipation, including

effects of external loads when applicable

J

P

ACTIVATION ENERGY

Determination of activation energies is accomplished by

testing randomly selected samples from the same population

at various stress levels and comparing failure rates due to the

same failure mechanism. The activation energy is

represented by the slope of the curve relating to the natural

logarithm of the failure rate to the various stress levels.

In calculating failure rates, the comprehensive method is to

use the specific activation energy for each failure mechanism

applicable to the technology and circuit under consideration.

A common alternative method is to use a single activation

energy value for the ‘‘expected’’ failure mechanism(s) with the

lowest activation energy.

θ

= average thermal resistance, junction to case

= average thermal resistance, case to ambient

= average thermal resistance, junction to ambient

JC

θ

CA

JA

This Motorola recommended formula has been approved

by RADC and DESC for calculating a ‘‘practical’’ maximum

operating junction temperature for MIL–M–38510 devices.

Only two terms on the right side of equation (1) can be

varied by the user, the ambient temperature and the device

case–to–ambient thermal resistance, θ . (To some extent

the device power dissipation can also be controlled, but under

recommended use the supply voltage and loading dictate a

CA

Reliability and Quality Assurance

9–14

Motorola Small–Signal Transistors, FETs and Diodes Device Data

RELIABILITY STRESS TESTS

The following are brief descriptions of the reliability tests

commonly used in the reliability monitoring program. Not all of

the tests listed are performed by each product division. Other

tests may be performed when appropriate.

HIGH TEMPERATURE REVERSE BIAS

(HTRB)

The purpose of this test is to align mobile ions by means of

temperature and voltage stress to form a high–current

leakage path between two or more junctions.

AUTOCLAVE (aka, PRESSURE COOKER)

Typical Test Conditions: T = 85°C to 150°C, Bias =

80% to 100% of Data Book max. rating, t = 120 to 1000

hours

Common Failure Modes: Parametric shifts in leakage

and gain

Common Failure Mechanisms: Ionic contamination on

the surface or under the metallization of the die

Military Reference: MIL–STD–750, Method 1039

A

Autoclave is an environmental test which measures device

resistance to moisture penetration and the resultant effect of

galvanic corrosion. Autoclave is a highly accelerated and

destructive test.

Typical Test Conditions: T = 121°C, rh = 100%, p = 1

A

atmosphere (15 psig), t = 24 to 96 hours

Common Failure Modes: Parametric shifts, high leak-

age and/or catastrophic

Common Failure Mechanisms: Die corrosion or con-

taminants such as foreign material on or within the pack-

age materials. Poor package sealing.

HIGH TEMPERATURE STORAGE LIFE

(HTSL)

HIGH HUMIDITY HIGH TEMPERATURE

BIAS (H3TB, H3TRB, or THB)

High temperature storage life testing is performed to

accelerate failure mechanisms which are thermally activated

through the application of extreme temperatures

This is an environmental test designed to measure the

moisture resistance of plastic encapsulated devices. A bias is

applied to create an electrolytic cell necessary to accelerate

corrosion of the die metallization. With time, this is a

catastrophically destructive test.

Typical Test Conditions: T = 70°C to 200°C, no bias, t

A

= 24 to 2500 hours

Common Failure Modes: Parametric shifts in leakage

and gain

Common Failure Mechanisms: Bulk die and diffusion

defects

Typical Test Conditions: T = 85°C to 95°C, rh = 85%

A

to 95%, Bias = 80% to 100% of Data Book max. rating, t

= 96 to 1750 hours

Military Reference: MIL–STD–750, Method 1032

Common Failure Modes: Parametric shifts, high leak-

age and/or catastrophic

Common Failure Mechanisms: Die corrosion or con-

taminants such as foreign material on or within the pack-

age materials. Poor package sealing.

INTERMITTENT OPERATING LIFE (IOL)

The purpose of this test is the same as SSOL in addition to

checking the integrity of both wire and die bonds by means of

thermal stressing

HIGH TEMPERATURE GATE BIAS (HTGB)

This test is designed to electrically stress the gate oxide under

a bias condition at high temperature.

Typical Test Conditions: T = 25°C, Pd = Data Book

A

maximum rating, T = T

on off

=

of 50°C to 100°C, t = 42

Typical Test Conditions: T = 150°C, Bias = 80% of

to 30000 cycles

A

Data Book max. rating, t = 120 to 1000 hours

Common Failure Modes: Parametric shifts in gate leak-

age and gate threshold voltage

Common Failure Mechanisms: Random oxide defects

and ionic contamination

Common Failure Modes: Parametric shifts and cata-

strophic

Common Failure Mechanisms: Foreign material, crack

and bulk die defects, metallization, wire and die bond

defects

Military Reference: MIL–STD–750, Method 1042

Military Reference: MIL–STD–750, Method 1037

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Reliability and Quality Assurance

9–15

MECHANICAL SHOCK

STEADY STATE OPERATING LIFE (SSOL)

The purpose of this test is to evaluate the bulk stability of the

die and to generate defects resulting from manufacturing

aberrations that are manifested as time and

stress–dependent failures.

This test is used to determine the ability of the device to

withstandasuddenchangeinmechanicalstressduetoabrupt

changes in motion as seen in handling, transportation, or

actual use.

Typical Test Conditions: T = 25°C, P = Data Book

maximum rating, t = 16 to 1000 hours

Common Failure Modes: Parametric shifts and cata-

strophic

Typical Test Conditions: Acceleration = 1500 g’s, Orienta-

A

D

tion = X , Y , Y plane, t = 0.5 msec, Blows = 5

1

2

Common Failure Modes: Open, short, excessive leak-

age, mechanical failure

Common Failure Mechanisms: Foreign material, crack

die, bulk die, metallization, wire and die bond defects

Military Reference: MIL–STD–750, Method 1026

Common Failure Mechanisms: Die and wire bonds,

cracked die, package defects

Military Reference: MIL–STD–750, Method 2015

TEMPERATURE CYCLING (AIR TO AIR)

MOISTURE RESISTANCE

The purpose of this test is to evaluate the ability of the device

to withstand both exposure to extreme temperatures and

transitions between temperature extremes. This testing will

also expose excessive thermal mismatch between materials.

The purpose of this test is to evaluate the moisture resistance

of components under temperature/humidity conditions typical

of tropical environments.

Typical Test Conditions: T = –10°C to 65°C, rh = 80%

A

Typical Test Conditions: T = –65°C to 200°C, cycle =

A

to 98%, t = 24 hours/cycles, cycle = 10

Common Failure Modes: Parametric shifts in leakage

and mechanical failure

10 to 4000

Common Failure Modes: Parametric shifts and cata-

strophic

Common Failure Mechanisms: Wire bond, cracked or

lifted die and package failure

Common Failure Mechanisms: Corrosion or contami-

nants on or within the package materials. Poor package

sealing

Military Reference: MIL–STD–750, Method 1051

Military Reference: MIL–STD–750, Method 1021

THERMAL SHOCK (LIQUID TO LIQUID)

SOLDERABILITY

The purpose of this test is to evaluate the ability of the device

to withstand both exposure to extreme temperatures and

sudden transitions between temperature extremes. This

testing will also expose excessive thermal mismatch between

materials.

The purpose of this test is to measure the ability of the device

leads/terminals to be soldered after an extended period of

storage (shelf life).

Typical Test Conditions: Steam aging = 8 hours, Flux =

R, Solder = Sn60, Sn63

Common Failure Modes: Pin holes, dewetting, nonwet-

ting

Common Failure Mechanisms: Poor plating, contami-

nated leads

Military Reference: MIL–STD–750, Method 2026

Typical Test Conditions: T = 0°C to 100°C, cycle = 20

A

to 300

Common Failure Modes: Parametric shifts and cata-

strophic

Common Failure Mechanisms: Wire bond, cracked or

lifted die and package failure

Military Reference: MIL–STD–750, Method 1056

SOLDER HEAT

VARIABLE FREQUENCY VIBRATION

This test is used to measure the ability of a device to withstand

the temperatures as may be seen in wave soldering

operations. Electrical testing is the endpoint critierion for this

stress.

This test is used to examine the ability of the device to

withstand deterioration due to mechanical resonance.

Typical Test Conditions: Peak acceleration = 20 g’s,

Frequency range = 20 Hz to KHz, t = 48 minutes

Common Failure Modes: Open, short, excessive leak-

age, mechanical failure

Typical Test Conditions: Solder Temperature = 260°C, t

= 10 seconds

Common Failure Modes: Parameter shifts, mechanical

failure

Common Failure Mechanisms: Poor package design

Military Reference: MIL–STD–750, Method 2031

Common Failure Mechanisms: Die and wire bonds,

cracked die, package defects

Military Reference: MIL–STD–750, Method 2056

Reliability and Quality Assurance

9–16

Motorola Small–Signal Transistors, FETs and Diodes Device Data

STATISTICAL PROCESS CONTROL

Communication Power & Signal Technologies Group

(CPSTG) is continually pursuing new ways to improveproduct

quality. Initial design improvement is one method that can be

used to produce a superior product. Equally important to

outgoing product quality is the ability to produce product that

consistently conforms to specification. Process variability is

the basic enemy of semiconductor manufacturing since it

leads to product variability. Used in all phases of Motorola’s

productmanufacturing, STATISTICAL PROCESS CONTROL

(SPC) replaces variability with predictability. The traditional

philosophy in the semiconductor industry has been

adherence to the data sheet specification. Using SPC

methods ensures that the product will meet specific process

requirements throughout the manufacturing cycle. The

emphasis is on defect prevention, not detection. Predictability

through SPC methods requires the manufacturing culture to

focus on constant and permanent improvements. Usually,

these improvements cannot be bought with state–of–the–art

equipment or automated factories. With quality in design,

process, and material selection, coupled with manufacturing

predictability, Motorola can produce world class products.

The immediate effect of SPC manufacturing is predictability

through process controls. Product centered and distributed

well within the product specification benefits Motorola with

fewer rejects, improved yields, and lower cost. The direct

benefit to Motorola’s customers includes better incoming

quality levels, less inspection time, and ship–to–stock

capability. Circuit performance is often dependent on the

cumulative effect of component variability. Tightly controlled

component distributions give the customer greater circuit

predictability. Many customers are also converting to

just–in–time (JIT) delivery programs. These programs require

improvements in cycle time and yield predictability achievable

only through SPC techniques. The benefit derived from SPC

helps the manufacturer meet the customer’s expectations of

higher quality and lower cost product.

–6σ –5σ –4σ –3σ –2σ –1σ

0

1σ 2σ 3σ 4σ 5σ 6σ

Standard Deviations From Mean

Distribution Centered

At ± 3σ 2700 ppm defective

Distribution Shifted ± 1.5

66810 ppm defective

93.32% yield

99.73% yield

At ± 4σ 63 ppm defective

6210 ppm defective

99.379% yield

99.9937% yield

At ± 5σ 0.57 ppm defective

233 ppm defective

99.9767% yield

99.999943% yield

At ± 6σ 0.002 ppm defective

3.4 ppm defective

99.99966% yield

99.9999998% yield

Figure 1. AOQL and Yield from a Normal

Distribution of Product With 6σ Capability

To better understand SPC principles, brief explanations

have been provided. These cover process capability,

implementation, and use.

PROCESS CAPABILITY

One goal of SPC is to ensure a process is CAPABLE.

Process capability is the measurement of a process to

produce products consistently to specification requirements.

The purpose of a process capability study is to separate the

inherent RANDOM VARIABILITY from ASSIGNABLE

CAUSES. Once completed, steps are taken to identify and

eliminate the most significant assignable causes. Random

variability is generally present in the system and does not

fluctuate. Sometimes, the random variability is due to basic

limitations associated with the machinery, materials,

personnel skills, or manufacturing methods. Assignable

cause inconsistencies relate to time variations in yield,

performance, or reliability.

Ultimately, Motorola will have Six Sigma capability on all

products. Thismeansparametricdistributionswillbecentered

withinthespecificationlimits, withaproductdistributionofplus

or minus Six Sigma about mean. Six Sigma capability, shown

graphically in Figure 1, details the benefit in terms of yield and

outgoing quality levels. This compares a centered distribution

versus a 1.5 sigma worst case distribution shift.

Traditionally, assignable causes appear to be random due

to the lack of close examination or analysis. Figure 2 shows

the impact on predictability that assignable cause can have.

Figure 3 shows the difference between process control and

process capability.

A process capability study involves taking periodic samples

from the process under controlled conditions. The

performance characteristics of these samples are charted

against time. In time, assignable causes can be identified and

engineered out. Careful documentation of the process is the

key to accurate diagnosis and successful removal of the

assignable causes. Sometimes, the assignable causes will

remain unclear, requiring prolonged experimentation.

Elements which measure process variation control and

capability are Cp and Cpk, respectively. Cp is the specification

width divided by the process width or Cp = (specification

width) / 6σ. Cpk is the absolute value of the closest

specification value to the mean, minus the mean, divided by

NewproductdevelopmentatMotorolarequiresmorerobust

design features that make them less sensitive to minor

variations in processing. These features make the

implementation of SPC much easier.

A complete commitment to SPC is present throughout

Motorola. All managers, engineers, production operators,

supervisors, and maintenance personnel have received

multiple training courses on SPC techniques. Manufacturing

has identified 22 wafer processing and 8 assembly steps

considered critical to the processing of semiconductor

products. Processes controlled by SPC methods that have

shown significant improvement are in the diffusion,

photolithography, and metallization areas.

half the process width or Cpk = closest specification – /3σ.

X

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Reliability and Quality Assurance

9–17

PREDICTION

In control assignable

causes eliminated

TIME

Out of control

(assignable causes present)

SIZE

Process “under control” – all assignable causes are

removed and future distribution is predictable.

SIZE

?

Lower

Specification Limit

PREDICTION

Upper

Specification Limit

In control and capable

(variation from random

variability reduced)

TIME

In control but not capable

TIME

SIZE

(variation from random variability

excessive)

SIZE

Figure 2. Impact of Assignable Causes

on Process Predictable

Figure 3. Difference Between Process

Control and Process Capability

At Motorola, for critical parameters, the process capability

is acceptable with a Cpk = 1.50 with continual improvement

our goal. The desired process capability is a Cpk = 2 and the

ideal is a Cpk = 5. Cpk, by definition, shows where the current

production process fits with relationship to the specification

limits. Off center distributions or excessive process variability

will result in less than optimum conditions.

be collected at appropriate time intervals to detect variations

in the process. As the process begins to show improved

stability, the interval may be increased. The data collected

must be carefully documented and maintained for later

correlation. Examples of common documentation entries are

operator, machine, time, settings, product type, etc.

Oncetheplanisestablished, datacollectionmaybegin. The

data collected with generate X and R values that are plotted

with respect to time. X refers to the mean of the values within

a given subgroup, while R is the range or greatest value minus

least value. When approximately 20 or more X and R values

have been generated, the average of these values is

computed as follows:

SPC IMPLEMENTATION AND USE

CPSTG uses many parameters that show conformance to

specification. Some parameters are sensitive to process

variations while others remain constant for a given product

line. Often, specific parameters are influenced when changes

to other parameters occur. It is both impractical and

unnecessary to monitor all parameters using SPC methods.

Only critical parameters that are sensitive to process

variability are chosen for SPC monitoring. The process steps

affecting these critical parameters must be identified as well.

It is equally important to find a measurement in these process

steps that correlates with product performance. This

measurement is called a critical process parameter.

Once the critical process parameters are selected, a

sample plan must be determined. The samples used for

measurement are organized into RATIONAL SUBGROUPS

of approximately two to five pieces. The subgroup size should

be such that variation among the samples within the subgroup

remain small. All samples must come from the same source

e.g.,thesamemoldpressoperator, etc. Subgroupdatashould

X = (X + X2 + X3 + . . .)/K

R = (R1 + R2 + R2 + . . .)/K

where K = the number of subgroups measured.

ThevaluesofXandRareusedtocreatetheprocesscontrol

chart. Control charts are the primary SPC tool used to signal

a problem. Shown in Figure 4, process control charts show X

and R values with respect to time and concerning reference

to upper and lower control limit values. Control limits are

computed as follows:

R upper control limit = UCL = D4 R

R

R lower control limit = LCL = D3 R

R

X upper control limit = UCL = X + A2 R

X

X lower control limit = LCL = X – A2 R

X

Reliability and Quality Assurance

9–18

Motorola Small–Signal Transistors, FETs and Diodes Device Data

154

153

UCL = 152.8

= 150.4

152

151

X

150

149

148

147

LCL = 148.0

UCL = 7.3

7

6

5

4

= 3.2

R

3

2

1

0

LCL = 0

Figure 4. Example of Process Control Chart Showing Oven Temperature Data

Where D4, D3, and A2 are constants varying by sample size,

with values for sample sizes from 2 to 10 shown in the

following partial table:

σ tot =

2

σ A + σ B + σ C + σ D + σ E

2

5 + 3 + 2 + 1 +(0.4) = 6.3

n

2

3

4

5

2.11

*

6

7

8

9

10

2.00 1.92 1.86 1.82 1.78

0.08 0.14 0.18 0.22

If only D is identified and eliminated, then:

σ tot =

D

3.27 2.57 2.28

4

3

2

5 + 3 + 2 + (0.4) = 6.2

D

A

*

This results in less than 2% total variability improvement. If

B, C, and D were eliminated, then:

1.88 1.02 0.73 0.58 0.48 0.42 0.37 0.34 0.31

*For sample sizes below 7, the LCL would technically be a negative number;

R

inthosecasesthereisnolowercontrollimit;thismeansthatforasubgroupsize

6, six ‘‘identical’’ measurements would not be unreasonable.

σ tot =

2

5 + (0.4) = 5.02

This gives a considerably better improvement of 23%. If

only A is identified and reduced from 5 to 2, then:

Control charts are used to monitor the variability of critical

process parameters. The R chart shows basic problems with

piece to piece variability related to the process. The X chart can

often identify changes in people, machines, methods, etc. The

source of the variability can be difficult to find and may require

experimental design techniques to identify assignable causes.

Some general rules have been established to help determine

when a process is OUT–OF–CONTROL. Figure 5 shows a

control chart subdivided into zones A, B, and C corresponding

to 3 sigma, 2 sigma, and 1 sigma limits respectively. In Figures

6 through 9 four of the tests that can be used to identify

excessive variability and the presence of assignable causes

are shown. As familiarity with a given process increases, more

subtle tests may be employed successfully.

Once the variability is identified, the cause of the variability

must be determined. Normally, only a few factors have a

significant impact on the total variability of the process. The

importance of correctly identifying these factors is stressed in

the following example. Suppose a process variability depends

on the variance of five factors A, B, C, D, and E. Each has a

variance of 5, 3, 2, 1, and 0.4, respectively.

σ tot =

2

2 + 3 + 2 + 1 + (0.4) = 4.3

Identifying and improving the variability from 5 to 2 yields a

total variability improvement of nearly 40%.

Most techniques may be employed to identify the primary

assignable cause(s). Out–of–control conditions may be

correlated to documented process changes. The product may

be analyzed in detail using best versus worst part comparisons

or Product Analysis Lab equipment. Multi–variance analysis

can be used to determine the family of variation (positional,

critical, or temporal). Lastly, experiments may be run to test

theoretical or factorial analysis. Whatever method is used,

assignable causes must be identified and eliminated in the

most expeditious manner possible.

After assignable causes have been eliminated, new control

limits are calculated to provide a more challenging variablility

criteria for the process. As yields and variability improve, it may

become more difficult to detect improvements because they

become much smaller. When all assignable causes have been

eliminated and the points remain within control limits for 25

groups, the process is said to in a state of control.

Since:

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Reliability and Quality Assurance

9–19

UCL

A

B

C

B

A

ZONE A (+ 3 SIGMA)

ZONE B (+ 2 SIGMA)

ZONE C (+ 1 SIGMA)

ZONE C (– 1 SIGMA)

ZONE B (– 2 SIGMA)

ZONE A (– 3 SIGMA)

CENTERLINE

LCL

UCL

Figure 5. Control Chart Zones

Figure 6. One Point Outside Control Limit

Indicating Excessive Variability

UCL

A

B

C

B

A

B

C

B

A

LCL

Figure 7. Two Out of Three Points in Zone A or

Beyond Indicating Excessive Variability

Figure 8. Four Out of Five Points in Zone B or

Beyond Indicating Excessive Variability

UCL

A

B

C

B

A

LCL

Figure 9. Seven Out of Eight Points in Zone C or

Beyond Indicating Excessive Variability

SUMMARY

Motorola is committed to the use of STATISTICAL

PROCESS CONTROLS. These principles, used throughout

manufacturing have already resulted in many significant

improvements to the processes. Continued dedication to the

SPC culture will allow Motorola to reach the Six Sigma and

zero defect capability goals. SPC will further enhance the

commitment to TOTAL CUSTOMER SATISFACTION.

Reliability and Quality Assurance

9–20

Motorola Small–Signal Transistors, FETs and Diodes Device Data

REPLACEMENT DEVICES

DEVICE

REPLACEMENT

MV2101

DEVICE

REPLACEMENT

DEVICE

REPLACEMENT

BC560C

1N5139

1N5139A

1N5140

1N5140A

1N5141

1N5141A

1N5142

1N5142A

1N5143

1N5143A

2N3053A

2N3244

2N3250

2N3251

2N3251A

2N3467

2N3468

2N3497

2N3500

2N3501

MPSA05

2N4403

MPS2907A

MPSA56

2N5401

BC560B

MV2101

BC849ALT1

BC850ALT1

BC857CLT1

BCY70

BCY71

BCY72

BDB01D

BDB02D

BDC02D

BC848ALT1

BC857ALT1

MPS2222A

BDB01C

MMBV2103LT1

MMBV2104LT1

MMBV2105LT1

2N5551

BDB02C

BDC01D

1N5144

1N5144A

1N5145

1N5145A

1N5146

1N5146A

1N5147

1N5147A

1N5441A

1N5443A

MMBV2107LT1

MMBV2108LT1

MMBV2109LT1

MV2109

MV2111

MV2101

MV2103

2N3546

2N3634

2N3635

2N3636

2N3637

2N3700

2N3799

2N3947

2N3963

2N3964

MPSH17

2N5401

MPSA92

MPSA06

MPSA18

MPS2222A

MPSA18

BDC05

BF244A

BF244B

BF245

BF245A

BF245B

BF245C

BF246A

BF246B

BF247B

MPSW42

2N3819

BF245A

1N5444A

1N5445A

1N5449A

1N5450A

1N5451A

1N5452A

1N5453A

1N5455A

2N697

MV2104

MV2105

MV2108

MV2109

MV2111

MV2115

MPSA20

MPSA05

2N4014

2N4032

2N4033

2N4036

2N4037

2N4126

2N4265

2N4405

2N4407

2N4931

MPS2222A

MPS2907A

MPSA56

MPS4126

2N4264

MPS8599

MPSA92

BF256B

BF256C

BF258

BF374

BF391

BF392

BF492

BF493

BFW43

BSP20AT1

BF256A

BF422

BC338

MPSA42

MPSA92

2N5401

BF720T1

2N718A

2N720A

2N930

2N930A

2N956

2N1613

2N1711

2N1893

2N2102

2N2218A

2N2219

MPSA06

MPSA18

MPSA05

2N4410

MPSA05

MPSA06

2N4410

2N5086

2N5668

2N5669

2N5670

2N6431

2N6433

2N6516

BA582T1

BC107

2N5087

2N3819

MPSA42

MPSA92

2N6517

MMBV3401LT1

BC237

BSS71

BSS72

BSS73

BSS74

BSS75

BSS76

BSS89

BSV16–10

BSX20

CV12253

MPSA42

MPSA92

BS107

MPS2907A

MPS2369A

MPSA06

MPS2222A

BC107A

BC237

2N2219A

2N2222

2N2222A

2N2270

2N2369

2N2369A

2N2484

2N2895

2N2896

2N2904

MPS2222A

MPS2222

MPS2222A

MPSA05

MPS2369

MPS2369A

2N5087

MPSA06

2N5551

MPS2907

BC107B

BC108

BC109C

BC140–10

BC140–16

BC141–10

BC141–16

BC160–16

BC161–16

BC177

BC237

IRFD110

IRFD113

IRFD120

IRFD123

IRFD210

IRFD213

IRFD220

IRFD223

IRFD9120

IRFD9123

BSS123LT1

MMBF170LT1

BSS123LT1

MMBF170LT1

MMFT107T1

BSS123LT1

2N7002LT1

BC3338

MPSW06

MPSW56

BC547

2N2904A

2N2905

2N2905A

2N2906

2N2906A

2N2907

2N2907A

2N3019

2N3020

2N3053

MPS2907A

MPS2907

MPS2907A

MPS2907

MPS2907A

MPS2907

MPS2907A

MPSA06

BC177A

BC177B

BC238

BC309B

BC393

BC394

BC450

BC450A

BC546A

BC559

BC547A

BC547B

BC238B

BC308C

MPSA92

MPSA42

MPSA92

BC546B

BC559B

J111

J113

J203

J300

J111RLRA

J113RL1

2N5458

2N5486

J305

MMBF5484LT1

BAS16LT1

MAD130P

MAD1103P

MAD1107P

MAD1108P

MAD1109P

MPSA06

MPSA20

Replacement Devices

10–2

Motorola Small–Signal Transistors, FETs and Diodes Device Data

REPLACEMENT DEVICES

DEVICE

REPLACEMENT

2N5551

MPS2222A

2N5401

DEVICE

REPLACEMENT

DEVICE

REPLACEMENT

MV2115

MM3001

MM3725

MM4001

MMAD1106

MMBF4856LT1

MMBF4860LT1

MMBF5459LT1

MMBF5486LT1

MMBT8599LT1

MMBV2104LT1

MPS6530

MPS6531

MPS6562

MPS6568A

MPS6571

MPS6595

MPS8093

MPSA16

MPS6530RLRM

MPS6651

MPS918

MPSA18

MPS3563

2N4402

MPSA17

MPSH17

MV2114

MVAM108

MVAM109

MVAM115

MVAM125

PBF259

PBF259S

PBF259RS

PBF493

MMBV2109LT1

MMBT6517LT1

MMBTA92LT1

BAS16LT1

MMBF4391LT1

MMBF5457LT1

2N5486

MMBT5551LT1

MMBV2103LT1

MPSH04

MPSH07A

PBF493R

MMPQ3799

MMSV3401T1

MPF970

MMPQ3725

MMBV3401LT1

MMBFJ175LT1

MMBF5457LT1

MPF4391RLRA

2N5639

MPSH20

MPSH24

MPSH34

MPSH69

MSA1022–BT1

MSB709–ST1

MSB710–QT1

MSB1218A–ST1

MSC1621T1

MSC2404–CT1

MPSH17

MPSH81

MSA1022–CT1

MSB709–RT1

MSB710–RT1

MSB1218A–RT1

MSD602–RT1

MSC2295–CT1

PBF493RS

PBF493S

VN1706L

MMBTA92LT1

MMFT107T1

MPF971

MPF3821

MPF3822

MPF4856

MPF4857

MPF4858

MPF4859

J112

2N5638RLRA

MPF4860

MPF4861

MPQ6501

MPS3638

MPS3866

MPS4123

MPS4125

MPS4258

MPS5771

MPS6520

2N5638RLRA

J112

MPQ6502

MPS3638A

BF224

MPS4124

MPS4126

MPS3640

MPS6521

MSD1819A–ST1 MSD1819A–RT1

MV1620

MV1624

MV1636

MV1640

MV1642

MV1644

MV2103

MV2107

MV2113

MV2101

MMBV2103LT1

MV2108

MV2109

MV2111

MMBV2103LT1

MV2108

MV2111

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Replacement Devices

10–3


型号：	BC307BRLRM
厂家：	ONSEMI
描述：	100mA, 45V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-92, PLASTIC, TO-226AA, 3 PIN
文件：	总34页 (文件大小：318K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BC307BRLRM [ONSEMI]

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