BC557ARLRM [ONSEMI]
TRANSISTOR 100 mA, 45 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-92, TO-226AA, 3 PIN, BIP General Purpose Small Signal;型号: | BC557ARLRM |
厂家: | ONSEMI |
描述: | TRANSISTOR 100 mA, 45 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-92, TO-226AA, 3 PIN, BIP General Purpose Small Signal |
文件: | 总25页 (文件大小:310K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
PNP Silicon
COLLECTOR
1
2
BASE
3
EMITTER
MAXIMUM RATINGS
1
2
Rating
Collector–Emitter Voltage
Collector–Base Voltage
Emitter–Base Voltage
Symbol BC556 BC557 BC558
Unit
Vdc
3
V
CEO
V
CBO
V
EBO
–65
–80
–45
–50
–30
–30
CASE 29–04, STYLE 17
TO–92 (TO–226AA)
Vdc
–5.0
–100
Vdc
Collector Current — Continuous
I
C
mAdc
Total Device Dissipation @ T = 25°C
Derate above 25°C
P
D
625
5.0
mW
mW/°C
A
Total Device Dissipation @ T = 25°C
Derate above 25°C
P
D
1.5
12
Watt
mW/°C
C
Operating and Storage Junction
Temperature Range
T , T
–55 to +150
°C
J
stg
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
200
Unit
°C/W
°C/W
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
R
R
JA
JC
83.3
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage
(I = –2.0 mAdc, I = 0)
V
V
V
V
V
V
(BR)CEO
(BR)CBO
(BR)EBO
BC556
BC557
BC558
–65
–45
–30
—
—
—
—
—
—
C
B
Collector–Base Breakdown Voltage
(I = –100 µAdc)
C
BC556
BC557
BC558
–80
–50
–30
—
—
—
—
—
—
Emitter–Base Breakdown Voltage
(I = –100 Adc, I = 0)
BC556
BC557
BC558
–5.0
–5.0
–5.0
—
—
—
—
—
—
E
C
Collector–Emitter Leakage Current
I
CES
(V
CES
(V
CES
= –40 V)
= –20 V)
BC556
BC557
BC558
BC556
BC557
BC558
—
—
—
—
—
—
–2.0
–2.0
–2.0
—
—
—
–100
–100
–100
–4.0
–4.0
–4.0
nA
(V
CES
= –20 V, T = 125°C)
µA
A
Motorola Small–Signal Transistors, FETs and Diodes Device Data
2–123
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)
A
Characteristic
Symbol
Min
Typ
Max
Unit
ON CHARACTERISTICS
DC Current Gain
(I = –10 µAdc, V
C CE
h
FE
—
= –5.0 V)
BC557A
BC556B/557B/558B
BC557C
BC556
BC557
BC558
BC557A
BC556B/557B/558B
BC557C
BC557A
—
—
—
120
120
120
120
180
420
—
90
150
270
—
—
—
170
290
500
120
180
300
—
—
—
500
800
800
220
460
800
—
(I = –2.0 mAdc, V
C
= –5.0 V)
= –5.0 V)
CE
(I = –100 mAdc, V
C CE
BC556B/557B/558B
BC557C
—
—
—
—
Collector–Emitter Saturation Voltage
(I = –10 mAdc, I = –0.5 mAdc)
V
V
V
CE(sat)
—
—
—
–0.075
–0.3
–0.25
–0.3
–0.6
–0.65
C
B
(I = –10 mAdc, I = see Note 1)
C
C
B
B
(I = –100 mAdc, I = –5.0 mAdc)
Base–Emitter Saturation Voltage
(I = –10 mAdc, I = –0.5 mAdc)
V
V
BE(sat)
—
—
–0.7
–1.0
—
—
C
C
B
B
(I = –100 mAdc, I = –5.0 mAdc)
Base–Emitter On Voltage
V
BE(on)
(I = –2.0 mAdc, V
(I = –10 mAdc, V
C
= –5.0 Vdc)
CE
= –5.0 Vdc)
CE
–0.55
—
–0.62
–0.7
–0.7
–0.82
C
SMALL–SIGNAL CHARACTERISTICS
Current–Gain — Bandwidth Product
f
T
MHz
(I = –10 mA, V
= –5.0 V, f = 100 MHz)
CE
BC556
BC557
BC558
—
—
—
280
320
360
—
—
—
C
Output Capacitance
(V = –10 V, I = 0, f = 1.0 MHz)
C
—
3.0
6.0
pF
dB
ob
CB
Noise Figure
(I = –0.2 mAdc, V
C
NF
= –5.0 V,
CE
= 2.0 k , f = 1.0 kHz, ∆f = 200 Hz)
BC556
BC557
BC558
—
—
—
2.0
2.0
2.0
10
10
10
C
R
S
Small–Signal Current Gain
(I = –2.0 mAdc, V = –5.0 V, f = 1.0 kHz) BC556
h
fe
—
125
125
125
240
450
—
—
220
330
600
500
900
260
500
900
C
CE
BC557/558
BC557A
BC556B/557B/558B
BC557C
Note 1: I = –10 mAdc on the constant base current characteristics, which yields the point I = –11 mAdc, V
CE
= –1.0 V.
C
C
2–124
Motorola Small–Signal Transistors, FETs and Diodes Device Data
BC557/BC558
2.0
1.5
–1.0
T = 25°C
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
A
V
= –10 V
CE
V
@ I /I = 10
BE(sat) C B
T = 25°C
A
1.0
0.7
0.5
V
BE(on)
@ V = –10 V
CE
0.3
0.2
V
@ I /I = 10
CE(sat) C B
–0.2
–0.5 –1.0 –2.0
–5.0 –10 –20
–50 –100 –200
–0.1
–1.0
–10
–100
–50
–0.2
–0.5
–2.0
–5.0
–20
I , COLLECTOR CURRENT (mAdc)
C
I , COLLECTOR CURRENT (mAdc)
C
Figure 1. Normalized DC Current Gain
Figure 2. “Saturation” and “On” Voltages
1.0
1.2
1.6
2.0
2.4
2.8
–2.0
–1.6
–1.2
–0.8
–0.4
0
–55°C to +125°C
T = 25°C
A
I
=
I
= –50 mA
I = –200 mA
C
C
C
–10 mA
I
C
= –100 mA
I
= –20 mA
C
–0.02
–0.1
–1.0
–10 –20
–0.2
–1.0
–10
–100
I , BASE CURRENT (mA)
B
I , COLLECTOR CURRENT (mA)
C
Figure 3. Collector Saturation Region
Figure 4. Base–Emitter Temperature Coefficient
10
7.0
5.0
400
300
C
ib
T = 25°C
A
200
150
V
= –10 V
CE
T = 25°C
A
100
80
C
ob
3.0
2.0
60
40
30
1.0
–0.4
20
–0.5
–0.6 –1.0
–2.0
–4.0 –6.0 –10
–20 –30 –40
–1.0
–2.0 –3.0 –5.0
–10
–20 –30 –50
V , REVERSE VOLTAGE (VOLTS)
R
I , COLLECTOR CURRENT (mAdc)
C
Figure 5. Capacitances
Figure 6. Current–Gain – Bandwidth Product
Motorola Small–Signal Transistors, FETs and Diodes Device Data
2–125
BC556
–1.0
–0.8
–0.6
T = 25°C
J
V
= –5.0 V
CE
T = 25°C
A
V
@ I /I = 10
BE(sat) C B
2.0
1.0
0.5
V
BE
@ V = –5.0 V
CE
–0.4
–0.2
0
0.2
V
@ I /I = 10
CE(sat) C B
–0.1 –0.2
–1.0 –2.0
–10 –20
–100 –200
–50
–0.2 –0.5 –1.0 –2.0
–5.0 –10 –20
–50 –100 –200
–5.0
I , COLLECTOR CURRENT (AMP)
C
I , COLLECTOR CURRENT (mA)
C
Figure 7. DC Current Gain
Figure 8. “On” Voltage
–2.0
–1.6
–1.2
–0.8
–0.4
0
–1.0
–1.4
–1.8
–2.2
–2.6
–3.0
–100 mA –200 mA
I
=
–20 mA
–50 mA
C
–10 mA
θ
for V
BE
VB
–55°C to 125°C
T = 25°C
J
–0.02 –0.05 –0.1 –0.2
–0.5 –1.0 –2.0
–5.0 –10 –20
–0.2 –0.5 –1.0 –2.0
–5.0 –10 –20
–50 –100 –200
I , BASE CURRENT (mA)
B
I , COLLECTOR CURRENT (mA)
C
Figure 9. Collector Saturation Region
Figure 10. Base–Emitter Temperature Coefficient
40
20
V
CE
= –5.0 V
500
T = 25°C
J
C
ib
200
100
50
10
8.0
6.0
4.0
C
ob
20
2.0
–0.1 –0.2
–0.5 –1.0 –2.0
–5.0 –10 –20
–50 –100
–1.0
–10
–100
V , REVERSE VOLTAGE (VOLTS)
R
I , COLLECTOR CURRENT (mA)
C
Figure 11. Capacitance
Figure 12. Current–Gain – Bandwidth Product
2–126
Motorola Small–Signal Transistors, FETs and Diodes Device Data
1.0
0.7
0.5
D = 0.5
0.2
0.3
0.2
SINGLE PULSE
0.05
Z
(t) = (t) R
= 83.3°C/W MAX
(t) = r(t) R
= 200°C/W MAX
0.1
θJC
θJC
0.1
0.07
0.05
R
θJC
P
(pk)
SINGLE PULSE
Z
R
θJA
θJA
θJA
t
1
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
t
2
0.03
0.02
DUTY CYCLE, D = t /t
1 2
READ TIME AT t
1
T
– T = P
R
(t)
J(pk)
C
(pk) θJC
0.01
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50
100
200
500
1.0 k
2.0 k
5.0 k
10 k
t, TIME (ms)
Figure 13. Thermal Response
–200
1 s
3 ms
–100
–50
The safe operating area curves indicate I –V
limits of the
CE
C
transistor that must be observed for reliable operation. Collector load
lines for specific circuits must fall below the limits indicated by the
applicable curve.
T = 25°C
J
T = 25°C
A
The data of Figure 14 is based upon T
= 150°C; T or T is
J(pk)
C A
BC558
BC557
BC556
variable depending upon conditions. Pulse curves are valid for duty
cyclesto10%providedT ≤150°C. T maybecalculatedfrom
J(pk)
J(pk)
–10
the data in Figure 13. At high case or ambient temperatures, thermal
limitations will reduce the power than can be handled to values less
than the limitations imposed by second breakdown.
–5.0
BONDING WIRE LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
–2.0
–1.0
–5.0
–10
–30 –45 –65 –100
V , COLLECTOR–EMITTER VOLTAGE (V)
CE
Figure 14. Active Region — Safe Operating Area
Motorola Small–Signal Transistors, FETs and Diodes Device Data
2–127
EMBOSSED TAPE AND REEL
SOT-23, SC-59, SC-70/SOT-323, SC–90/SOT–416, SOT-223 and SO-16 packages are available only in
Tape and Reel. Use the appropriate suffix indicated below to order any of the SOT-23, SC-59,
SC-70/SOT-323, SOT-223 and SO-16 packages. (See Section 6 on Packaging for additional information).
SOT-23:
SC-59:
SC-70/
available in 8 mm Tape and Reel
Use the device title (which already includes the “T1” suffix) to order the 7 inch/3000 unit reel.
Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/10,000 unit reel.
available in 8 mm Tape and Reel
Use the device title (which already includes the “T1” suffix) to order the 7 inch/3000 unit reel.
Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/10,000 unit reel.
available in 8 mm Tape and Reel
SOT-323: Use the device title (which already includes the “T1” suffix) to order the 7 inch/3000 unit reel.
Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/10,000 unit reel.
SOT-223: available in 12 mm Tape and Reel
Use the device title (which already includes the “T1” suffix) to order the 7 inch/1000 unit reel.
Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/4000 unit reel.
SO-16:
available in 16 mm Tape and Reel
Add an “R1” suffix to the device title to order the 7 inch/500 unit reel.
Add an “R2” suffix to the device title to order the 13 inch/2500 unit reel.
RADIAL TAPE IN FAN FOLD BOX OR REEL
TO-92 packages are available in both bulk shipments and in Radial Tape in Fan Fold Boxes or Reels.
Fan Fold Boxes and Radial Tape Reel are the best methods for capturing devices for automatic insertion in
printed circuit boards.
TO-92:
available in Fan Fold Box
Add an “RLR” suffix and the appropriate Style code* to the device title to order the Fan Fold box.
available in 365 mm Radial Tape Reel
Add an “RLR” suffix and the appropriate Style code* to the device title to order the Radial Tape
Reel.
*Refer to Section 6 on Packaging for Style code characters and additional information on ordering
*requirements.
DEVICE MARKINGS/DATE CODE CHARACTERS
SOT-23, SC-59, SC-70/SOT-323, and the SC–90/SOT–416 packages have a device marking and a date
code etched on the device. The generic example below depicts both the device marking and a representa-
tion of the date code that appears on the SC-70/SOT-323, SC-59 and SOT-23 packages.
D
ABC
The “D” represents a smaller alpha digit Date Code. The Date Code indicates the actual month in which the
part was manufactured.
2–2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Tape and Reel Specifications
and Packaging Specifications
Embossed Tape and Reel is used to facilitate automatic pick and place equipment feed requirements. The tape is used as the
shipping container for various products and requires a minimum of handling. The antistatic/conductive tape provides a secure
cavity for the product when sealed with the “peel–back” cover tape.
• Two Reel Sizes Available (7″ and 13″)
• Used for Automatic Pick and Place Feed Systems
• Minimizes Product Handling
• SOD–123, SC–59, SC–70/SOT–323, SC–70ML/SOT–363,
SOT–23, TSOP–6, in 8 mm Tape
• SOT–223 in 12 mm Tape
• EIA 481, –1, –2
• SO–14, SO–16 in 16 mm Tape
Usethestandarddevicetitleandaddtherequiredsuffixaslistedintheoptiontableonthefollowingpage. Notethattheindividual
reels have a finite number of devices depending on the type of product contained in the tape. Also note the minimum lot size is
one full reel for each line item, and orders are required to be in increments of the single reel quantity.
SC–70ML/SOT–363, TSOP–6
T1 ORIENTATION
SC–59, SC–70/SOT–323, SOT–23
SOD–123
8 mm
8 mm
8 mm
SC–70ML/SOT–363
SOT–223
SO–14, 16
DIRECTION
OF FEED
T2 ORIENTATION
12 mm
16 mm
8 mm
EMBOSSED TAPE AND REEL ORDERING INFORMATION
Devices Per Reel
and Minimum
Order Quantity
Tape Width
(mm)
Pitch
(inch)
Reel Size
mm (inch)
Device
Suffix
mm
Package
SC–59
8
4.0 ± 0.1 (.157 ± .004)
4.0 ± 0.1 (.157 ± .004)
178
(7)
3,000
T1
SC–70/SOT–323
8
8
178
330
(7)
(13)
3,000
10,000
T1
T3
SO–14
SO–16
16
16
8.0 ± 0.1 (.315 ± .004)
8.0 ± 0.1 (.315 ± .004)
4.0 ± 0.1 (.157 ± .004)
4.0 ± 0.1 (.157 ± .004)
8.0 ± 0.1 (.315 ± .004)
4.0 ± 0.1 (.157 ± .004)
4.0 ± 0.1 (.157 ± .004)
178
330
(7)
(13)
500
2,500
R1
R2
16
16
178
330
(7)
(13)
500
2,500
R1
R2
SOD–123
8
8
178
330
(7)
(13)
3,000
10,000
T1
T3
SOT–23
8
8
178
330
(7)
(13)
3,000
10,000
T1
T3
SOT–223
12
12
178
330
(7)
(13)
1,000
4,000
T1
T3
SC–70ML/SOT–363
TSOP–6
8
8
178
178
(7)
(7)
3,000
3,000
T1
T2
8
178
(7)
3,000
T1
Tape and Reel Specifications
6–2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
EMBOSSED TAPE AND REEL DATA FOR DISCRETES
CARRIER TAPE SPECIFICATIONS
10 Pitches Cumulative Tolerance on Tape
P
0
± 0.2 mm
(± 0.008″)
K
t
P
2
D
E
F
Top Cover
Tape
A
0
W
K
0
B
0
B
1
See
Note 1
P
D
1
Center Lines
of Cavity
Embossment
For Components
2.0 mm x 1.2 mm and Larger
For Machine Reference Only
Including Draft and RADII
User Direction of Feed
Concentric Around B
0
* Top Cover Tape
Thickness (t )
0.10 mm
1
Bar Code Label
R Min
(.004″) Max.
Tape and Components
Shall Pass Around Radius “R”
Without Damage
Bending Radius
Embossed Carrier
100 mm
(3.937″)
Embossment
10°
Maximum Component Rotation
1 mm Max
Typical Component
Cavity Center Line
Tape
1 mm
(.039″) Max
250 mm
(9.843″)
Typical Component
Center Line
Camber (Top View)
Allowable Camber To Be 1 mm/100 mm Nonaccumulative Over 250 mm
DIMENSIONS
Tape
Size
B
Max
D
D
E
F
K
P
P
2
R Min
T Max
W Max
1
1
0
8 mm
4.55 mm
(.179″)
1.0 Min
(.039″)
3.5±0.05 mm
(.138±.002″)
2.4 mm Max
(.094″)
25 mm
(.98″)
8.3 mm
(.327″)
1.5+0.1 mm
–0.0
1.75±0.1 mm
(.069±.004″)
4.0±0.1 mm
(.157±.004″)
2.0±0.1 mm
(.079±.002″)
0.6 mm
(.024″)
(.059+.004″
–0.0)
12 mm
16 mm
24 mm
8.2 mm
(.323″)
5.5±0.05 mm
(.217±.002″)
6.4 mm Max
(.252″)
12±.30 mm
(.470±.012″)
1.5 mm Min
(.060″)
30 mm
(1.18″)
12.1 mm
(.476″)
7.5±0.10 mm
(.295±.004″)
7.9 mm Max
(.311″)
16.3 mm
(.642″)
20.1 mm
(.791″)
11.5±0.1 mm
(.453±.004″)
11.9 mm Max
(.468″)
24.3 mm
(.957″)
Metric dimensions govern — English are in parentheses for reference only.
NOTE 1: A , B , and K are determined by component size. The clearance between the components and the cavity must be within .05 mm min. to .50 mm max.,
0
0
0
NOTE 1: the component cannot rotate more than 10° within the determined cavity.
NOTE 2: If B exceeds 4.2 mm (.165) for 8 mm embossed tape, the tape may not feed through all tape feeders.
1
NOTE 3: Pitch information is contained in the Embossed Tape and Reel Ordering Information on pg. 5.12–3.
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Tape and Reel Specifications
6–3
EMBOSSED TAPE AND REEL DATA FOR DISCRETES
T Max
Outside Dimension
Measured at Edge
1.5 mm Min
(.06″)
13.0 mm ± 0.5 mm
(.512″ ± .002″)
A
20.2 mm Min
(.795″)
50 mm Min
(1.969″)
Full Radius
Inside Dimension
G
Measured Near Hub
Size
A Max
G
T Max
8 mm
330 mm
8.4 mm + 1.5 mm, –0.0
14.4 mm
(12.992″)
(.33″ + .059″, –0.00)
(.56″)
12 mm
16 mm
24 mm
330 mm
(12.992″)
12.4 mm + 2.0 mm, –0.0
(.49″ + .079″, –0.00)
18.4 mm
(.72″)
360 mm
(14.173″)
16.4 mm + 2.0 mm, –0.0
(.646″ + .078″, –0.00)
22.4 mm
(.882″)
360 mm
24.4 mm + 2.0 mm, –0.0
30.4 mm
(14.173″)
(.961″ + .070″, –0.00)
(1.197″)
Reel Dimensions
Metric Dimensions Govern — English are in parentheses for reference only
Tape and Reel Specifications
6–4
Motorola Small–Signal Transistors, FETs and Diodes Device Data
TO–92 EIA, IEC, EIAJ
Radial Tape in Fan Fold
Box or On Reel
TO–92
RADIAL
TAPE IN
FAN FOLD
BOX OR
ON REEL
Radial tape in fan fold box or on reel of the reliable TO–92 package are
the best methods of capturing devices for automatic insertion in printed
circuit boards. These methods of taping are compatible with various
equipment for active and passive component insertion.
• Available in Fan Fold Box
• Available on 365 mm Reels
• Accommodates All Standard Inserters
• Allows Flexible Circuit Board Layout
• 2.5 mm Pin Spacing for Soldering
• EIA–468, IEC 286–2, EIAJ RC1008B
Ordering Notes:
When ordering radial tape in fan fold box or on reel, specify the style per
Figures 3 through 8. Add the suffix “RLR” and “Style” to the device title, i.e.
MPS3904RLRA. This will be a standard MPS3904 radial taped and
supplied on a reel per Figure 9.
Fan Fold Box Information — Order in increments of 2000.
Reel Information — Order in increments of 2000.
US/European Suffix Conversions
US
EUROPE
RL
RLRA
RLRE
RLRM
RL1
ZL1
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Packaging Specifications
6–5
TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
H2A
H2A
H2B
H2B
H
W2
H4
H5
T1
L1
H1
W1
W
L
T
T2
F1
F2
D
P2
P1
P2
P
Figure 1. Device Positioning on Tape
Specification
Millimeter
Inches
Symbol
D
Item
Min
Max
Min
Max
0.1496
0.015
0.0945
.059
0.1653
3.8
4.2
Tape Feedhole Diameter
D2
F1, F2
H
0.020
0.110
.156
0.38
2.4
1.5
8.5
0
0.51
2.8
Component Lead Thickness Dimension
Component Lead Pitch
4.0
Bottom of Component to Seating Plane
Feedhole Location
H1
H2A
H2B
H4
H5
L
0.3346
0
0.3741
0.039
0.051
0.768
0.649
0.433
—
9.5
1.0
Deflection Left or Right
0
0
1.0
Deflection Front or Rear
0.7086
0.610
0.3346
0.09842
0.4921
0.2342
0.1397
0.06
18
19.5
16.5
11
Feedhole to Bottom of Component
Feedhole to Seating Plane
Defective Unit Clipped Dimension
Lead Wire Enclosure
15.5
8.5
2.5
12.5
5.95
3.55
0.15
—
L1
—
P
0.5079
0.2658
0.1556
0.08
12.9
6.75
3.95
0.20
1.44
0.65
19
Feedhole Pitch
P1
Feedhole Center to Center Lead
First Lead Spacing Dimension
Adhesive Tape Thickness
Overall Taped Package Thickness
Carrier Strip Thickness
P2
T
T1
—
0.0567
0.027
0.7481
0.2841
0.01968
T2
0.014
0.6889
0.2165
.0059
0.35
17.5
5.5
.15
W
Carrier Strip Width
W1
W2
6.3
Adhesive Tape Width
0.5
Adhesive Tape Position
NOTES:
1. Maximum alignment deviation between leads not to be greater than 0.2 mm.
2. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 11 mm.
3. Component lead to tape adhesion must meet the pull test requirements established in Figures 5, 6 and 7.
4. Maximum non–cumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches.
5. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive.
6. No more than 1 consecutive missing component is permitted.
7. A tape trailer and leader, having at least three feed holes is required before the first and after the last component.
8. Splices will not interfere with the sprocket feed holes.
Packaging Specifications
6–6
Motorola Small–Signal Transistors, FETs and Diodes Device Data
TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
FAN FOLD BOX STYLES
ADHESIVE TAPE ON
TOP SIDE
ADHESIVE TAPE ON
TOP SIDE
330 mm
13”
MAX
FLAT SIDE
ROUNDED SIDE
CARRIER
STRIP
CARRIER
STRIP
252 mm
9.92”
MAX
FLAT SIDE OF TRANSISTOR
AND ADHESIVE TAPE VISIBLE.
ROUNDED SIDE OF TRANSISTOR AND
ADHESIVE TAPE VISIBLE.
58 mm
2.28”
MAX
Style M fan fold box is equivalent to styles E and F of
reel pack dependent on feed orientation from box.
Style P fan fold box is equivalent to styles A and B of
reel pack dependent on feed orientation from box.
Figure 2. Style M
Figure 3. Style P
Figure 4. Fan Fold Box Dimensions
ADHESION PULL TESTS
500 GRAM PULL FORCE
70 GRAM
PULL FORCE
100 GRAM
PULL FORCE
16 mm
16 mm
HOLDING
FIXTURE
HOLDING
FIXTURE
HOLDING
FIXTURE
There shall be no deviation in the leads and
no component leads shall be pulled free of
the tape with a 500 gram load applied to the
component body for 3 ± 1 second.
The component shall not pull free with a 300 gram
load applied to the leads for 3 ± 1 second.
The component shall not pull free with a 70 gram
load applied to the leads for 3 ± 1 second.
Figure 5. Test #1
Figure 6. Test #2
Figure 7. Test #3
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Packaging Specifications
6–7
TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
REEL STYLES
CORE DIA.
82mm ± 1mm
ARBOR HOLE DIA.
30.5mm ± 0.25mm
MARKING NOTE
HUB RECESS
76.2mm ± 1mm
RECESS DEPTH
9.5mm MIN
365mm + 3, – 0mm
38.1mm ± 1mm
48 mm
MAX
Material used must not cause deterioration of components or degrade lead solderability
Figure 8. Reel Specifications
ADHESIVE TAPE ON REVERSE SIDE
CARRIER STRIP
ROUNDED
CARRIER STRIP
FLAT SIDE
SIDE
ADHESIVE TAPE
FEED
FEED
Rounded side of transistor and adhesive tape visible.
Flat side of transistor and carrier strip visible
(adhesive tape on reverse side).
Figure 9. Style A
Figure 10. Style B
ADHESIVE TAPE ON REVERSE SIDE
CARRIER STRIP
ROUNDED
SIDE
CARRIER STRIP
FLAT SIDE
ADHESIVE TAPE
FEED
FEED
Flat side of transistor and adhesive tape visible.
Rounded side of transistor and carrier strip visible
(adhesive tape on reverse side).
Figure 11. Style E
Figure 12. Style F
Packaging Specifications
6–8
Motorola Small–Signal Transistors, FETs and Diodes Device Data
INFORMATION FOR USING SURFACE MOUNT PACKAGES
RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection inter-
face between the board and the package. With the correct
pad geometry, the packages will self align when subjected to
a solder reflow process.
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a func-
tion of the drain/collector pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
Although the power dissipation can almost be doubled with
this method, area is taken up on the printed circuit board
which can defeat the purpose of using surface mount
technology. For example, a graph of R
area is shown in Figure 1.
versus drain pad
θJA
mount device is determined by T
junction temperature of the die, R
, the maximum rated
, the thermal resistance
J(max)
θJA
from the device junction to ambient, and the operating
temperature, T . Using the values provided on the data
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad . Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
A
sheet, P can be calculated as follows:
D
T
– T
A
θJA
J(max)
P
=
D
R
160
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
Board Material = 0.0625″
G–10/FR–4, 2 oz Copper
T = 25°C
A
140
120
the equation for an ambient temperature T of 25°C, one can
A
calculate the power dissipation of the device. For example,
0.8 Watts
for a SOT–223 device, P is calculated as follows.
D
150°C – 25°C
156°C/W
1.5 Watts
= 800 milliwatts
P
=
1.25 Watts*
D
100
80
The 156°C/W for the SOT–223 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 800 milliwatts. There
are other alternatives to achieving higher power dissipation
from the surface mount packages. One is to increase the
area of the drain/collector pad. By increasing the area of the
drain/collector pad, the power dissipation can be increased.
*Mounted on the DPAK footprint
0.2 0.4
0.0
0.6
A, AREA (SQUARE INCHES)
0.8
1.0
Figure 1. Thermal Resistance versus Drain Pad
Area for the SOT–223 Package (Typical)
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SOT–23, SC–59, SC–70/SOT–323, SC–90/SOT–416,
SOD–123, SOT–223, SOT–363, SO–14, SO–16, and
TSOP–6 packages, the stencil opening should be the same
as the pad size or a 1:1 registration.
Surface Mount Information
7–10
Motorola Small–Signal Transistors, FETs and Diodes Device Data
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to mini-
mize the thermal stress to which the devices are subjected.
• Always preheat the device.
• The soldering temperature and time should not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used since the use of forced
cooling will increase the temperature gradient and will
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference should be a maximum of 10°C.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones and a figure
for belt speed. Taken together, these control settings make
up a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remem-
bers these profiles from one operating session to the next.
Figure 2 shows a typical heating profile for use when
soldering a surface mount device to a printed circuit board.
This profile will vary among soldering systems, but it is a
good starting point. Factors that can affect the profile include
the type of soldering system in use, density and types of
components on the board, type of solder used, and the type
of board or substrate material being used. This profile shows
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density board.
The Vitronics SMD310 convection/infrared reflow soldering
system was used to generate this profile. The type of solder
used was 62/36/2 Tin Lead Silver with a melting point
between 177–189°C. When this type of furnace is used for
solder reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
STEP 5
STEP 6
VENT
STEP 7
COOLING
STEP 1
STEP 4
STEP 2
VENT
“SOAK”
STEP 3
HEATING
ZONES 4 & 7
“SPIKE”
PREHEAT
ZONE 1
“RAMP”
HEATING
ZONES 3 & 6
“SOAK”
HEATING
ZONES 2 & 5
“RAMP”
205° TO 219°C
PEAK AT
SOLDER JOINT
200°C
170°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160°C
150°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
100°C
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°C
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 2. Typical Solder Heating Profile
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Surface Mount Information
7–11
Footprints for Soldering
0.037
0.95
0.037
0.95
0.037
0.95
0.037
0.95
0.094
2.4
0.079
2.0
0.039
1.0
0.035
0.9
inches
mm
0.031
0.8
inches
0.031
0.8
mm
SC–59
SOT–23
0.025
0.65
0.025
0.65
0.5 min. (3x)
0.075
1.9
0.035
0.9
0.028
0.7
1.4
inches
mm
SC–70/SOT–323
SOT 416/SC–90
0.15
3.8
0.060
1.52
0.079
2.0
0.275
7.0
0.155
4.0
0.248
6.3
0.091
2.3
0.091
2.3
0.079
2.0
0.024
0.6
0.050
1.270
inches
mm
0.059
1.5
0.059
1.5
0.059
1.5
inches
mm
SOT–223
SO–14, SO–16
Surface Mount Information
7–12
Motorola Small–Signal Transistors, FETs and Diodes Device Data
0.5 mm (min)
0.91
0.036
1.22
0.048
2.36
0.093
4.19
mm
inches
0.165
1.9 mm
SOD–123
SOT–363
(SC–70 6 LEAD)
0.094
2.4
0.037
0.95
0.074
1.9
0.037
0.95
0.028
0.7
0.039
1.0
inches
mm
TSOP–6
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Surface Mount Information
7–13
Package Outline Dimensions
Dimensions are in inches unless otherwise noted.
NOTES:
A
B
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
R
4. DIMENSION F APPLIES BETWEEN P AND L.
DIMENSION D AND J APPLY BETWEEN L AND K
MINIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIMENSION K MINIMUM.
P
L
F
SEATING
PLANE
K
INCHES
DIM MIN MAX
MILLIMETERS
MIN
4.45
4.32
3.18
0.41
0.41
1.15
2.42
0.39
MAX
5.20
5.33
4.19
0.55
0.48
1.39
2.66
0.50
–––
A
B
C
D
F
G
H
J
K
L
N
P
0.175
0.170
0.125
0.016
0.016
0.045
0.095
0.015
0.500
0.250
0.080
–––
0.205
0.210
0.165
0.022
0.019
0.055
0.105
0.020
D
X X
G
H
J
V
C
––– 12.70
SECTION X–X
–––
0.105
0.100
–––
6.35
2.04
–––
2.93
3.43
–––
1
2.66
2.54
–––
N
N
R
V
0.115
0.135
–––
–––
STYLE 2:
STYLE 1:
PIN 1. EMITTER
STYLE 3:
STYLE 4:
PIN 1. CATHODE
STYLE 5:
PIN 1. DRAIN
STYLE 7:
PIN 1. SOURCE
PIN 1. BASE
2. EMITTER
3. COLLECTOR
PIN 1. ANODE
2. ANODE
3. CATHODE
2. BASE
3. COLLECTOR
2. CATHODE
3. ANODE
2. SOURCE
3. GATE
2. DRAIN
3. GATE
STYLE 14:
STYLE 15:
STYLE 17:
STYLE 21:
STYLE 22:
STYLE 30:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
PIN 1. COLLECTOR
2. BASE
3. EMITTER
PIN 1. COLLECTOR
2. EMITTER
3. BASE
PIN 1. SOURCE
2. GATE
3. DRAIN
PIN 1. DRAIN
2. GATE
3. SOURCE
CASE 029–04
(TO–226AA) TO–92
PLASTIC
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. DIMENSION F APPLIES BETWEEN P AND L.
DIMENSIONS D AND J APPLY BETWEEN L AND K
MIMIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIMENSION K MINIMUM.
B
R
SEATING
PLANE
P
L
F
K
INCHES
DIM MIN MAX
MILLIMETERS
MIN
4.44
7.37
3.18
0.46
0.41
1.15
2.42
0.46
MAX
5.21
7.87
4.19
0.56
0.48
1.39
2.66
0.61
–––
A
B
C
D
F
G
H
J
K
L
N
P
R
V
0.175
0.290
0.125
0.018
0.016
0.045
0.095
0.018
0.500
0.250
0.080
–––
0.205
0.310
0.165
0.022
0.019
0.055
0.105
0.024
X X
G
D
H
J
V
––– 12.70
–––
0.105
0.100
–––
6.35
2.04
–––
3.43
3.43
–––
SECTION X–X
2.66
2.54
–––
C
1
2
3
N
0.135
0.135
N
–––
–––
STYLE 1:
PIN 1. EMITTER
STYLE 14:
PIN 1. EMITTER
STYLE 22:
PIN 1. SOURCE
2. BASE
3. COLLECTOR
2. COLLECTOR
3. BASE
2. GATE
3. DRAIN
CASE 029–05
(TO–226AE) TO–92
1–WATT PLASTIC
Package Outline Dimensions
8–2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE OUTLINE DIMENSIONS (continued)
B
NOTES:
1. PACKAGE CONTOUR OPTIONAL WITHIN DIA B
AND LENGTH A. HEAT SLUGS, IF ANY, SHALL BE
INCLUDED WITHIN THIS CYLINDER, BUT SHALL
NOT BE SUBJECT TO THE MIN LIMIT OF DIA B.
2. LEAD DIA NOT CONTROLLED IN ZONES F, TO
ALLOW FOR FLASH, LEAD FINISH BUILDUP,
AND MINOR IRREGULARITIES OTHER THAN
HEAT SLUGS.
D
K
F
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
A
B
D
F
5.84
2.16
0.46
–––
7.62 0.230 0.300
2.72 0.085 0.107
0.56 0.018 0.022
F
1.27
––– 0.050
K
25.40 38.10 1.000 1.500
K
All JEDEC dimensions and notes apply.
CASE 51–02
(DO–204AA)
DO–7
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND ZONE R IS
UNCONTROLLED.
4. DIMENSION F APPLIES BETWEEN P AND L.
DIMENSIONS D AND J APPLY BETWEEN L AND K
MINIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIM K MINIMUM.
R
SEATING
PLANE
D
L
P
F
J
K
INCHES
DIM MIN MAX
MILLIMETERS
MIN
4.45
4.32
3.18
0.41
MAX
5.21
5.33
4.49
0.56
0.482
A
B
C
D
F
0.175
0.170
0.125
0.016
0.016
0.205
0.210
0.165
0.022
SECTION X–X
X X
D
G
H
0.019 0.407
G
H
J
K
L
N
P
0.050 BSC
0.100 BSC
0.014 0.016
––– 12.70
1.27 BSC
3.54 BSC
0.36
0.41
–––
–––
2.66
1.27
–––
–––
0.500
0.250
0.080
–––
V
–––
0.105
0.050
–––
6.35
2.03
–––
2.93
3.43
C
R
V
0.115
0.135
–––
1
2
N
N
STYLE 1:
PIN 1. ANODE
2. CATHODE
CASE 182–02
(T0–226AC) TO–92
PLASTIC
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Package Outline Dimensions
8–3
PACKAGE OUTLINE DIMENSIONS (continued)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIUMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
A
L
3
INCHES
DIM MIN MAX
MILLIMETERS
S
C
B
MIN
2.80
1.20
0.89
0.37
1.78
MAX
3.04
1.40
1.11
0.50
2.04
1
2
A
B
C
D
G
H
J
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
V
G
0.0005 0.0040 0.013 0.100
0.0034 0.0070 0.085 0.177
K
L
S
0.0140 0.0285
0.0350 0.0401
0.0830 0.1039
0.0177 0.0236
0.35
0.89
2.10
0.45
0.69
1.02
2.64
0.60
H
J
D
V
K
STYLE 10:
STYLE 11:
PIN 1. ANODE
STYLE 6:
PIN 1. BASE
2. EMITTER
STYLE 8:
STYLE 9:
PIN 1. ANODE
PIN 1. DRAIN
2. SOURCE
3. GATE
PIN 1. ANODE
2. NO CONNECTION
3. CATHODE
2. CATHODE
3. CATHODE–ANODE
2. ANODE
3. CATHODE
3. COLLECTOR
STYLE 12:
STYLE 18:
PIN 1. NO CONNECTION
STYLE 19:
PIN 1. CATHODE
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
PIN 1. CATHODE
2. CATHODE
3. ANODE
2. CATHODE
3. ANODE
2. ANODE
3. CATHODE–ANODE
CASE 318–08
(TO–236AB) SOT–23
PLASTIC
A
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
3
S
B
A
B
C
D
G
H
J
2.70
1.30
1.00
0.35
1.70
0.013
0.09
0.20
1.25
2.50
3.10 0.1063 0.1220
1.70 0.0512 0.0669
1.30 0.0394 0.0511
0.50 0.0138 0.0196
2.10 0.0670 0.0826
0.100 0.0005 0.0040
0.18 0.0034 0.0070
0.60 0.0079 0.0236
1.65 0.0493 0.0649
3.00 0.0985 0.1181
2
1
D
G
K
L
S
J
C
K
H
STYLE 4:
PIN 1. N.C.
STYLE 5:
STYLE 1:
PIN 1. EMITTER
2. BASE
STYLE 2:
PIN 1. N.C.
2. ANODE
3. CATHODE
STYLE 3:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
3. ANODE
2. CATHODE
3. ANODE
2. ANODE
3. CATHODE
3. COLLECTOR
CASE 318D–04
SC–59
Package Outline Dimensions
8–4
Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE OUTLINE DIMENSIONS (continued)
A
F
NOTES:
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
4. CONTROLLING DIMENSION: INCH.
4
INCHES
DIM MIN MAX
MILLIMETERS
S
B
MIN
6.30
3.30
1.50
0.60
2.90
2.20
MAX
6.70
3.70
1.75
0.89
3.20
2.40
0.100
0.35
2.00
1.05
10
1
2
3
A
B
C
D
F
G
H
J
K
L
M
S
0.249
0.130
0.060
0.024
0.115
0.087
0.263
0.145
0.068
0.035
0.126
0.094
D
L
0.0008 0.0040 0.020
G
0.009
0.060
0.033
0
0.014
0.078
0.041
10
0.24
1.50
0.85
0
J
C
0.08 (0003)
0.264
0.287
6.70
7.30
M
H
K
STYLE 1:
PIN 1. BASE
STYLE 2:
PIN 1. ANODE
STYLE 3:
PIN 1. GATE
2. DRAIN
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. CATHODE
3. NC
4. CATHODE
3. SOURCE
4. DRAIN
CASE 318E–04
SOT–223
A
NOTES:
L
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
6
5
2
4
B
S
1
3
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
D
A
B
C
D
G
H
J
K
L
M
S
2.90
1.30
0.90
0.25
0.85
0.013
0.10
0.20
1.25
0
3.10 0.1142 0.1220
1.70 0.0512 0.0669
1.10 0.0354 0.0433
0.50 0.0098 0.0197
1.05 0.0335 0.0413
0.100 0.0005 0.0040
0.26 0.0040 0.0102
0.60 0.0079 0.0236
1.55 0.0493 0.0610
G
M
J
C
0.05 (0.002)
K
10
0
10
H
2.50
3.00 0.0985 0.1181
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
CASE 318G–02
TSOP–6
PLASTIC
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Package Outline Dimensions
8–5
PACKAGE OUTLINE DIMENSIONS (continued)
A
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3
2. CONTROLLING DIMENSION: INCH.
B
S
INCHES
DIM MIN MAX
MILLIMETERS
1
2
MIN
1.80
1.15
0.90
0.30
1.20
0.00
0.10
0.425 REF
0.650 BSC
0.700 REF
0.80
2.00
0.30
MAX
2.20
1.35
1.25
0.40
1.40
0.10
0.25
A
B
C
D
G
H
J
K
L
N
R
S
0.071 0.087
0.045 0.053
0.035 0.049
0.012 0.016
0.047 0.055
0.000 0.004
0.004 0.010
0.017 REF
D
V
G
0.026 BSC
R
J
N
C
0.028 REF
0.031 0.039
0.079 0.087
0.012 0.016
1.00
2.20
0.40
0.05 (0.002)
V
K
H
STYLE 2:
PIN 1. ANODE
2. N.C.
STYLE 3:
PIN 1. BASE
2. EMITTER
STYLE 4:
STYLE 5:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
3. ANODE
2. ANODE
3. CATHODE
3. CATHODE
3. COLLECTOR
STYLE 7:
STYLE 9:
PIN 1. ANODE
STYLE 10:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
PIN 1. CATHODE
2. ANODE
3. ANODE–CATHODE
2. CATHODE
3. CATHODE–ANODE
CASE 419–02
SC–70/SOT–323
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
G
V
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
A
B
C
D
G
H
J
K
N
S
0.071 0.087
0.045 0.053
0.031 0.043
0.004 0.012
0.026 BSC
6
5
4
3
S
–B–
0.65 BSC
1
2
–––
0.004
–––
0.10
0.10
0.10
0.25
0.30
0.004 0.010
0.004 0.012
0.008 REF
0.079 0.087
0.012 0.016
0.20 REF
2.00
0.30
2.20
0.40
M
M
0.2 (0.008)
B
D6 PL
V
STYLE 1:
PIN 1. EMITTER 2
N
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
J
6. COLLECTOR 2
C
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
K
H
6. CATHODE 2
CASE 419B-01
SOT–363
Package Outline Dimensions
8–6
Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE OUTLINE DIMENSIONS (continued)
A
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
H
1
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.40
2.55
0.95
0.50
0.25
0.00
–––
MAX
1.80
2.85
1.35
0.70
–––
0.10
0.15
3.85
A
B
C
D
E
H
J
0.055
0.100
0.037
0.020
0.004
0.000
–––
0.071
0.112
0.053
0.028
–––
0.004
0.006
0.152
K
B
K
0.140
3.55
E
2
STYLE 1:
PIN 1. CATHODE
2. ANODE
J
D
CASE 425–04
SOD–123
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
–A–
S
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
2
A
B
C
D
G
H
J
K
L
S
0.70
1.40
0.60
0.15
0.80 0.028 0.031
1.80 0.055 0.071
0.90 0.024 0.035
0.30 0.006 0.012
3
G
–B–
1
D 3 PL
0.20 (0.008)
1.00 BSC
0.039 BSC
M
B
–––
0.10
1.45
0.10
0.10
––– 0.004
0.20 (0.008) A
0.25 0.004 0.010
1.75 0.057 0.069
0.20 0.004 0.008
K
0.50 BSC
0.020 BSC
STYLE 1:
J
PIN 1. BASE
2. EMITTER
3. COLLECTOR
C
STYLE 4:
L
H
PIN 1. CATHODE
2. CATHODE
3. ANODE
CASE 463–01
SOT–416/SC–90
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Package Outline Dimensions
8–7
PACKAGE OUTLINE DIMENSIONS (continued)
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
14
1
8
7
B
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
A
F
INCHES
DIM MIN MAX
0.770 18.16
MILLIMETERS
MIN
MAX
19.56
6.60
4.69
0.53
1.78
A
B
C
D
F
0.715
0.240
0.145
0.015
0.040
L
0.260
0.185
0.021
0.070
6.10
3.69
0.38
1.02
C
G
H
J
K
L
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
SEATING
PLANE
K
0.300 BSC
7.62 BSC
H
G
D
M
M
N
0
10
0.039
0
0.39
10
1.01
0.015
CASE 646–06
14–PIN DIP
PLASTIC
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
9
8
B
S
1
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
G
H
J
K
L
M
S
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
CASE 648–08
16–PIN DIP
PLASTIC
Package Outline Dimensions
8–8
Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE OUTLINE DIMENSIONS (continued)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
–B–
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
8.75 0.337
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
–T–
SEATING
PLANE
J
M
G
J
K
M
P
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
M
S
S
0.25 (0.010)
T B
A
7
0
5.80
0.25
6.20 0.228
0.50 0.010
0.244
0.019
R
CASE 751A–03
SO–14
PLASTIC
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
CASE 751B–05
SO–16
PLASTIC
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Package Outline Dimensions
8–9
相关型号:
BC557ATA
PNP Epitaxial Silicon Transistor, 3 LD, TO92, MOLDED 0.200 IN LINE SPACING LD FORM, 2000/AMMO
FAIRCHILD
BC557A{AMMOPAK}
Small Signal Bipolar Transistor, 45V V(BR)CEO, 1-Element, PNP, Silicon, TO-92
DIODES
©2020 ICPDF网 联系我们和版权申明