CAT1024SA-42TE13 [ONSEMI]

IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, SOIC-8, Power Management Circuit;


型号：	CAT1024SA-42TE13
厂家：	ONSEMI
描述：	IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, SOIC-8, Power Management Circuit 光电二极管
文件：	总19页 (文件大小：192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT1024, CAT1025

Supervisory Circuits with

I²C Serial 2k-bit CMOS

EEPROM and Manual Reset

Description

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The CAT1024 and CAT1025 are complete memory and supervisory

solutions for microcontroller−based systems. A 2k−bit serial

EEPROM memory and a system power supervisor with brown−out

protection are integrated together in low power CMOS technology.

Memory interface is via a 400 kHz I C bus.

The CAT1025 provides a precision V^CCsense circuit and two open

drain outputs: one (RESET) drives high and the other (RESET) drives

low whenever V^CCfalls below the reset threshold voltage. The

CAT1025 also has a Write Protect input (WP). Write operations are

disabled if WP is connected to a logic high.

PDIP−8

CASE 646AA

TSSOP−8

CASE 948S

SOIC−8

CASE 751BD

The CAT1024 also provides a precision V^CCsense circuit, but has

only a RESET output and does not have a Write Protect input.

All supervisors have a 1.6 second watchdog timer circuit that resets

a system to a known state if software or a hardware glitch halts or

“hangs” the system. For the CAT1024 and CAT1022, the watchdog

timer monitors the SDA signal. The CAT1023 has a separate watchdog

timer interrupt input pin, WDI.

MSOP−8

CASE 846AD

TDFN−8

CASE 511AL

ORDERING INFORMATION

For Ordering Information details, see page 13.

The power supply monitor and reset circuit protect memory and

system controllers during power up/down and against brownout

conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V

systems. If power supply voltages are out of tolerance reset signals

become active, preventing the system microcontroller, ASIC or

peripherals from operating. Reset signals become inactive typically

200 ms after the supply voltage exceeds the reset threshold level. With

both active high and low reset signals, interface to microcontrollers

and other ICs is simple. In addition, the RESET pin or a separate input,

MR, can be used as an input for push−button manual reset capability.

The CAT1024/25 memory features a 16−byte page. In addition,

hardware data protection is provided by a V^CCsense circuit that

prevents writes to memory whenever V^CCfalls below the reset

threshold or until V^CCreaches the reset threshold during power up.

Available packages include an 8−pin PDIP and a surface mount

8−pin SO, 8−pin TSSOP, 8−pin TDFN and 8−pin MSOP packages.

The TDFN package thickness is 0.8 mm maximum. TDFN footprint is

3 x 3 mm.

Features

• Precision Power Supply Voltage Monitor

• Built−in Inadvertent Write Protection

♦ WP Pin (CAT1025)

♦ 5 V, 3.3 V and 3 V Systems

♦ Five Threshold Voltage Options

• 1,000,000 Program/Erase Cycles

• Manual Reset Input

• Active High or Low Reset

♦ Valid Reset Guaranteed at VCC = 1 V

• 100 Year Data Retention

• 400 kHz I C Bus

• Industrial and Extended Temperature Ranges

• Green Packages Available with NiPdAu Lead Finished

• 2.7 V to 5.5 V Operation

• Low Power CMOS Technology

• 16−Byte Page Write Buffer

• These Devices are Pb−Free, Halogen Free/BFR Free

and are RoHS Compliant

Publication Order Number:

November, 2011 − Rev. 20

CAT1024/D

CAT1024, CAT1025

Table 1. THRESHOLD VOLTAGE OPTION

Part Dash

Number

Minimum

Threshold

Maximum

Threshold

−45

−42

−30

−28

−25

4.50

4.25

3.00

2.85

2.55

4.75

4.50

3.15

3.00

2.70

BLOCK DIAGRAM

EXTERNAL LOAD

SENSEAMPS

SHIFT REGISTERS

OUT

ACK

WORDADDRESS

BUFFERS

COLUMN

DECODERS

START/STOP

SDA

WP*

LOGIC

2kbit

EEPROM

XDEC

CONTROL

LOGIC

DATA IN STORAGE

HIGHVOLTAGE/

TIMING CONTROL

RESET Controller

STATE COUNTERS

SCL

Precision

SLAVE

ADDRESS

Vcc Monitor

COMPARATORS

RESET* RESET

*CAT1025 Only

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CAT1024, CAT1025

PIN CONFIGURATION

DIP Package (L)

SOIC Package (W)

TSSOP Package (Y)

MSOP Package (Z)

(Bottom View)

TDFN Package: 3 mm x 3 mm

0.8mm maximum height − (ZD4)

RESET

CAT1024

CAT1025

CAT1024

CAT1025

SCL

SDA

SCL

SDA

RESET

WDI

SCL

SDA

SCL

SDA

PIN DESCRIPTION

RESET/RESET: RESET OUTPUTs

(RESET CAT1025 Only)

Table 2. PIN FUNCTION

Pin Name

Function

These are open drain pins and RESET can be used as a

manual reset trigger input. By forcing a reset condition on

the pin the device will initiate and maintain a reset condition.

The RESET pin must be connected through a pull−down

resistor, and the RESET pin must be connected through a

pull−up resistor.

No Connect

RESET

Active Low Reset Input/Output

Ground

SDA

SCL

Serial Data/Address

Clock Input

SDA: SERIAL DATA ADDRESS

RESET

Active High Reset Output

(CAT1025 Only)

The bidirectional serial data/address pin is used to transfer

all data into and out of the device. The SDA pin is an open

drain output and can be wire−ORed with other open drain or

open collector outputs.

Power Supply

Write Protect (CAT1025 Only)

Manual Reset Input

SCL: SERIAL CLOCK

Serial clock input.

MR: MANUAL RESET INPUT

Table 3. OPERATING TEMPERATURE RANGE

Manual Reset input is a debounced input that can be

connected to an external source for Manual Reset. Pulling

the MR input low will generate a Reset condition. Reset

outputs are active while MR input is low and for the reset

timeout period after MR returns to high. The input has an

internal pull up resistor.

Industrial

Extended

−40°C to 85°C

−40°C to 125°C

WP (CAT1025 Only): WRITE PROTECT INPUT

When WP input is tied to V^SSor left unconnected write

operations to the entire array are allowed. When tied to V^CC,

the entire array is protected. This input has an internal pull

down resistor.

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CAT1024, CAT1025

Table 4. CAT102X FAMILY OVERVIEW

Device

Manual Reset

Input Pin

Watchdog

Monitor Pin

Write

Protection

Independent

Auxiliary Voltage

Sense

RESET:

Active High

and LOW

EEPROM

CAT1021

CAT1022

CAT1023

CAT1024

CAT1025

CAT1026

CAT1027

SDA

WDI

NOTE: For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets.

SPECIFICATIONS

Table 5. ABSOLUTE MAXIMUM RATINGS

Parameters

Ratings

Units

°C

Temperature Under Bias

Storage Temperature

–55 to +125

–65 to +150

Voltage on any Pin with Respect to Ground (Note 1)

with Respect to Ground

−2.0 to V + 2.0

−2.0 to 7.0

1.0

Package Power Dissipation Capability (T = 25°C)

Lead Soldering Temperature (10 s)

Output Short Circuit Current (Note 2)

300

°C

100

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum

DC voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns.

2. Output shorted for no more than one second. No more than one output shorted at a time.

Table 6. D.C. OPERATING CHARACTERISTICS

= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.

Symbol

Parameter

Input Leakage Current

Test Conditions

Min

−2

Typ

Max

Units

= GND to V

Output Leakage Current

−10

Power Supply Current (Write)

= 400 kHz

= 5.5 V

CC1

SCL

Power Supply Current (Read)

Standby Current

= 400 kHz

= 5.5 V

CC2

SCL

= 5.5 V

= GND or V

(Note 3)

Input Low Voltage

Input High Voltage

−0.5

0.3 x V

0.7 x V

+ 0.5

Output Low Voltage

(SDA, RESET)

= 3 mA

0.4

= 2.7 V

Output High Voltage

(RESET)

= −0.4 mA

V − 0.75

= 2.7 V

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CAT1024, CAT1025

Table 6. D.C. OPERATING CHARACTERISTICS

= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.

Symbol

Parameter

Reset Threshold

Test Conditions

Min

Typ

Max

Units

CAT102x−45

4.50

4.75

(V = 5.0 V)

CAT102x−42

4.25

3.00

2.85

2.55

4.50

3.15

3.00

2.70

(V = 5.0 V)

CAT102x−30

(V = 3.3 V)

CAT102x−28

(V = 3.3 V)

CAT102x−25

(V = 3.0 V)

Reset Output Valid V Voltage

1.00

RVALID

(Note 4)

Reset Threshold Hysteresis

3. V min and V max are reference values only and are not tested.

4. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.

Table 7. CAPACITANCE

T = 25°C, f = 1.0 MHz, V = 5 V

Symbol

(Note 5)

Test

Test Conditions

= 0 V

OUT

Max

Units

Output Capacitance

Input Capacitance

OUT

(Note 5)

= 0 V

Table 8. AC CHARACTERISTICS

= 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.

Memory Read & Write Cycle (Note 6)

Symbol

Parameter

Min

Max

400

100

Units

kHz

Clock Frequency

SCL

Input Filter Spike Suppression (SDA, SCL)

Clock Low Period

1.3

0.6

LOW

Clock High Period

HIGH

(Note 5)

SDA and SCL Rise Time

300

t (Note 5)

SDA and SCL Fall Time

Start Condition Hold Time

0.6

HD; STA

Start Condition Setup Time (for a Repeated Start)

Data Input Hold Time

SU; STA

HD; DAT

Data Input Setup Time

100

0.6

SU; DAT

SU; STO

Stop Condition Setup Time

SCL Low to Data Out Valid

900

Data Out Hold Time

(Note 5)

(Note 7)

Time the Bus must be Free Before a New Transmission Can Start

Write Cycle Time (Byte or Page)

1.3

BUF

5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

6. Test Conditions according to “AC Test Conditions” table.

7. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the

write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.

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CAT1024, CAT1025

Table 9. RESET CIRCUIT AC CHARACTERISTICS

Symbol

Parameter

Test Conditions

Min

Typ

Max

270

Units

Power−Up Reset Timeout

Note 2

Note 3

130

200

PURST

to RESET output Delay

Glitch Reject Pulse Width

RDP

Notes 4 and 5

Note 1

GLITCH

MR Glitch

Manual Reset Glitch Immunity

MR Pulse Width

100

Note 1

MRW

MR Input to RESET Output Delay

Note 1

MRD

Table 10. POWER−UP TIMING (Notes 5 and 6)

Symbol

Parameter

Power−Up to Read Operation

Power−Up to Write Operation

Test Conditions

Min

Typ

Max

270

Units

PUR

PUW

Table 11. AC TEST CONDITIONS

Parameter

Test Conditions

Input Pulse Voltages

0.2 x V to 0.8 x V

Input Rise and Fall Times

Input Reference Voltages

Output Reference Voltages

Output Load

10 ns

0.3 x V , 0.7 x V

0.5 x V

Current Source: I = 3 mA; C = 100 pF

Table 12. RELIABILITY CHARACTERISTICS

Symbol

(Note 5)

Parameter

Endurance

Reference Test Method

Min

1,000,000

100

Max

Units

MIL−STD−883, Test Method 1033

MIL−STD−883, Test Method 1008

MIL−STD−883, Test Method 3015

JEDEC Standard 17

Cycles/Byte

Years

END

(Note 5)

Data Retention

ESD Susceptibility

2000

Volts

ZAP

(Notes 5 & 7) Latch−Up

100

LTH

1. Test Conditions according to “AC Test Conditions” table.

2. Power−up, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

3. Power−Down, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

4. V Glitch Reference Voltage = V

; Based on characterization data

THmin

5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

6. t

and t

are the delays required from the time V is stable until the specified memory operation can be initiated.

PUR

PUW CC

7. Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to V + 1 V.

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CAT1024, CAT1025

DEVICE OPERATON

Reset Controller Description

Hardware Data Protection

The CAT1024/25 precision RESET controllers ensure

correct system operation during brownout and power

up/down conditions. They are configured with open drain

RESET outputs.

During power−up, the RESET outputs remain active until

V^CCreaches the VTH threshold and will continue driving the

outputs for approximately 200 ms (t^PURST) after reaching

V^TH. After the tPURST timeout interval, the device will cease

to drive the reset outputs. At this point the reset outputs will

be pulled up or down by their respective pull up/down

resistors.

During power−down, the RESET outputs will be active

when V^CCfalls below VTH. The RESET output will be valid

so long as V^CCis > 1.0 V (VRVALID). The device is designed

to ignore the fast negative going V^CCtransient pulses

(glitches).

The CAT1024/25 supervisors have been designed to solve

many of the data corruption issues that have long been

associated with serial EEPROMs. Data corruption occurs

when incorrect data is stored in a memory location which is

assumed to hold correct data.

Whenever the device is in a Reset condition, the

embedded EEPROM is disabled for all operations,

including write operations. If the Reset output(s) are active,

in progress communications to the EEPROM are aborted

and no new communications are allowed. In this condition

an internal write cycle to the memory can not be started, but

an in progress internal nonvolatile memory write cycle can

not be aborted. An internal write cycle initiated before the

Reset condition can be successfully finished if there is

enough time (5ms) before V^CCreaches the minimum value

of 2 V.

Reset output timing is shown in Figure 1.

In addition, the CAT1025 includes a Write Protection

Input which when tied to V^CCwill disable any write

operations to the device.

Manual Reset Operation

The RESET pin can operate as reset output and manual

reset input. The input is edge triggered; that is, the RESET

input will initiate a reset timeout after detecting a high to low

transition.

When RESET I/O is driven to the active state, the 200 ms

timer will begin to time the reset interval. If external reset is

shorter than 200 ms, Reset outputs will remain active at least

200 ms.

The CAT1024/25 also have a separate manual reset input.

Driving the MR input low by connecting a pushbutton

(normally open) from MR pin to GND will generate a reset

condition. The input has an internal pull up resistor.

Reset remains asserted while MR is low and for the Reset

Timeout period after MR input has gone high.

Glitches shorter than 100 ns on MR input will not generate

a reset pulse. No external debouncing circuits are required.

Manual reset operation using MR input is shown in Figure 2.

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L D

CAT1024, CAT1025

t_GLITCH

V_TH

t_RPD

t_PUR

V_CC

t_RPD

t_PUR

RESEꢀT

RESET

Figure 1. RESET Output Timing

t_MRW

t_MRD

t_PURST

RESET

Figure 2. MR Operation and Timing

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8TH B

ACK

CAT1024, CAT1025

EMBEDDED EEPROM OPERATON

The CAT1024 and CAT1025 feature a 2−kbit embedded

serial EEPROM that supports the I C Bus data transmission

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

protocol. This Inter−Integrated Circuit Bus protocol defines

any device that sends data to the bus to be a transmitter and

any device receiving data to be a receiver. The transfer is

controlled by the Master device which generates the serial

clock and all START and STOP conditions for bus access.

Both the Master device and Slave device can operate as

either transmitter or receiver, but the Master device controls

which mode is activated.

changes in the data line while the clock line is high

will be interpreted as a START or STOP condition.

Start Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The CAT1024/25 monitors the SDA

and SCL lines and will not respond until this condition is

met.

I²C Bus Protocol

The features of the I C bus protocol are defined as

Stop Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

follows:

1. Data transfer may be initiated only when the bus is

not busy.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition. The Master sends the address of the particular

slave device it is requesting. The four most significant bits

of the 8−bit slave address are programmable in metal and the

default is 1010.

The last bit of the slave address specifies whether a Read

or Write operation is to be performed. When this bit is set to

1, a Read operation is selected, and when set to 0, a Write

operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT1024/25 monitors the bus and

responds with an acknowledge (on the SDA line) when its

address matches the transmitted slave address. The

CAT1024/25 then perform a Read or Write operation

depending on the R/W bit.

HIGH

LOW

SCL

HD:DAT

SU:STA

HD:STA

SU:DAT

SU:STO

SDA IN

BUF

SDA OUT

Figure 3. Bus Timing

SCL

SDA

BYTE n

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 4. Write Cycle Timing

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CAT1024, CAT1025

ACKNOWLEDGE

After a successful data transfer, each receiving device is

When the CAT1024/25 begins a READ mode it transmits

8 bits of data, releases the SDA line and monitors the line for

an acknowledge. Once it receives this acknowledge, the

CAT1024/25 will continue to transmit data. If no

acknowledge is sent by the Master, the device terminates

data transmission and waits for a STOP condition.

required to generate an acknowledge. The acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data.

The CAT1024/25 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

responds with an acknowledge after receiving each 8−bit

byte.

WRITE OPERATIONS

Byte Write

Master device transmits the data to be written into the

addressed memory location. The CAT1024/25

acknowledges once more and the Master generates the

STOP condition. At this time, the device begins an internal

programming cycle to non−volatile memory. While the

cycle is in progress, the device will not respond to any

request from the Master device.

In the Byte Write mode, the Master device sends the

START condition and the slave address information (with

the R/W bit set to zero) to the Slave device. After the Slave

generates an acknowledge, the Master sends a 8−bit address

that is to be written into the address pointers of the device.

After receiving another acknowledge from the Slave, the

SDA

SCL

START BIT

STOP BIT

Figure 5. Start/Stop Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 6. Acknowledge Timing

Default Configuration

R/W

Figure 7. Slave Address Bits

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CAT1024, CAT1025

Page Write

The CAT1024/25 writes up to 16 bytes of data in a single

write cycle, using the Page Write operation. The page write

operation is initiated in the same manner as the byte write

operation, however instead of terminating after the initial

byte is transmitted, the Master is allowed to send up to 15

additional bytes. After each byte has been transmitted, the

CAT1024/25 will respond with an acknowledge and

internally increment the lower order address bits by one. The

high order bits remain unchanged.

If the Master transmits more than 16 bytes before sending

the STOP condition, the address counter ‘wraps around,’

and previously transmitted data will be overwritten.

When all 16 bytes are received, and the STOP condition

has been sent by the Master, the internal programming cycle

begins. At this point, all received data is written to the

CAT1024/25 in a single write cycle.

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS

DATA

SDA LINE

Figure 8. Byte Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

DATAꢁn

DATA nꢀ+ꢀ1

DATA n+15

SDA LINE

Figure 9. Page Write Timing

Acknowledge Polling

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is issued

to indicate the end of the host’s write operation, the

CAT1024/25 initiates the internal write cycle. ACK polling

can be initiated immediately. This involves issuing the start

condition followed by the slave address for a write

operation. If the device is still busy with the write operation,

no ACK will be returned. If a write operation has completed,

an ACK will be returned and the host can then proceed with

the next read or write operation.

WRITE PROTECTION PIN (WP)

The Write Protection feature (CAT1025 only) allows the

user to protect against inadvertent memory array

programming. If the WP pin is tied to V^CC, the entire

memory array is protected and becomes read only. The

CAT1025 will accept both slave and byte addresses, but the

memory location accessed is protected from programming

by the device’s failure to send an acknowledge after the first

byte of data is received.

READ OPERATIONS

The READ operation for the CAT1024/25 is initiated in

the same manner as the write operation with one exception,

the R/W bit is set to one. Three different READ operations

are possible: Immediate/Current Address READ,

Selective/Random READ and Sequential READ.

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CAT1024, CAT1025

BUS ꢀACTIVITꢀY:

MASTER

SLꢀAVE

ADDRESS

SDꢀA LINE

DATA

SCꢀL

SDꢀAꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂ8TH BIꢀT

DATA OUꢀT

NO ACK

STOP

Figure 10. Immediate Address Read Timing

Immediate/Current Address Read

again, this time with the R/W bit set to one. The CAT1024

and CAT1025 then responds with its acknowledge and sends

the 8−bit byte requested. The master device does not send an

acknowledge but will generate a STOP condition.

The CAT1024 and CAT1025 address counter contains the

address of the last byte accessed, incremented by one. In

other words, if the last READ or WRITE access was to

address N, the READ immediately following would access

data from address N + 1. For N = E = 255, the counter will

wrap around to zero and continue to clock out valid data.

After the CAT1024/1025 receives its slave address

information (with the R/W bit set to one), it issues an

acknowledge, then transmits the 8−bit byte requested. The

master device does not send an acknowledge, but will

generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by either

the Immediate Address READ or Selective READ

operations. After the CAT1024 and CAT1025 sends the

initial 8− bit byte requested, the Master will responds with

an acknowledge which tells the device it requires more data.

The CAT1024 and CAT1025 will continue to output an 8−bit

byte for each acknowledge, thus sending the STOP

condition.

Selective/Random Read

Selective/Random READ operations allow the Master

device to select at random any memory location for a READ

operation. The Master device first performs a ‘dummy’

write operation by sending the START condition, slave

address and byte addresses of the location it wishes to read.

After the CAT1024 and CAT1025 acknowledges, the Master

device sends the START condition and the slave address

The data being transmitted from the CAT1024 and

CAT1025 is sent sequentially with the data from address N

followed by data from address N + 1. The READ operation

address counter increments all of the CAT1024 and

CAT1025 address bits so that the entire memory array can

be read during one operation.

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

SLAVE

ADDRESS

SDA LINE

DATA n

Figure 11. Selective Read Timing

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CAT1024, CAT1025

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA n

DATA n+1

DATA n+2

DATA n+x

SDA LINE

Figure 12. Sequential Read Timing

ORDERING INFORMATION

Orderable Part Numbers − CAT1024 Series

(See Notes 1 − 5)

Device

Reset Threshold

4.50 V − 4.75 V

4.25 V − 4.50 V

3.00 V − 3.15 V

2.85 V − 3.00 V

2.55 V − 2.70 V

4.50 V − 4.75 V

4.25 V − 4.50 V

3.00 V − 3.15 V

2.85 V − 3.00 V

2.55 V − 2.70 V

4.50 V − 4.75 V

4.25 V − 4.50 V

3.00 V − 3.15 V

2.85 V − 3.00 V

2.55 V − 2.70 V

4.50 V − 4.75 V

4.25 V − 4.50 V

3.00 V − 3.15 V

2.85 V − 3.00 V

2.55 V − 2.70 V

4.50 V − 4.75 V

4.25 V − 4.50 V

3.00 V − 3.15 V

2.85 V − 3.00 V

2.55 V − 2.70 V

Package

Shipping

CAT1024LI−45−G

CAT1024LI−42−G

CAT1024LI−30−G

PDIP

CAT1024LI−28−G

CAT1024LI−25−G

CAT1024WI−45−GT3

CAT1024WI−42−GT3

CAT1024WI−30−GT3

CAT1024WI−28−GT3

CAT1024WI−25−GT3

CAT1024YI−45−GT3

CAT1024YI−42−GT3

CAT1024YI−30−GT3

CAT1024YI−28−GT3

CAT1024YI−25−GT3

CAT1024ZI−45−GT3

CAT1024ZI−42−GT3

CAT1024ZI−30−GT3

CAT1024ZI−28−GT3

CAT1024ZI−25−GT3

CAT1024ZD4I−45T3*

CAT1024ZD4I−42T3*

CAT1024ZD4I−30T3*

CAT1024ZD4I−28T3*

CAT1024ZD4I−25T3*

SOIC

TSSOP

MSOP

TDFN

3000 Tape & Reel

1. All packages are RoHS−compliant (Lead−free, Halogen−free).

2. The standard lead finish is NiPdAu.

3. For additional package and temperature options, please contact your nearest

ON Semiconductor Sales office.

4. TDFN not available in NiPdAu (–G) version.

5. For detailed information and a breakdown of device nomenclature and numbering

systems, please see the ON Semiconductor Device Nomenclature document,

TND310/D, available at www.onsemi.com

http://onsemi.com

CAT1024, CAT1025

Orderable Part Numbers − CAT1025 Series

(See Notes 1 − 5)

Device

Reset Threshold

4.50 V − 4.75 V

4.25 V − 4.50 V

3.00 V − 3.15 V

2.85 V − 3.00 V

2.55 V − 2.70 V

4.50 V − 4.75 V

4.25 V − 4.50 V

3.00 V − 3.15 V

2.85 V − 3.00 V

2.55 V − 2.70 V

4.50 V − 4.75 V

4.25 V − 4.50 V

3.00 V − 3.15 V

2.85 V − 3.00 V

2.55 V − 2.70 V

4.50 V − 4.75 V

4.25 V − 4.50 V

3.00 V − 3.15 V

2.85 V − 3.00 V

2.55 V − 2.70 V

4.50 V − 4.75 V

4.25 V − 4.50 V

3.00 V − 3.15 V

2.85 V − 3.00 V

2.55 V − 2.70 V

Package

Shipping

CAT1025LI−45−G

CAT1025LI−42−G

CAT1025LI−30−G

PDIP

CAT1025LI−28−G

CAT1025LI−25−G

CAT1025WI−45−GT3

CAT1025WI−42−GT3

CAT1025WI−30−GT3

CAT1025WI−28−GT3

CAT1025WI−25−GT3

CAT1025YI−45−GT3

CAT1025YI−42−GT3

CAT1025YI−30−GT3

CAT1025YI−28−GT3

CAT1025YI−25−GT3

CAT1025ZI−45−GT3

CAT1025ZI−42−GT3

CAT1025ZI−30−GT3

CAT1025ZI−28−GT3

CAT1025ZI−25−GT3

CAT1025ZD4I−45T3*

CAT1025ZD4I−42T3*

CAT1025ZD4I−30T3*

CAT1025ZD4I−28T3*

CAT1025ZD4I−25T3*

SOIC

TSSOP

MSOP

TDFN

3000 Tape & Reel

1. All packages are RoHS−compliant (Lead−free, Halogen−free).

2. The standard lead finish is NiPdAu.

3. For additional package and temperature options, please contact your nearest

ON Semiconductor Sales office.

4. TDFN not available in NiPdAu (–G) version.

5. For detailed information and a breakdown of device nomenclature and numbering

systems, please see the ON Semiconductor Device Nomenclature document,

TND310/D, available at www.onsemi.com

http://onsemi.com

CAT1024, CAT1025

PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

SYMBOL

MIN

NOM

MAX

1.35

1.75

0.10

0.33

0.19

0.25

0.51

0.25

4.80

5.80

3.80

5.00

6.20

4.00

1.27 BSC

0.25

0.40

0º

0.50

1.27

8º

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

http://onsemi.com

CAT1024, CAT1025

PDIP−8, 300 mils

CASE 646AA−01

ISSUE A

SYMBOL

MIN

NOM

MAX

5.33

0.38

2.92

0.36

3.30

0.46

1.52

0.25

9.27

4.95

0.56

1.78

0.36

10.16

1.14

0.20

9.02

7.62

6.10

7.87

6.35

8.25

7.11

2.54 BSC

7.87

2.92

10.92

3.80

PIN # 1

IDENTIFICATION

3.30

TOP VIEW

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MS-001.

http://onsemi.com

CAT1024, CAT1025

MSOP 8, 3x3

CASE 846AD−01

ISSUE O

SYMBOL

MIN

NOM

MAX

1.10

0.15

0.95

0.38

0.23

3.10

5.00

3.10

0.05

0.75

0.22

0.13

2.90

4.80

2.90

0.10

0.85

3.00

4.90

3.00

0.65 BSC

0.60

0.40

0.80

0.95 REF

0.25 BSC

0º

6º

TOP VIEW

DETAIL A

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-187.

DETAIL A

http://onsemi.com

CAT1024, CAT1025

TDFN8, 3x3

CASE 511AL−01

ISSUE A

PIN#1 ID

PIN#1 INDEX AREA

TOP VIEW

SIDE VIEW

BOTTOM VIEW

SYMBOL

MIN

0.70

0.00

NOM

MAX

0.80

0.05

0.75

0.02

0.20 REF

0.30

0.23

2.90

2.20

2.90

1.40

0.37

3.10

2.50

3.10

1.80

3.00

−−−

3.00

FRONT VIEW

−−−

0.65 TYP

0.30

0.20

0.40

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MO-229.

http://onsemi.com

CAT1024, CAT1025

TSSOP−8

CASE 948S−01

ISSUE C

8x K REF

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

0.10 (0.004)

T U

0.20 (0.008) T U

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

2X L/2

−U−

PIN 1

IDENT

0.20 (0.008) T U

SECTION N−N

−V−

MILLIMETERS

INCHES

MIN

0.114

DIM MIN

MAX

0.122

0.177

0.043

0.006

0.028

2.90

4.30

---

3.10

−W−

4.50 0.169

1.10 ---

0.076 (0.003)

0.05

0.50

0.15 0.002

0.70 0.020

DETAIL E

SEATING

−T−

0.65 BSC

0.026 BSC

PLANE

0.09

0.19

0.20 0.004

0.16 0.004

0.30 0.007

0.25 0.007

0.008

0.006

0.012

0.010

0.25 (0.010)

6.40 BSC

0.252 BSC

DETAIL E

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

CAT1024/D

http://onsemi.com

CAT1024SA-42TE13 [ONSEMI]

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