CAT5112VI50GT3 [ONSEMI]
32âtap Digital Potentiometer (POT); 32A ????抽头数字电位器（ POT ）
| 型号： | CAT5112VI50GT3 |
| 厂家： | 
ONSEMI |
| 描述： | 32âtap Digital Potentiometer (POT) |
| 文件： | 总10页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT5112
32‐tap Digital
Potentiometer (POT)
with Buffered Wiper
Description
The CAT5112 is a single digital POT designed as an electronic
replacement for mechanical potentiometers. Ideal for automated
adjustments on high volume production lines, they are also well suited
for applications where equipment requiring periodic adjustment is
either difficult to access or located in a hazardous or remote
environment.
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SOIC−8
V SUFFIX
MSOP−8
Z SUFFIX
The CAT5112 contains a 32-tap series resistor array connected
CASE 751BD
CASE 846AD
between two terminals R and R . An up/down counter and decoder
H
L
that are controlled by three input pins, determines which tap is
connected to the wiper, R . The CAT5112 wiper is buffered by an op
WB
amp that operates rail to rail. The wiper setting, stored in non-volatile
memory, is not lost when the device is powered down and is
automatically recalled when power is returned. The wiper can be
adjusted to test new system values without effecting the stored setting.
Wiper-control of the CAT5112 is accomplished with three input
control pins, CS, U/D, and INC. The INC input increments the wiper
in the direction which is determined by the logic state of the U/D input.
The CS input is used to select the device and also store the wiper
position prior to power down.
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATIONS
1
V
CC
INC
U/D
CS
The digital POT can be used as a buffered voltage divider. For
applications where the potentiometer is used as a 2-terminal variable
resistor, please refer to the CAT5114. The buffered wiper of the
CAT5112 is not compatible with that application.
R
R
GND
L
H
R
WB
PDIP (L), SOIC (V), MSOP (Z)
1
R
CS
L
Features
V
CC
INC
U/D
R
WB
GND
32-position Linear Taper Potentiometer
Non-volatile EEPROM Wiper Storage; Buffered Wiper
Low Power CMOS Technology
R
H
TSSOP (Y)
(Top Views)
Single Supply Operation: 2.5 V − 6.0 V
Increment Up/Down Serial Interface
PIN FUNCTION
Resistance Values: 10 kW, 50 kW and 100 kW
Available in PDIP, SOIC, TSSOP and MSOP Packages
Pin Name
INC
Function
Increment Control
Up/Down Control
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
U/D
Compliant
R
Potentiometer High Terminal
Ground
H
Applications
GND
Automated Product Calibration
Remote Control Adjustments
Offset, Gain and Zero Control
Tamper-proof Calibrations
Contrast, Brightness and Volume Controls
Motor Controls and Feedback Systems
Programmable Analog Functions
R
Buffered Wiper Terminal
Potentiometer Low Terminal
Chip Select
WB
R
L
CS
V
Supply Voltage
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
June, 2013 − Rev. 16
CAT5112/D
CAT5112
R
H
V
CC
R
H
U/D
Control
and
+
–
INC
CS
+
–
R
R
WB
Memory
R
R
WB
Power On Recall
GND
L
L
Figure 1. Functional Diagram
Figure 2. Electronic Potentiometer Implementation
Pin Description
Device Operation
The CAT5112 operates like a digitally controlled
potentiometer with R and R equivalent to the high and low
INC: Increment Control Input
H
L
The INC input (on the falling edge) moves the wiper in the
up or down direction determined by the condition of the U/D
input.
terminals and
R
WB
equivalent to the mechanical
potentiometer’s wiper. There are 32 available tap positions
including the resistor end points, R and R . There are 31
resistor elements connected in series between the R and R
H
L
U/D: Up/Down Control Input
H
L
The U/D input controls the direction of the wiper movement.
When in a high state and CS is low, any high−to−low
transition on INC will cause the wiper to move one
terminals. The wiper terminal is connected to one of the 32
taps and controlled by three inputs, INC, U/D and CS. These
inputs control a five-bit up/down counter whose output is
decoded to select the wiper position. The selected wiper
position can be stored in nonvolatile memory using the INC
and CS inputs.
increment toward the R terminal. When in a low state and
H
CS is low, any high-to-low transition on INC will cause the
wiper to move one increment towards the R terminal.
L
With CS set LOW the CAT5112 is selected and will
respond to the U/D and INC inputs. HIGH to LOW
transitions on INC will increment or decrement the wiper
(depending on the state of the U/D input and five-bit
counter). The wiper, when at either fixed terminal, acts like
its mechanical equivalent and does not move beyond the last
position. The value of the counter is stored in nonvolatile
memory whenever CS transitions HIGH while the INC input
is also HIGH. When the CAT5112 is powered-down, the last
stored wiper counter position is maintained in the
nonvolatile memory. When power is restored, the contents
of the memory are recalled and the counter is set to the value
stored.
R : High End Potentiometer Terminal
H
R
H
is the high end terminal of the potentiometer. It is not
required that this terminal be connected to a potential greater
than the R terminal. Voltage applied to the R terminal
L
H
cannot exceed the supply voltage, V or go below ground,
CC
GND.
R : Wiper Potentiometer Terminal (Buffered)
WB
R
WB
is the buffered wiper terminal of the potentiometer. Its
position on the resistor array is controlled by the control
inputs, INC, U/D and CS.
R : Low End Potentiometer Terminal
L
R is the low end terminal of the potentiometer. It is not
L
With INC set low, the CAT5112 may be deselected and
powered down without storing the current wiper position in
nonvolatile memory. This allows the system to always
power up to a preset value stored in nonvolatile memory.
required that this terminal be connected to a potential less
than the R terminal. Voltage applied to the R terminal
H
L
cannot exceed the supply voltage, V or go below ground,
CC
GND. R and R are electrically interchangeable.
L
H
CS: Chip Select
The chip select input is used to activate the control input of
the CAT5112 and is active low. When in a high state, activity
on the INC and U/D inputs will not affect or change the
position of the wiper.
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2
CAT5112
Table 1. OPERATION MODES
INC
High to Low
High to Low
High
CS
Low
U/D
High
Low
X
Operation
Wiper toward R
H
Low
Wiper toward R
L
Low to High
Low to High
High
Store Wiper Position
No Store, Return to Standby
Standby
Low
X
X
X
R
H
C
H
R
WI
R
WB
C
W
C
L
R
L
Figure 3. Potentiometer Equivalent Circuit
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Supply Voltage
V
V
to GND
−0.5 to +7
CC
Inputs
V
CS to GND
INC to GND
U/D to GND
−0.5 to V +0.5
CC
−0.5 to V +0.5
V
V
CC
−0.5 to V +0.5
CC
R
to GND
−0.5 to V +0.5
V
H
CC
R to GND
L
−0.5 to V +0.5
V
CC
R
WB
to GND
−0.5 to V +0.5
V
CC
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix)
C
0 to 70
−40 to +85
+150
Industrial (‘I’ suffix)
Junction Temperature
Storage Temperature
Lead Soldering (10 s max)
C
C
C
C
−65 to +150
+300
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
(Note 1)
Parameter
ESD Susceptibility
Latch-Up
Test Method
Min
2000
Typ
Max
Units
V
V
MIL−STD−883, Test Method 3015
JEDEC Standard 17
ZAP
I
(Notes 1, 2)
100
mA
LTH
T
Data Retention
Endurance
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 1003
100
Years
Stores
DR
N
1,000,000
END
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V + 1 V
CC
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3
CAT5112
Table 4. DC ELECTRICAL CHARACTERISTICS (V = +2.5 V to +6 V unless otherwise specified)
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER SUPPLY
V
I
Operating Voltage Range
Supply Current (Increment)
2.5
–
–
–
6
V
CC
V
V
= 6 V, f = 1 MHz, I = 0
200
100
1000
500
150
mA
mA
mA
mA
mA
CC1
CC2
CC
W
= 6 V, f = 250 kHz, I = 0
–
–
CC
W
I
Supply Current (Write)
Programming, V = 6 V
–
–
CC
V
CC
= 3 V
–
–
I
(Note 4)
Supply Current (Standby)
CS = V − 0.3 V
U/D, INC = V − 0.3 V or GND
–
75
SB1
CC
CC
LOGIC INPUTS
I
Input Leakage Current
V
V
= V
CC
–
–
2
0
–
–
–
–
–
–
10
mA
mA
V
IH
IN
I
Input Leakage Current
= 0 V
−10
IL
IN
V
IH1
TTL High Level Input Voltage
TTL Low Level Input Voltage
CMOS High Level Input Voltage
CMOS Low Level Input Voltage
4.5 V V 5.5 V
V
CC
CC
V
0.8
+ 0.3
V
IL1
V
IH2
2.5 V V 6 V
V
CC
x 0.7
V
CC
V
CC
V
−0.3
V
x 0.2
V
IL2
CC
POTENTIOMETER CHARACTERISTICS
R
Potentiometer Resistance
−10 Device
−50 Device
−00 Device
10
50
kW
POT
100
Pot. Resistance Tolerance
20
%
V
V
RH
Voltage on R pin
0
0
V
CC
V
CC
H
V
RL
Voltage on R pin
V
L
Resolution
1
%
INL
Integral Linearity Error
Differential Linearity Error
Buffer Output Resistance
I
I
2 mA
2 mA
0.5
0.25
1
LSB
LSB
W
W
DNL
0.5
1
W
R
0.05 V V
V
0.95 V
0.95 V
,
,
OUT
CC
WB
CC
= 5 V
CC
I
Buffer Output Current
0.05 V V
V
3
mA
OUT
CC
WB
CC
= 5 V
CC
TC
TC of Pot Resistance
Ratiometric TC
300
20
ppm/C
ppm/C
pF
RPOT
TC
RATIO
C
/C /C
RH RL RW
Potentiometer Capacitances
Frequency Response
Output Voltage Range
8/8/25
1.7
fc
Passive Attenuator, 10 kW
100 mA, V = 5 V
MHz
V
I
0.01 V
0.99 V
CC
WB(SWING)
OUT
CC
CC
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch-up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V + 1 V
CC
5. I = source or sink
W
6. These parameters are periodically sampled and are not 100% tested.
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CAT5112
Table 5. AC TEST CONDITIONS
V
CC
Range
2.5 V V 6 V
CC
Input Pulse Levels
0.2 V to 0.7 V
CC
CC
Input Rise and Fall Times
Input Reference Levels
10 ns
0.5 V
CC
Table 6. AC OPERATING CHARACTERISTICS (V = +2.5 V to +6.0 V, V = V , V = 0 V, unless otherwise specified)
CC
H
CC
L
Symbol
Parameter
Min
100
50
100
250
250
1
Typ (Note 7)
Max
−
Units
ns
t
CI
t
DI
t
ID
CS to INC Setup
U/D to INC Setup
U/D to INC Hold
INC LOW Period
INC HIGH Period
−
−
−
−
−
−
−
−
1
−
−
–
5
−
ns
−
ns
t
−
ns
IL
IH
IC
t
t
−
ns
INC Inactive to CS Inactive
CS Deselect Time (NO STORE)
CS Deselect Time (STORE)
−
ms
t
t
100
10
−
−
ns
CPH
CPH
−
ms
ms
t
IW
INC to V
Change
5
OUT
t
INC Cycle Time
1
−
ms
CYC
t , t (Note 8) INC Input Rise and Fall Time
−
500
1
ms
R
F
t
(Note 8)
Power-up to Wiper Stable
Store Cycle
–
ms
ms
PU
t
–
10
WR
7. Typical values are for T = 25C and nominal supply voltage.
A
8. This parameter is periodically sampled and not 100% tested.
9. MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.
CS
(store)
t
CYC
t
t
IC
CPH
t
CI
t
IL
t
IH
90%
90%
10%
INC
U/D
t
DI
t
ID
t
F
t
R
(3)
t
IW
MI
R
WB
Figure 4. A.C. Timing
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CAT5112
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT5112
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT5112
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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CAT5112
PACKAGE DIMENSIONS
MSOP 8, 3x3
CASE 846AD
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E1
E
E1
e
3.00
0.65 BSC
0.60
L
0.40
0.80
L1
L2
θ
0.95 REF
0.25 BSC
0º
6º
TOP VIEW
D
A2
A
DETAIL A
A1
e
b
c
SIDE VIEW
END VIEW
q
L2
Notes:
L
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L1
DETAIL A
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9
CAT5112
Table 7. ORDERING INFORMATION
Specific Device
Package
Type
Temperature
Range
Lead
Finish
†
Marking
CAT5112V
CAT5112V
CAT5112V
A22
Device Order Number
CAT5112VI−10−GT3
CAT5112VI−50−GT3
CAT5112VI−00−GT3
CAT5112YI−10−GT3
CAT5112YI−50−GT3
CAT5112YI−00−GT3
CAT5112ZI−10−GT3
CAT5112ZI−50−GT3
CAT5112ZI−00−GT3
CAT5112LI−10−G
Shipping
SOIC−8
SOIC−8
−40C to +85C
−40C to +85C
−40C to +85C
−40C to +85C
−40C to +85C
−40C to +85C
−40C to +85C
−40C to +85C
−40C to +85C
−40C to +85C
−40C to +85C
−40C to +85C
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Rail, 50 Units
SOIC−8
TSSOP−8
TSSOP−8
TSSOP−8
MSOP−8
MSOP−8
MSOP−8
PDIP−8
A24
A25
ABPN
ABPN
ABPN
CAT5112L
CAT5112L
CAT5112L
CAT5112LI−50−G
PDIP−8
Rail, 50 Units
CAT5112LI−00−G
PDIP−8
Rail, 50 Units
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
10.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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