CAT5251JI-00-TE13_技术文档

CAT5251

Quad Digital

Potentiometer (POT)

with 256 Taps

and SPI Interface

Description

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The CAT5251 is four digital POTs integrated with control logic and

16 bytes of NVRAM memory. Each digital POT consists of a series of

resistive elements connected between two externally accessible end

points. The tap points between each resistive element are connected to

the wiper outputs with CMOS switches. A separate 8-bit control

register (WCR) independently controls the wiper tap switches for each

digital POT. Associated with each wiper control register are four 8-bit

non-volatile memory data registers (DR) used for storing up to four

wiper settings. Writing to the wiper control register or any of the

non-volatile data registers is via a SPI serial bus. On power-up, the

contents of the first data register (DR0) for each of the four

potentiometers is automatically loaded into its respective wiper

control register.

TSSOP−24

Y SUFFIX

CASE 948AR

SOIC−24

W SUFFIX

CASE 751BK

PIN CONNECTIONS

HOLD

SCK

SO

A0

1

The CAT5251 can be used as a potentiometer or as a two terminal,

variable resistor. It is intended for circuit level or system level

adjustments in a wide variety of applications. It is available in the

−40C to 85C industrial operating temperature range and offered in a

24-lead SOIC and TSSOP package.

R

L2

W3

R

H2

H3

R

W2

R

L3

NC

CAT5251

GND

V

CC

R

W1

L0

Features

R

H1

H0

 Four Linear-taper Digital Potentiometers

 254 Resistor Taps per Potentiometer

 End to End Resistance 50 kW or 100 kW

 Potentiometer Control and Memory Access via SPI Interface

 Low Wiper Resistance, Typically 100 W

R

L1

W0

A1

SI

CS

WP

SOIC−24 (W)

TSSOP−24 (Y)

(Top View)

 Nonvolatile Memory Storage for up to Four Wiper Settings for Each

Potentiometer

 Automatic Recall of Saved Wiper Settings at Power Up

 2.5 to 6.0 Volt Operation

 Standby Current less than 1 mA

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 13 of this data sheet.

 1,000,000 Nonvolatile WRITE Cycles

 100 Year Nonvolatile Memory Data Retention

 SOIC 24-lead and TSSOP 24-lead

 Industrial Temperature Range

 These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS

Compliant

 Semiconductor Components Industries, LLC, 2013

1

Publication Order Number:

July, 2013 − Rev. 9

CAT5251/D

CAT5251

MARKING DIAGRAMS

(SOIC−24)

(TSSOP−24)

L3B

CAT5251WT

−RRYMXXXX

RLB

CAT5251YT

3YMXXX

L = Assembly Location

3 = Lead Finish − Matte−Tin

B = Product Revision (Fixed as “B”)

CAT = Fixed as “CAT”

5251W = Device Code

T = Temperature Range (I = Industrial)

− = Dash

RR = Resistance

25 = 2.5 KW

10 = 10 KW

50 = 50 KW

R = Resistance

1 = 2.5 KW

2 = 10 KW

4 = 50 KW

5 = 100 KW

L = Assembly Location

B = Product Revision (Fixed as “B”)

CAT5251Y = Device Code

T = Temperature Range (I = Industrial)

3 = Lead Finish − Matte−Tin

Y = Production Year (Last Digit)

M = Production Month (1−9, O, N, D)

XXX = Last Three Digits of Assembly Lot Number

00 = 100 KW

Y = Production Year (Last Digit)

M = Production Month (1-9, O, N, D)

XXXX = Last Four Digits of Assembly Lot Number

R

H3

H0

H1

H2

CS

WIPER

SPI BUS

INTERFACE

SCK

SI

CONTROL

R

W0

REGISTERS

SO

R

W1

R

W2

WP

A0

NONVOLATILE

DATA

REGISTERS

R

W3

CONTROL

LOGIC

A1

HOLD

R

L3

L0

L1

L2

Figure 1. Functional Diagram

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CAT5251

PIN DESCRIPTIONS

SI: Serial Input

having to re-transmit entire sequence at a later time. To

pause, HOLD must be brought low while SCK is low. The

SO pin is in a high impedance state during the time the part

is paused, and transitions on the SI pins will be ignored. To

resume communication, HOLD is brought high, while SCK

is low. (HOLD should be held high any time this function is

SI is the serial data input pin. This pin is used to input all

opcodes, byte addresses and data to be written to the

CAT5251. Input data is latched on the rising edge of the

serial clock.

SO: Serial Output

not being used.) HOLD may be tied high directly to V or

CC

SO is the serial data output pin. This pin is used to transfer

data out of the CAT5251. During a read cycle, data is shifted

out on the falling edge of the serial clock.

tied to V through a resistor.

CC

Table 1. PIN DESCRIPTION

SCK: Serial Clock

Pin #

Name

SO

Function

Serial Data Output

SCK is the serial clock pin. This pin is used to synchronize

the communication between the microcontroller and the

CAT5251. Opcodes, byte addresses or data present on the SI

pin are latched on the rising edge of the SCK. Data on the SO

pin is updated on the falling edge of the SCK.

1

2

3

4

A0

Device Address, LSB

R

W3

Wiper Terminal for Potentiometer 3

R

High Reference Terminal for

Potentiometer 3

H3

A0, A1: Device Address Inputs

These inputs set the device address when addressing

multiple devices. A total of four devices can be addressed on

a single bus. A match in the slave address must be made with

the address input in order to initiate communication with the

CAT5251.

5

R

Low Reference Terminal for

Potentiometer 3

L3

6

7

8

NC

No Connect

V

CC

Supply Voltage

R

Low Reference Terminal for

Potentiometer 0

L0

H0

W0

R , R : Resistor End Points

H

L

The four sets of R and R pins are equivalent to the

H

L

9

R

High Reference Terminal for

Potentiometer 0

terminal connections on a mechanical potentiometer.

R : Wiper

W

10

11

12

13

14

15

R

Wiper Terminal for Potentiometer 0

Chip Select

The four R pins are equivalent to the wiper terminal of

W

a mechanical potentiometer.

CS

WP

SI

CS: Chip Select

Write Protection

CS is the Chip select pin. CS low enables the CAT5251

and CS high disables the CAT5251. CS high takes the SO

output pin to high impedance and forces the devices into a

Standby mode (unless an internal write operation is

underway). The CAT5251 draws ZERO current in the

Standby mode. A high to low transition on CS is required

prior to any sequence being initiated. A low to high

transition on CS after a valid write sequence is what initiates

an internal write cycle.

Serial Input

A1

Device Address

R

Low Reference Terminal for

Potentiometer 1

L1

16

R

High Reference Terminal for

Potentiometer 1

H1

17

18

19

20

21

R

W1

Wiper Terminal for Potentiometer 1

Ground

GND

NC

WP: Write Protect

No Connect

WP is the Write Protect pin. The Write Protect pin will

allow normal read/write operations when held high. When

WP is tied low, all non-volatile write operations to the Data

registers are inhibited (change of wiper control register is

allowed). WP going low while CS is still low will interrupt

a write to the registers. If the internal write cycle has already

been initiated, WP going low will have no effect on any write

operation.

R

W2

Wiper Terminal for Potentiometer 2

R

High Reference Terminal for

Potentiometer 2

H2

22

R

Low Reference Terminal for

Potentiometer 2

L2

23

24

SCK

Bus Serial Clock

Hold

HOLD

HOLD: Hold

The HOLD pin is used to pause transmission to the

CAT5251 while in the middle of a serial sequence without

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CAT5251

SERIAL BUS PROTOCOL

The CAT5251 supports the SPI bus data transmission

After the device is selected with CS going low the first

byte will be received. The part is accessed via the SI pin, with

data being clocked in on the rising edge of SCK. The first

byte contains one of the six op-codes that define the

operation to be performed.

protocol. The synchronous Serial Peripheral Interface (SPI)

helps the CAT5251 to interface directly with many of

today’s popular microcontrollers. The CAT5251 contains an

8-bit instruction register. The instruction set and the

operation codes are detailed in Table 13, Instruction Set on

page 9.

DEVICE OPERATION

The CAT5251 is four resistor arrays integrated with an

SPI serial interface logic, four 8-bit wiper control registers

and sixteen 8-bit, non-volatile memory data registers. Each

resistor array contains 255 separate resistive elements

connected in series. The physical ends of each array are

equivalent to the fixed terminals of a mechanical

point for each potentiometer is connected to its wiper

terminal at a time and is determined by the value of the wiper

control register. Data can be read or written to the wiper

control registers or the non-volatile memory data registers

via the SPI bus. Additional instructions allow data to be

transferred between the wiper control registers and each

respective potentiometer’s non-volatile data registers. Also,

the device can be instructed to operate in an “increment/

decrement” mode.

potentiometer (R and R ). R and R are symmetrical and

H

L

H

L

may be interchanged. The tap positions between and at the

ends of the series resistors are connected to the output wiper

terminals (R ) by a CMOS transistor switch. Only one tap

W

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter

Ratings

Units

C

V

Temperature Under Bias

Storage Temperature

−55 to +125

−65 to +150

Voltage on any Pin with Respect to V (Notes 1, 2)

−2.0 to +V +2.0

SS

CC

V

CC

with Respect to Ground

−2.0 to +7.0

V

Package Power Dissipation Capability (T = 25C)

1.0

300

6

W

A

Lead Soldering Temperature (10 s)

Wiper Current

C

mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC

voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.

CC

2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V + 1 V.

CC

Table 3. RECOMMENDED OPERATING CONDITIONS

Parameter

Ratings

+2.5 V to +6

−40 to +85

Units

V

CC

Operating Ambient Temperature (Industrial)

C

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CAT5251

Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Test Conditions

Min

Typ

100

50

Max

Units

kW

%

R

Potentiometer Resistance (−00)

Potentiometer Resistance (−50)

Potentiometer Resistance Tolerance

POT

20

1

R

Matching

%

POT

Power Rating

25C, each pot

50

mW

mA

W

I

W

Wiper Current

Wiper Resistance

3

R

W

I

= 3 mA @ V = 3 V

200

100

300

150

W

CC

= 3 mA @ V = 5 V

W

CC

V

TERM

Voltage on any R or R Pin

V

SS

= 0 V

GND

V

CC

V

H

L

V

N

Noise

(Note 3)

nV/Hz

%

Resolution

0.4

Absolute Linearity (Note 4)

Relative Linearity (Note 5)

Temperature Coefficient of R

R

− R

1

LSB

W(n)(actual)

(n)(expected)

(Note 7)

(Note 6)

R

W(n+1)

− [R ]

W(n)+LSB

0.5

LSB

(Note 6)

(Note 7)

(Note 3)

TC

300

ppm/C

pF

RPOT

POT

TC

Ratiometric Temp. Coefficient

Potentiometer Capacitances

Frequency Response

20

RATIO

C /C /C

H

10/10/25

0.4

L

W

fc

R

= 50 kW (Note 3)

MHz

POT

3. This parameter is tested initially and after a design or process change that affects the parameter.

4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.

It is a measure of the error in step size.

6. LSB = R

/ 255 or (R − R ) / 255, single pot

TOT

H L

7. n = 0, 1, 2, ..., 255.

Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

I

Power Supply Current

f

= 2.5 MHz, SO Open

= 6 V Inputs = GND

1

mA

CC1

SCK

CC

V

I

Power Supply Current

Non-volatile Write

f

= 2.5 MHz, SO = Open

= 6 V Inputs = GND

5

mA

CC2

SCK

CC

V

I

Standby Current (V = 5.0 V)

= GND or V ; SO Open

1

mA

V

SB

CC

IN

CC

I

LI

Input Leakage Current

Output Leakage Current

Input Low Voltage

= GND to V

CC

10

IN

= GND to V

CC

LO

OUT

V

IL

−1

V

x 0.3

CC

V

Input High Voltage

V

x 0.7

V

+ 1.0

V

IH

CC

V

Output Low Voltage (V = 3 V)

I

= 3 mA

0.4

V

OL1

OH1

CC

OL

V

Output High Voltage (V = 6 V)

= −1.6 mA

− 0.8

V

CC

OH

CC

Table 6. PIN CAPACITANCE (Note 8)

(Applicable over recommended operating range from T = 25C, f = 1.0 MHz, V = +5.0 V (unless otherwise noted).)

A

CC

Symbol

Parameter

Output Capacitance (SO)

Input Capacitance (CS, SCK, SI, WP, HOLD, A0, A1

Test Conditions

Min

Typ

Max

8

Units

C

V

OUT

= 0 V

pF

OUT

C

V

IN

= 0 V

6

IN

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CAT5251

Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Test Conditions

Min

50

Typ

Max

Units

ns

t

Data Setup Time

Data Hold Time

SCK High Time

SCK Low Time

Clock Frequency

SU

t

H

50

ns

t

125

DC

ns

WH

t

ns

WL

f

3

50

2

MHz

ns

SCK

t

LZ

HOLD to Output Low Z

Input Rise Time

t

(Note 8)

ms

RI

t

Input Fall Time

2

ms

FI

t

HOLD Setup Time

HOLD Hold Time

Output Valid from Clock Low

Output Hold Time

Output Disable Time

HOLD to Output High Z

CS High Time

100

ns

C_L= 50 pF

HD

t

ns

CD

t

V

200

ns

t

0

ns

HO

t

250

100

ns

DIS

t

ns

HZ

t

250

ns

CS

t

CS Setup Time

ns

CSS

CSH

t

CS Hold Time

ns

Table 8. POWER UP TIMING (Notes 8, 9) (Over recommended operating conditions unless otherwise stated.)

Symbol Parameter Min Typ

Power-up to Read Operation

Power-up to Write Operation

8. This parameter is tested initially and after a design or process change that affects the parameter.

Max

Units

ms

t

1

PUR

t

ms

PUW

9. t and t are the delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

CC

Table 9. WIPER TIMING

Symbol

Parameter

Min

5

Max

10

Units

ms

t

Wiper Response Time After Power Supply Stable

Wiper Response Time After Instruction Issued

WRPO

t

5

10

ms

WRL

Table 10. WRITE CYCLE LIMITS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Min

Typ

Max

Units

t

Write Cycle Time

5

ms

WR

Table 11. RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

(Note 10)

Parameter

Endurance

Reference Test Method

MIL−STD−883, Test Method 1033

MIL−STD−883, Test Method 1008

MIL−STD−883, Test Method 3015

JEDEC Standard 17

Min

1,000,000

100

Typ

Max

Units

N

Cycles/Byte

END

T

(Note 10)

Data Retention

ESD Susceptibility

Latch-Up

Years

V

DR

ZAP

LTH

V

2000

I

100

mA

10.This parameter is tested initially and after a design or process change that affects the parameter.

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CAT5251

t

CS

V

IH

CS

V

IL

t

CSH

CSS

V

IH

t

SCK

SI

WH

WL

V

IL

t

H

SU

V

IH

VALID IN

V

IL

t

RI

FI

t

V

t

DIS

HO

V

OH

HI−Z

SO

V

OL

Note: Dashed Line = mode (1, 1)

Figure 2. Sychronous Data Timing

CS

t

CD

SCK

t

HD

t

HD

HOLD

SO

t

HZ

HIGH IMPEDANCE

t

LZ

Figure 3. HOLD Timing

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CAT5251

INSTRUCTION AND REGISTER DESCRIPTION

Instruction Byte

Device Type / Address Byte

The first byte sent to the CAT5251 from the

master/processor is called the Device Address Byte. The

most significant four bits of the Device Type address are a

device type identifier. These bits for the CAT5251 are fixed

at 0101[B] (refer to Figure 4).

The two least significant bits in the slave address byte, A1

− A0, are the internal slave address and must match the

physical device address which is defined by the state of the

A1 −A0 input pins for the CAT5251 to successfully continue

the command sequence. Only the device which slave

address matches the incoming device address sent by the

master executes the instruction. The A1 − A0 inputs can be

The next byte sent to the CAT5251 contains the

instruction and register pointer information. The four most

significant bits used provide the instruction opcode I3−I0.

The R1 and R0 bits point to one of the four data registers of

each associated potentiometer. The least two significant bits

point to one of four Wiper Control Registers. The format is

shown in Figure 5.

Table 12. DATA REGISTER SELECTION

Data Register Selected

R1

0

R0

0

DR0

DR1

DR2

DR3

0

1

actively driven by CMOS input signals or tied to V or

CC

1

0

V . The remaining two bits in the device address byte must

SS

be set to 0.

1

Device Type

Identifier

Slave Address

ID3

0

ID2

ID1

ID0

0

A1

A0

1

0

1

(MSB)

(LSB)

Figure 4. Identification Byte Format

Instruction

Opcode

Data Register

Selection

WCR/Pot Selection

I3

I2

I1

I0

R1

R0

P1

P0

(MSB)

(LSB)

Figure 5. Instruction Byte Format

WIPER CONTROL AND DATA REGISTERS

Data Registers (DR)

Wiper Control Register (WCR)

The CAT5251 contains four 8-bit Wiper Control

Registers, one for each potentiometer. The Wiper Control

Register output is decoded to select one of 256 switches

along its resistor array. The contents of the WCR can be

altered in four ways: it may be written by the host via Write

Wiper Control Register instruction; it may be written by

transferring the contents of one of four associated Data

Registers via the XFR Data Register instruction; it can be

modified one step at a time by the Increment/decrement

instruction (see Instruction section for more details).

Finally, it is loaded with the content of its data register zero

(DR0) upon power-up.

The Wiper Control Register is a volatile register that loses

its contents when the CAT5251 is powered-down. Although

the register is automatically loaded with the value in DR0

upon power-up, this may be different from the value present

at power-down.

Each potentiometer has four 8-bit non-volatile Data

Registers. These can be read or written directly by the host.

Data can also be transferred between any of the four Data

Registers and the associated Wiper Control Register. Any

data changes in one of the Data Registers is a non-volatile

operation and will take a maximum of 5 ms.

If the application does not require storage of multiple

settings for the potentiometer; the Data Registers can be

used as standard memory locations for system parameters or

user preference data.

Write in Process

The contents of the Data Registers are saved to

nonvolatile memory when the CS input goes HIGH after a

write sequence is received. The status of the internal write

cycle can be monitored by issuing a Read Status command

to read the Write in Process (WIP) bit.

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CAT5251

Instructions

Four of the ten instructions are three bytes in length. These

instructions are:

 Read Data Register – read the contents of the selected

Data Register

 Read Wiper Control Register – read the current wiper

position of the selected potentiometer in the WCR

 Write Data Register – write a new value to the

selected Data Register

 Write Wiper Control Register – change current wiper

 Read Status – Read the status of the WIP bit which

when set to “1” signifies a write cycle is in progress.

position in the WCR of the selected potentiometer

Table 13. INSTRUCTION SET (Note: 1/0 = data is one or zero)

Instruction Set

I3 I2 I1 I0

R1

R0

WCR1/P1

WCR0/P0

Instruction

Operations

Read Wiper Control

Register

1

0

1

0

1

0

1

0

1

0

1

0

1/0

Read the contents of the Wiper Control Register

pointed to by P1−P0

Write Wiper Control

Register

0

1/0

Write new value to the Wiper Control Register

pointed to by P1−P0

Read Data Register

1/0

Read the contents of the Data Register pointed to

by P1−P0 and R1−R0

Write Data Register

Write new value to the Data Register pointed to

by P1−P0 and R1−R0

XFR Data Register

to Wiper Control

Register

Transfer the contents of the Data Register

pointed to by P1−P0 and R1−R0 to its

associated Wiper Control Register

XFR Wiper Control

Register to Data

Register

1

0

1

0

1

0

1

0

1/0

0

1/0

0

Transfer the contents of the Wiper Control

Register pointed to by P1−P0 to the Data

Register pointed to by R1−R0

Global XFR Data

Registers to Wiper

Control Registers

Transfer the contents of the Data Registers

pointed to by R1−R0 of all four pots to their

respective Wiper Control Registers

Global XFR Wiper

Control Registers to

Data Register

0

Transfer the contents of both Wiper Control

Registers to their respective data Registers

pointed to by R1−R0 of all four pots

Increment/Decrement

Wiper Control Register

0

1

0

1

0

1/0

0

1/0

1

Enable Increment/decrement of the Control Latch

pointed to by P1−P0

Read Status (WIP bit)

Read WIP bit to check internal write cycle status

The basic sequence of the three byte instructions is

illustrated in Figure 7. These three-byte instructions

exchange data between the WCR and one of the Data

Registers. The WCR controls the position of the wiper. The

 XFR Wiper Control Register to Data Register

This transfers the contents of the specified Wiper

Control Register to the specified associated Data

Register.

 Global XFR Data Register to Wiper Control

Register

This transfers the contents of all specified Data

Registers to the associated Wiper Control Registers.

 Global XFR Wiper Counter Register to Data

Register

response of the wiper to this action will be delayed by t

.

WRL

A transfer from the WCR (current wiper position), to a Data

Register is a write to non-volatile memory and takes a

minimum of t

to complete. The transfer can occur

WR

between one of the four potentiometers and one of its

associated registers; or the transfer can occur between all

potentiometers and one associated register.

Four instructions require a two-byte sequence to

complete, as illustrated in Figure 6. These instructions

transfer data between the host/processor and the CAT5251;

either between the host and one of the data registers or

directly between the host and the Wiper Control Register.

These instructions are:

This transfers the contents of all Wiper Control Registers

to the specified associated Data Registers.

Increment/Decrement Command

The final command is Increment/Decrement (Figures 8

and 9). The Increment/Decrement command is different

from the other commands. Once the command is issued the

master can clock the selected wiper up and/or down in one

segment steps; thereby providing a fine tuning capability to

 XFR Data Register to Wiper Control Register

This transfers the contents of one specified Data

Register to the associated Wiper Control Register.

the host. For each SCK clock pulse (t

) while SI is

HIGH

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9

CAT5251

HIGH, the selected wiper will move one resistor segment

See Instructions format for more detail.

towards the R terminal. Similarly, for each SCK clock

H

pulse while SI is LOW, the selected wiper will move one

resistor segment towards the R terminal.

L

SI

0

1

0

1

0

ID3 ID2 ID1 ID0

A3 A2 A1 A0

I3 I2 I1 I0

R1 R0 P1 P0

Internal

Address

Instruction

Opcode

Register

Address

Pot/WCR

Address

Device ID

Figure 6. Two-byte Instruction Sequence

0

1

0

1

0

SI

I3 I2 I1 I0

D7 D6 D5 D4 D3 D2 D1 D0

R1 R0 P1 P0

ID3 ID2 ID1 ID0 A3 A2 A1 A0

Internal

Address

Device ID

Instruction

Opcode

Data

Register Address

Address

WCR[7:0]

or

Pot/WCR

Data Register D[7:0]

Figure 7. Three-byte Instruction Sequence

0

1

0

1

0

SI

ID3 ID2 ID1 ID0

A3 A2 A1 A0 I3

I2 I1 I0

R1 R0 P1 P0

I

D

E

C

1

I

D

E

C

n

N

C

2

N

C

n

Instruction

Opcode

Pot/WCR C

Address

Internal

Address

Data

Device ID

1

Register

Address

Figure 8. Increment/Decrement Instruction Sequence

INC/DEC

Command

Issued

t

WRL

SCK

SI

Voltage Out

R

W

Figure 9. Increment/Decrement Timing Limits

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10

CAT5251

INSTRUCTION FORMAT

Table 14. READ WIPER CONTROL REGISTER (WCR)

CS

DEVICE ADDRESSES

A1 A0

INSTRUCTION

DATA

CS

0

1

0

1

0

1

0

1

0

P1 P0

7

6

5

4

3

2

1

0

Table 15. WRITE WIPER CONTROL REGISTER (WCR)

CS

DEVICE ADDRESSES

A1 A0

INSTRUCTION

DATA

0

1

0

1

0

1

0

1

0

P1 P0

4

3

Table 16. READ DATA REGISTER (DR)

CS

DEVICE ADDRESSES

A1 A0

INSTRUCTION

R1 R0 P1 P0

DATA

0

1

0

1

0

1

4

3

Table 17. WRITE DATA REGISTER (DR)

CS

DEVICE ADDRESSES

A1 A0

INSTRUCTION

DATA

High

Voltage

Write

0

1

0

1

0

1

0

R1 R0 P1 P0

4

3

Cycle

Table 18. READ STATUS (WIP)

CS

DEVICE ADDRESSES

A1 A0

INSTRUCTION

DATA

0

1

0

1

0

1

0

1

7

0

6

0

5

0

4

0

3

0

2

0

1

0

W

I

P

Table 19. GLOBAL TRANSFER DATA REGISTER (DR)

TO WIPER CONTROL REGISTER (WCR)

CS

DEVICE ADDRESSES

A1 A0

INSTRUCTION

R1 R0

CS

0

1

0

1

0

1

0

Table 20. GLOBAL TRANSFER WIPER CONTROL REGISTER (WCR)

TO DATA REGISTER (DR)

CS

DEVICE ADDRESSES

A1 A0

INSTRUCTION

R1 R0

CS

High

Voltage

Write

0

1

0

1

0

1

0

Cycle

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11

CAT5251

Table 21. TRANSFER WIPER CONTROL REGISTER (WCR)

TO DATA REGISTER (DR)

CS

DEVICE ADDRESSES

A1 A0

INSTRUCTION

CS

High

Voltage

Write

0

1

0

1

0

1

0

R1 R0 P1 P0

Cycle

Table 22. TRANSFER DATA REGISTER (DR)

TO WIPER CONTROL REGISTER (WCR)

CS

DEVICE ADDRESSES

A1 A0

INSTRUCTION

CS

0

1

0

1

0

1

0

1

R1 R0 P1 P0

Table 23. INCREMENT (I)/DECREMENT (D) WIPER CONTROL REGISTER (WCR)

CS

DEVICE ADDRESSES

A1 A0

INSTRUCTION

DATA

CS

0

1

0

1

0

1

0

P1 P0

I/D

. . .

I/D

NOTE: Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.

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12

CAT5251

Table 24. ORDERING INFORMATION

Orderable Part Number

CAT5251WI−50−T1

CAT5251WI−00−T1

CAT5251YI−50−T2

CAT5251YI−00−T2

CAT5251WI50

Resistance (kW)

Lead Finish

Package

Shipping

50

100

50

1000 / Tape & Reel

2000 / Tape & Reel

31 Units / Tube

SOIC

TSSOP

SOIC

100

50

Matte-Tin

CAT5251WI00

100

50

31 Units / Tube

CAT5251YI50

62 Units / Tube

TSSOP

CAT5251YI00

100

62 Units / Tube

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

11. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device

Nomenclature document, TND310/D, available at www.onsemi.com.

12.All packages are RoHS-compliant (Lead-free, Halogen-free).

13.The standard lead finish is Matte-Tin.

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13

CAT5251

PACKAGE DIMENSIONS

SOIC−24, 300 mils

CASE 751BK

ISSUE O

SYMBOL

MIN

NOM

MAX

2.65

0.30

2.55

0.51

0.33

15.40

10.51

7.60

2.35

A

A1

A2

b

0.10

2.05

0.31

0.20

15.20

10.11

7.34

E1

E

c

D

E

E1

e

1.27 BSC

h

0.25

0.40

0º

0.75

1.27

8º

L

b

e

θ

PIN#1 IDENTIFICATION

5º

15º

θ1

TOP VIEW

h

D

h

q1

A2

q

A

q1

L

c

A1

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-013.

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14

CAT5251

PACKAGE DIMENSIONS

TSSOP24, 4.4x7.8

CASE 948AR

ISSUE A

b

SYMBOL

MIN

NOM

MAX

A

A1

A2

b

1.20

0.15

1.05

0.30

0.20

7.90

6.55

4.50

0.05

0.80

0.19

0.09

7.70

6.25

4.30

c

E1

E

D

7.80

6.40

E

E1

e

4.40

0.65 BSC

0.60

L

0.50

0.70

L1

1.00 REF

0º

8º

θ

e

TOP VIEW

D

c

A2

A

θ1

L

A1

L1

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

CAT5251/D

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15


型号：	CAT5251JI-00-TE13
厂家：	ONSEMI
描述：	QUAD 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24, SOIC-24 光电二极管
文件：	总15页 (文件大小：189K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT5251JI-00-TE13 [ONSEMI]

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