CAT872-05ULGT3 [ONSEMI]
Dual Input Reset Generator;
| 型号： | CAT872-05ULGT3 |
| 厂家： | 
ONSEMI |
| 描述： | Dual Input Reset Generator |
| 文件： | 总9页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT871, CAT872
Dual Input Reset Generator
Description
CAT871, CAT872 are dual input reset generators designed to restart
microprocessor and microcontroller based systems when the
watchdog timer or other resetting mechanisms have become disabled
or failed.
http://onsemi.com
CAT871, CAT872 monitor two inputs and output an active low reset
pulse after both inputs have been active (logic low) for a factory preset
minimum time. The reset pulse width is 2.2 ms for CAT871 and 70 ms
for CAT872. Releasing either input from its active state before the
minimum timeout period resets the internal timer and both inputs must
return to being active before the timer will restart with a fresh count
down.
CAT871, CAT872’s open drain output is capable of sinking up to
3 mA of current and may be wire−OR’d with other open drain devices
to drive a common reset input.
1
ULLGA−6
UL SUFFIX
CASE 613AF
MARKING DIAGRAM
Features
XM
• Operate on 1.65 V to 5.5 V Power Supplies
• Ultra Low Quiescent Current: 10 nA (typical)
• Schmitt Trigger Inputs
• 8 Factory Preset Delay Times from 0.5 s to 5 s to Choose From
• Small mLLGA−6 Package: 1.45 x 1.0 x 0.4 mm
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
X = Specific Device Code
X = (J = CAT871, K = CAT872)
M = Date Code
PIN CONNECTIONS
Typical Applications
MR1
MR2
NIC
1
VDD
• Mobile Phones
• PDAs
RESET
GND
• MP3 Players
• Personal Navigation Devices
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
November, 2011 − Rev. 0
CAT871/D
CAT871, CAT872
FUNCTIONAL BLOCK DIAGRAM
VDD
RESET
MR2
MR1
RESET
Pulse
Delay Timer
Generator
GND
Figure 2. Functional Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
MR1
Description
1
2
3
4
5
6
Manual reset input #1. CMOS input.
Manual reset input #2. CMOS input.
MR2
NIC
No Internal Connection. A voltage or signal applied to this pin will have no effect on device operation.
GND
System Ground.
RESET
VDD
Reset Output. Active−low open drain output.
Positive Power Supply.
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Input Voltage Range
V
DD
−0.3 to 6
−0.3 to 6
Output Voltage Range
V
OUT
V
or (V + 0.3), whichever is lower
DD
Input Voltage; MR2, MR1
V
IN
−0.3 to 6
V
or (V + 0.3), whichever is lower
DD
Maximum Junction Temperature
Output Current; RESET
T
150
10
°C
mA
°C
kV
V
J(max)
I
OUT
Storage Temperature Range
T
−65 to 150
2
STG
ESD Capability, Human Body Model (Note 1)
ESD Capability, Machine Model (Note 1)
ESD
HBM
ESD
200
MM
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 2)
T
SLD
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latch−up Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
http://onsemi.com
2
CAT871, CAT872
Table 3. RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Min
1.65
0
Max
Unit
V
Input Voltage; VDD
V
DD
5.5
Input Voltage; MR1, MR2
Output Current; RESET
Ambient Temperature
V
IN
V
DD
V
I
0
3
mA
°C
OUT
T
A
−40
85
Table 4. ELECTRICAL OPERATING CHARACTERISTICS
(V = 1.65 V to 5.5 V. For typical values T = 25°C, for min/max values T = −40°C to +85°C unless otherwise noted.)
DD
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
POWER
V
Supply Voltage
V
1.65
5.5
1000
50
V
DD
DD
Quiescent Supply Current
Operating Supply Current
MR1 = MR2 = V
.
I
10
nA
mA
DD
DD
MR1 = MR2 = 0 V
Measured during setup period. Measurement
includes current through internal 200 kΩ
pull−up resistor on MR2
LOGIC INPUTS AND OUTPUTS
Input Voltage; HIGH
Input Voltage; LOW
Hysteresis
MR1, MR2
MR1, MR2
V
0.7 x V
V
V
IH
DD
V
0.25xV
300
IL
DD
V
HYS
−
250
50
mV
nA
mA
Input Current
MR1 = 0 V; V = 5 V (no internal pull−up)
I
DD
PU
Input Current
MR2 = 0 V; V = 5 V
(internal 200 kW pull−up resistor)
I
25
DD
PU
Output Voltage; HIGH
External 10 kW pull−up resistor to V
V
V – 0.1
DD
V
V
DD
OH
Output Voltage; LOW
TIMING
I
= 3 mA, V = 1.8 V
V
OL
0.1
0.4
SINK
DD
Timeout
CAT87x−05
CAT87x−10
CAT87x−15
CAT87x−20
CAT87x−25
CAT87x−30
CAT87x−40
CAT87x−50
CAT871
t
0.41
0.50
1.00
1.50
2.00
2.50
3.00
4.00
5.00
2.2
0.59
1.18
1.77
2.36
2.95
3.54
4.72
5.9
s
s
LOW_DELAY
0.82
1.23
1.64
2.05
2.46
3.28
4.1
s
s
s
s
s
s
Reset Output Pulse Width
t
R
1.8
2.6
ms
CAT872
57
70
83
TEST MODE (at T = 25°C) (Note 3)
A
Start TEST window
t
35
ms
ms
ST
Test Mode delay
MR1=0 V, MR2→8 cycles, delay measured
t
250
1
D
th
after 8 rising edge of the MR2 clock pulse
Test Mode Clock Frequency
Clock applied to MR2
f
MHz
tm
MR2 Test mode clock setup
time
Measured from MR1 falling edge to first
falling edge of MR2
t
P
1
ms
MR2 Input Voltage; LOW
MR2 Pulse Width
MR2, Test mode operation
V
0.2xV
V
IL_TM
DD
t
pw
500
ns
3. “Test Mode” parameters are not tested in production.
http://onsemi.com
3
CAT871, CAT872
TIMING WAVEFORMS (Note 4)
Figure 3. Timing Waveforms
4. The order of the MR inputs going low does not matter. The last input to go low marks the beginning of t
LOW_DELAY
TYPICAL CHARACTERISTICS
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
−40°C
5.6 V
25°C
90°C
3.2 V
1.6 V
1.30
1.25
1.30
1.25
1
2
3
4
5
6
−50 −25
0
25
50
75
100
125 150
VDD (V)
TEMPERATURE (°C)
Figure 4. tLOW_DELAY vs. VDD (CAT87x−1.5)
Figure 5. tLOW_DELAY vs. Temperature
(CAT87x−1.5)
3.5
3.4
3.3
3.2
3.1
−40°C
3.0
25°C
2.9
90°C
2.8
2.7
2.6
2.5
0
1
2
3
4
5
6
VDD (V)
Figure 6. tLOW_DELAY vs. VDD (CAT87x−3.0)
http://onsemi.com
4
CAT871, CAT872
TYPICAL CHARACTERISTICS
30
25
20
15
10
25
20
15
10
85°C
−40°C
25°C
5
0
5
0
0
1
2
3
4
5
6
1
2
3
4
5
6
VDD (V)
VDD (V)
Figure 7. IDD vs. VDD (MR1 = MR2 = 0)
Figure 8. IMR2 @ MR2 = 0
2.6
2.5
2.4
2.3
2.2
2.1
2.0
2.6
2.5
2.4
2.3
2.2
2.1
2.0
−40°C
5.6 V
25°C
3.2 V
1.6 V
85°C
1.9
1.8
1.9
1.8
1
2
3
4
5
6
−50 −25
0
25
50
75
100
125 150
VDD (V)
TEMPERATURE (°C)
Figure 9. tR vs. VDD for CAT871
Figure 10. tR vs. Temperature for CAT871
83
81
79
77
75
73
71
69
67
65
63
61
−40°C
25°C
90°C
59
57
0
1
2
3
4
5
6
VDD (V)
Figure 11. Reset Pulse Width for CAT872
http://onsemi.com
5
CAT871, CAT872
SYSTEM DESCRIPTION AND APPLICATIONS INFORMATION
Reset Output
General
CAT871, CAT872 are designed for the manual resetting of
CAT871, CAT872 provide an active−low open drain
output to be wire−OR’d with other open drain reset devices.
This output will sink up to 3 mA and as such will not be
loaded down by low value (strong) pull−up resistors. The
reset pulse is typically 2 ms long for CAT871 and 70 ms long
for CAT872 and is issued at the conclusion of the delay
timer’s countdown sequence.
microprocessors and microcontrollers when normal
resetting mechanisms have failed. To prevent accidental
resets, CAT871, CAT872 require both manual reset inputs
be held low for a prescribed period before a reset pulse is
issued to the system processor.
Manual Reset Inputs
MR1 and MR2 are Schmitt trigger CMOS inputs. Both
inputs must go low and stay low for a predetermined period
CAT871, CAT872 will not generate a reset pulse at
power−up.
(t
) to generate a single reset pulse on the output.
Delay Timer Testing
LOW_DELAY
MR1 and MR2 operate independently and may be brought
low at any time and in any order. The last input to reach 0 V
starts the delay timer.
MR1 is a standard CMOS input and MR2 is also a CMOS
input with an internal 200 kW pull−up resistor, thus MR2 can
be left floating whereas MR1 must be biased by a pull−up
resistor, powered switch or some other means external to the
IC. (Consult factory for other input biasing options)
To aid in−circuit testing of the delay timer, a special test
function has been included in CAT871, CAT872. This test
mode, TOC, allows the delay timer to clock at an accelerated
rate. Upon the conclusion of the countdown a standard width
reset pulse will be issued and the chip will exit test mode.
To initiate TOC, MR1→ 0 V and a fast external CLK
(typically 1 MHz) is applied on MR2, with the falling edge
of the first clock pulse on MR2 delayed with tP from MR1→
0 V. CAT871, CAT872 look for 8 sequential pulses to appear
on MR2 within 35 ms to confirm TOC is desired. After the
rising edge of the 8’th pulse, there will be a delay of 250 ms
typical followed by a standard reset pulse at the reset output.
This delay is independent of the normal timeout delay
setting.
Delay Timer
When both MR1 and MR2 go low, an internal timing cycle
is initiated. If any input goes high before the countdown
timer has concluded its cycle, the timer will reset and will
restart from the beginning when MR1 and MR2 return to
being low.
If both manual reset inputs (MR1 and MR2) remain low
after a reset pulse is issued, no second reset pulse will be
issued after that.
After issuing the reset pulse, CAT871, CAT872 exit TOC
mode and returns to normal operation. If at any time during
TOC both MR1 and MR2 are HIGH, CAT871, CAT872 will
immediately exit TOC mode.
Figure 12. TOC Mode
http://onsemi.com
6
CAT871, CAT872
APPLICATION INFORMATION
Reset Pulse Operation
When both MR1 and MR2 inputs are kept low, a single
reset pulse is generated after the delay t . Even
with both MR1 and MR2 maintained low continuously after
that time, no second reset pulse will be generated. The delay
timer restarts if either MR1 or MR2 (or both) input
transitions from high to low, as shown in the timing diagram
in Figure 13.
than the VDD rail (1.8 V). MR1 and MR2 inputs are
activated here by two separate switches connected to GND
and pulling the inputs low when pressed. The Schottky diode
provides the supply isolation needed between the
CAT871/CAT872 (VDD) and the microcontroller (VBAT).
LOW_DELAY
Operation with Low VDD Voltage and Brownout
Condition
The CAT871, CAT872 reset generators require a
minimum supply voltage VDD of 1.65 V to guarantee the
normal operation within the specification. To prevent small
VDD supply glitch, a small ceramic capacitor can be added
between the VDD pin and GND.
System with Two Different Power Supply Voltages
The reset generator can be used in a system where the
supply VDD is different than the MR1, MR2 input logic.
Figure 14 shows an application schematic where the
microcontroller uses a supply VBAT (3.6 V) that is higher
Figure 13. Reset Timing Diagram
Figure 14. Application Schematic in Dual Supply System
http://onsemi.com
7
CAT871, CAT872
PACKAGE DIMENSIONS
ULLGA6, 1.45x1.0, 0.5P
CASE 613AF−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
PIN ONE
E
REFERENCE
MILLIMETERS
DIM MIN
−−−
A1 0.00
MAX
0.40
0.05
0.25
A
0.10
C
TOP VIEW
SIDE VIEW
b
D
E
e
0.15
1.45 BSC
1.00 BSC
0.50 BSC
0.25
0.10
C
L
0.35
0.40
0.05
0.05
C
C
L1 0.30
A
SEATING
PLANE
6X
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
A1
C
05.4X9
6X
0.30
e
NOTE 4
5X L
3
1
6
L1
1.24
1
4
0.53
6X b
0.50
PITCH
PKG
OUTLINE
0.10
C
C
A B
DIMENSIONS: MILLIMETERS
NOTE 3
0.05
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
8
CAT871, CAT872
Table 5. ORDERING INFORMATION
Device
Timeout (s)
Reset Pulse Width (ms)
Marking
Package
Shipping (Note 5)
CAT871−05ULGT3 (Note 6)
CAT871−10ULGT3 (Note 6)
CAT871−15ULGT3 (Note 6)
CAT871−20ULGT3 (Note 6)
CAT871−25ULGT3 (Note 6)
CAT871−30ULGT3 (Note 6)
CAT871−40ULGT3 (Note 6)
CAT871−50ULGT3 (Note 6)
CAT872−05ULGT3 (Note 6)
CAT872−10ULGT3 (Note 6)
CAT872−15ULGT3
0.5
1
1.5
2
2.2
JM
2.5
3
4
5
mLLGA−6
3,000 / Tape & Reel
0.5
1
1.5
2
CAT872−20ULGT3 (Note 6)
CAT872−25ULGT3 (Note 6)
CAT872−30ULGT3
70
KM
2.5
3
CAT872−40ULGT3 (Note 6)
CAT872−50ULGT3 (Note 6)
4
5
5. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
6. Contact Factory for availability.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
CAT871/D
相关型号：
CAT8801LSD-GT3
200 nA Microprocessor Power Supply Supervisors Ultra Low 200 nA Supply Current
ONSEMI
©2020 ICPDF网 联系我们和版权申明