CAT93C57LA-REVE [ONSEMI]
暂无描述;
| 型号： | CAT93C57LA-REVE |
| 厂家： | 
ONSEMI |
| 描述： | 暂无描述 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总17页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT93C56, CAT93C57
2-Kb Microwire Serial
CMOS EEPROM
Description
The CAT93C56/57 is a 2−kb CMOS Serial EEPROM device which
is organized as either 128 registers of 16 bits (ORG pin at V ) or 256
http://onsemi.com
CC
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The CAT93C56/57 features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
SOIC−8
V or W SUFFIX
CASE 751BD
SOIC−8 EIAJ
X SUFFIX
CASE 751BE
TDFN−8
VP2 SUFFIX
CASE 511AK
Features
• High Speed Operation: 2 MHz
• 1.8 V to 5.5 V Supply Voltage Range
• Selectable x8 or x16 Memory Organization
• Sequential Read
PDIP−8
L SUFFIX
CASE 646AA
TDFN−8
ZD4 SUFFIX
CASE 511AL
TSSOP−8
Y SUFFIX
CASE 948AL
• Software Write Protection
• Power−up Inadvertant Write Protection
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
PIN CONFIGURATIONS
1
V
CS
CC
SK
NC
DI
DO
ORG
• Industrial and Extended Temperature Ranges
• 8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
GND
PDIP (L), SOIC (V, X),
TSSOP (Y), TDFN (VP2, ZD4*)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
* TDFN 3x3 mm (ZD4) and
NC
1
ORG
GND
DO
SOIC (W) rotated pin−out
packages are available for
CAT93C57 and CAT93C56,
Rev. E only (not recommen-
ded for new designs of
CAT93C56)
V
CC
V
CC
CS
SK
DI
ORG
SOIC (W*)
(Top Views)
CS
SK
DI
CAT93C56
CAT93C57
DO
PIN FUNCTION
Pin Name
Function
Chip Select
CS
SK
DI
GND
Clock Input
Figure 1. Functional Symbol
Serial Data Input
Serial Data Output
Power Supply
Ground
NOTE: When the ORG pin is connected to V , the x16 organization is selected.
DO
CC
When it is connected to ground, the x8 pin is selected. If the ORG pin is left
unconnected, then an internal pullup device will select the x16 organization.
V
CC
GND
ORG
NC
Memory Organization
No Connection
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
August, 2009 − Rev. 18
CAT93C56/D
CAT93C56, CAT93C57
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on Any Pin with Respect to Ground (Note 1)
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V = 5 V, 25°C
CC
Table 3. D.C. OPERATING CHARACTERISTICS, CAT93C56, Die Rev. G – New Product
(V = +1.8 V to +5.5 V, T =−40°C to +125°C unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
= 1 MHz, V = 5.0 V
Min
Max
Units
I
Power Supply
Current (Write)
f
f
1
mA
CC1
SK
CC
I
Power Supply
Current (Read)
= 1 MHz, V = 5.0 V
500
mA
mA
CC2
SK
CC
I
I
Power Supply
Current (Standby)
(x8 Mode)
V
= GND or V
,
T = −40°C to +85°C
2
4
SB1
IN
CC
A
CS = GND ORG = GND
T = −40°C to +125°C
A
Power Supply
Current (Standby)
(x16 Mode)
V
= GND or V , CS =
T = −40°C to +85°C
1
mA
SB2
IN
CC
A
GND ORG = Float or V
CC
T = −40°C to +125°C
A
2
I
Input Leakage
Current
V
= GND to V
T = −40°C to +85°C
1
mA
mA
LI
IN
CC
A
T = −40°C to +125°C
A
2
I
LO
Output Leakage
Current
V
= GND to V
CS = GND
,
T = −40°C to +85°C
A
1
OUT
CC
T = −40°C to +125°C
A
2
V
V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
4.5 V v V < 5.5 V
−0.1
2
0.8
V
V
V
V
V
IL1
CC
4.5 V v V < 5.5 V
V
+ 1
IH1
CC
CC
V
IL2
1.8 V v V < 4.5 V
0
V
x 0.2
CC
CC
V
V
1.8 V v V < 4.5 V
V
x 0.7
V
+ 1
IH2
CC
CC
CC
4.5 V v V < 5.5 V,
0.4
OL1
CC
= 2.1 mA
I
OL
V
Output High Voltage
Output Low Voltage
Output High Voltage
4.5 V v V < 5.5 V,
2.4
V
V
V
OH1
CC
I
= −400 mA
OH
V
1.8 V v V < 4.5 V,
0.2
OL2
CC
= 1 mA
I
OL
V
OH2
1.8 V v V < 4.5 V,
V
− 0.2
CC
= −100 mA
CC
I
OH
http://onsemi.com
2
CAT93C56, CAT93C57
Table 4. D.C. OPERATING CHARACTERISTICS, CAT93C56/57, Die Rev. E – Mature Product (CAT93C56, Rev. E –
NOT RECOMMENDED FOR NEW DESIGNS) (V = +1.8 V to +5.5 V, T =−40°C to +125°C unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
Min
Max
3
Units
mA
mA
I
I
Power Supply Current (Write)
Power Supply Current (Read)
f
f
= 1 MHz, V = 5.0 V
CC
CC1
CC2
SK
= 1 MHz, V = 5.0 V
500
10
SK
CC
I
Power Supply Current (Standby)
(x8 Mode)
V
V
= GND or V , CS = GND
mA
SB1
IN
CC
ORG = GND
I
Power Supply Current (Standby)
(x16 Mode)
= GND or V , CS = GND
10
mA
SB2
IN
CC
ORG = Float or V
CC
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
V
= GND to V
CC
1
1
mA
mA
V
LI
IN
I
LO
V
OUT
= GND to V , CS = GND
CC
V
V
4.5 V v V < 5.5 V
−0.1
2
0.8
IL1
CC
Input High Voltage
Input Low Voltage
4.5 V v V < 5.5 V
V + 1
CC
V
IH1
CC
V
IL2
1.8 V v V < 4.5 V
0
V x 0.2
CC
V
CC
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
1.8 V v V < 4.5 V
V
V
x 0.7
V + 1
CC
V
IH2
CC
CC
4.5 V v V < 5.5 V, I = 2.1 mA
0.4
V
OL1
OH1
CC
OL
V
4.5 V v V < 5.5 V, I = −400 mA
2.4
V
CC
OH
V
V
1.8 V v V < 4.5 V, I = 1 mA
0.2
V
OL2
CC
OL
1.8 V v V < 4.5 V, I = −100 mA
− 0.2
CC
V
OH2
CC
OH
Table 5. PIN CAPACITANCE (T = 25°C, f = 1 MHz, V = 5 V)
A
CC
Symbol
(Note 4)
Test
Conditions
Min
Typ
Max
5
Units
pF
C
Output Capacitance (DO)
V
OUT
= 0 V
OUT
C
(Note 4)
Input Capacitance (CS, SK, DI, ORG)
V
IN
= 0 V
5
pF
IN
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
http://onsemi.com
3
CAT93C56, CAT93C57
Table 6. A.C. CHARACTERISTICS (Note 5), CAT93C56, Die Rev. G – New Product
(V = +1.8V to +5.5V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Limits
Min
50
Max
Symbol
Parameter
Units
ns
t
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
CSS
t
0
ns
CSH
t
100
100
ns
DIS
DIH
PD1
PD0
t
ns
t
t
Output Delay to 1
Output Delay to 0
0.25
0.25
100
5
ms
ms
t
(Note 6)
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
HZ
t
ms
ms
EW
t
0.25
0.25
0.25
CSMIN
t
ms
SKHI
t
ms
SKLOW
t
SV
0.25
ms
SK
DC
2000
kHz
MAX
Table 7. A.C. CHARACTERISTICS (Note 5), CAT93C56/57, Die Rev. E – Mature Product
(CAT93C56 Rev. E − NOT RECOMMENDED FOR NEW DESIGNS)
Limits
V
CC
= 1.8 V − 5.5 V
V
CC
= 2.5 V − 5.5 V
V
CC
= 4.5 V − 5.5 V
Min
200
0
Max
Min
100
0
Max
Min
50
Max
Symbol
Parameter
CS Setup Time
Units
t
ns
ns
ns
ns
ms
ms
ns
CSS
t
CS Hold Time
0
CSH
t
DI Setup Time
400
400
200
200
100
100
DIS
t
DI Hold Time
DIH
t
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
1
1
0.5
0.5
200
0.25
0.25
100
PD1
PD0
t
t
HZ
400
(Note 6)
t
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
10
10
10
ms
ms
EW
t
1
1
1
0.5
0.5
0.5
0.25
0.25
0.25
CSMIN
t
ms
SKHI
t
ms
SKLOW
t
Output Delay to Status Valid
Maximum Clock Frequency
1
0.5
0.25
ms
SV
SK
DC
250
DC
500
DC
1000
kHz
MAX
Table 8. POWER−UP TIMING (Notes 6 and 7)
Symbol
Parameter
Max
1
Units
t
Power−up to Read Operation
Power−up to Write Operation
ms
ms
PUR
t
1
PUW
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
7. t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
http://onsemi.com
4
CAT93C56, CAT93C57
Table 9. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.4 V to 2.4 V
4.5 V v V v 5.5 V
CC
Timing Reference Voltages
Input Pulse Voltages
0.8 V, 2.0 V
4.5 V v V v 5.5 V
CC
0.2 V to 0.7 V
1.8 V v V v 4.5 V
CC
CC
CC
Timing Reference Voltages
Output Load
0.5 V
1.8 V v V v 4.5 V
CC
CC
Current Source I
/I
; CL=100 pF
OLmax OHmax
Device Operation
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
The CAT93C56/57 is a 2048−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C56/57 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 10−bit
instructions for 93C57 or seven 11−bit instructions for
93C56 control the reading, writing and erase operations of
the device. When organized as X8, seven 11−bit instructions
for 93C57 or seven 12−bit instructions for 93C56 control the
reading, writing and erase operations of the device. The
CAT93C56/57 operates on a single power supply and will
generate on chip, the high voltage required during any write
operation.
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
t
t
SKLOW
t
SKHI
CSH
SK
t
t
DIH
DIS
VALID
VALID
DI
t
CSS
CS
t
t
, t
t
DIS
PD0 PD1
CSMN
DO
DATA VALID
Figure 2. Synchronous Data Timing
http://onsemi.com
5
CAT93C56, CAT93C57
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 7−bit address
(CAT93C57) / 8−bit address (CAT93C56) (an additional bit
when organized X8) and for write operations a 16−bit data
field (8−bit for X8 organizations). The instruction format is
shown in Instruction Set table.
Table 10. INSTRUCTION SET
Start
Address
Data
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
x8
x16
x8
x16
Instruction
Device Type
93C56 (Note 8)
93C57
Opcode
10
Comments
READ
A8−A0
A7−A0
Read Address
AN–A0
10
A7−A0
A6−A0
ERASE
WRITE
EWEN
EWDS
ERAL
93C56 (Note 8)
93C57
11
A8−A0
A7−A0
Clear Address
AN–A0
11
A7−A0
A6−A0
93C56 (Note 8)
93C57
01
A8−A0
A7−A0
D7−D0
D7−D0
D15−D0
D15−D0
Write Address
AN–A0
01
A7−A0
A6−A0
93C56 (Note 8)
93C57
00
11XXXXXXX
11XXXXXX
00XXXXXXX
00XXXXXX
10XXXXXXX
10XXXXXX
01XXXXXXX
01XXXXXX
11XXXXXX
11XXXXX
00XXXXXX
00XXXXX
10XXXXXX
10XXXXX
01XXXXXX
01XXXXX
Write Enable
Write Disable
00
93C56 (Note 8)
93C57
00
00
93C56 (Note 8)
93C57
00
Clear All
Addresses
00
WRAL
93C56 (Note 8)
93C57
00
D7−D0
D7−D0
D15−D0
D15−D0
Write All
Addresses
00
8. Address bit A8 for 256x8 organization and A7 for 128x16 organization are “Don’t Care” bits, but must be kept at either a “1” or “0” for READ,
WRITE and ERASE commands.
http://onsemi.com
6
CAT93C56, CAT93C57
Read
data word is preceeded by a dummy zero bit. All subsequent
data words will follow without a dummy zero bit. The
READ instruction timing is illustrated in Figure 3.
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C56/57
will come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
Erase/Write Enable and Disable
The CAT93C56/57 powers up in the write disable state.
Any writing after power−up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C56/57 write
and erase instructions, and will prevent any accidental
writing or clearing of the device. Data can be read normally
from the device regardless of the write enable/disable status.
The EWEN and EWDS instructions timing is shown in
Figure 4.
specified time delay (t
or t ).
PD0
PD1
For the CAT93C56/57, after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial
SK
CS
Don’t Care
A
N
A
N−1
A
0
DI
1
1
0
t
PD0
HIGH−Z
DO
Dummy 0
D
. . . D
Address + 1 Address + 2 Address + n
. . . D . . . D . . .
15
0
or
D . . . D
D
D
D
15
15
0
15
0
or
D . . . D
or
or
D . . .
7
0
D . . . D
7
7
0
0
7
Figure 3. READ Instruction Timing
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 4. EWEN/EWDS Instruction Timing
http://onsemi.com
7
CAT93C56, CAT93C57
Write
Erase
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of t . The falling edge of CS will start the
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
t
(Figure 6). The falling edge of CS will start the self
CSMIN
CSMIN
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAT93C56/57
can be determined by selecting the device and polling the
DO pin. Since this device features Auto−Clear before write,
it is NOT necessary to erase a memory location before it is
written into.
clocking clear cycle of the selected memory location. The
clocking of the SaK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
SK
CS
t
CSMIN
STANDBY
STATUS
VERIFY
A
N
A
N−1
A
0
D
D
0
N
DI
1
0
1
t
SV
t
HZ
BUSY
HIGH−Z
DO
READY
HIGH−Z
t
EW
Figure 5. Write Instruction Timing
SK
STANDBY
CS
DI
STATUS VERIFY
t
CS
A
N
A
N−1
A
0
1
1
1
t
SV
t
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 6. Erase Instruction Timing
http://onsemi.com
8
CAT93C56, CAT93C57
Erase All
Write All
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
. The falling edge of CS will start the self clocking
t
(Figure 8). The falling edge of CS will start the self
CSMIN
CSMIN
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the CAT93C56/57 can be determined by selecting the device
and polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
STATUS VERIFY
STANDBY
t
CS
DI
1
0
0
1
0
t
SV
t
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 7. ERAL Instruction Timing
SK
CS
DI
STATUS VERIFY STANDBY
t
CSMIN
1
0
0
0
1
D
D
0
N
t
SV
t
HZ
BUSY
DO
READY
HIGH−Z
t
EW
Figure 8. WRAL Instruction Timing
http://onsemi.com
9
CAT93C56, CAT93C57
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
http://onsemi.com
10
CAT93C56, CAT93C57
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
http://onsemi.com
11
CAT93C56, CAT93C57
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
b
2.03
0.25
0.48
0.25
0.05
0.36
0.19
c
E
E1
D
5.13
7.75
5.13
5.33
8.26
5.38
E
E1
e
1.27 BSC
0.51
0.76
L
0º
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
q
L
e
b
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
http://onsemi.com
12
CAT93C56, CAT93C57
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
http://onsemi.com
13
CAT93C56, CAT93C57
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
0.45
NOM
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.75
0.02
A2
0.55
0.20 REF
0.25
A3
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
D
2.00
FRONT VIEW
D2
E
1.40
3.00
E2
e
1.30
0.50 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
http://onsemi.com
14
CAT93C56, CAT93C57
PACKAGE DIMENSIONS
TDFN8, 3x3
CASE 511AL−01
ISSUE A
D
A
e
b
L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
NOM
MAX
0.80
0.05
A
A1
A3
b
0.75
0.02
0.20 REF
0.30
0.23
2.90
2.20
2.90
1.40
0.37
3.10
2.50
3.10
1.80
A
A3
D
3.00
D2
E
−−−
A1
3.00
FRONT VIEW
E2
e
−−−
0.65 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
http://onsemi.com
15
CAT93C56, CAT93C57
Example of Ordering Information
CAT93C56, Die Rev. G, New Product
Prefix
Device #
Suffix
CAT
93C56
V
I
− G
T3
Temperature Range
Lead Finish
G: NiPdAu
Blank: Matte−Tin
Tape & Reel (Note 16)
T: Tape & Reel
2: 2,000 Units / Reel (Note 14)
3: 3,000 Units / Reel
Company ID
I = Industrial (−40°C to +85°C)
E = Extended (−40°C to +125°C)
Product Number
93C56
Package
L: PDIP
V: SOIC, JEDEC
X: SOIC, EIAJ (Note 14)
Y: TSSOP
VP2: TDFN (2 x 3 mm)
9. The device used in the above example is a CAT93C56VI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel).
CAT93C56/57, Die Rev. E, Mature Product
(CAT93C56, Rev. E − Not Recommended for New Designs)
Prefix
Device #
Suffix
CAT
93C56
V
I
−1.8
− G
T3
Rev E (Note 13)
Temperature Range
Lead Finish
Die Revision
Company ID
G: NiPdAu
Blank: Matte−Tin
93C56: E
93C57: E
I = Industrial (−40°C to +85°C)
A = Automotive (−40°C to +105°C)
E = Extended (−40°C to +125°C)
Product Number
93C56
93C57
Tape & Reel (Note 16)
Package
L: PDIP
Operating Voltage
T: Tape & Reel
Blank: V = 2.5 V to 5.5 V
CC
2: 2,000 Units / Reel (Note 14)
3: 3,000 Units / Reel
V: SOIC, JEDEC
W: SOIC, JEDEC
X: SOIC, EIAJ (Note 14)
Y: TSSOP
1.8: V = 1.8 V to 5.5 V
CC
ZD4: TDFN (3 x 3 mm)
10.All packages are RoHS−compliant (Lead−free, Halogen−free).
11. The standard lead finish is NiPdAu.
12.The device used in the above example is a CAT93C56VI−1.8−GT3 (SOIC green package, Industrial Temperature, 1.8 Volt to 5.5 Volt
Operating Voltage, NiPdAu finish, Tape & Reel).
13.Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE). For additional information,
please contact your ON Semiconductor sales office.
14.For SOIC, EIAJ (X) package the standard lead finish is Matte−Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C56XI−T2.
15.For additional package and temperature options, please contact your nearest ON Semiconductor sales office.
16.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
16
CAT93C56, CAT93C57
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
CAT93C56/D
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明