CAT93C57LE-1.8-G [ONSEMI]
IC,SERIAL EEPROM,128X16/256X8,CMOS,DIP,8PIN,PLASTIC;
| 型号： | CAT93C57LE-1.8-G |
| 厂家： | 
ONSEMI |
| 描述： | IC,SERIAL EEPROM,128X16/256X8,CMOS,DIP,8PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总18页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT93C56, CAT93C57
2-Kb Microwire Serial CMOS EEPROM
FEATURES
DESCRIPTION
The CAT93C56/57 is a 2-Kb CMOS Serial EEPROM
device which is organized as either 128 registers of 16
bits (ORG pin at VCC) or 256 registers of 8 bits (ORG pin
at GND). Each register can be written (or read) serially
by using the DI (or DO) pin. The CAT93C56/57 features
sequential read and self-timed internal write with auto-
clear. On-chip Power-On Reset circuitry protects the
internal logic against powering up in the wrong state.
High speed operation: 2MHz
1.8V to 5.5V supply voltage range
Selectable x8 or x16 memory organization
Sequential read
Software write protection
Power-up inadvertant write protection
Low power CMOS technology
1,000,000 Program/erase cycles
100 year data retention
Industrial and Extended temperature ranges
For Ordering Information details, see page 16.
RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
8-pad TDFN packages
FUNCTIONAL SYMBOL
PIN CONFIGURATION
PDIP (L)
SOIC (V, X)
TSSOP (Y)
VCC
TDFN (VP2, ZD4*)
SOIC (W*)
ORG
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
NC
VCC
CS
SK
1
2
3
4
8
7
6
5
ORG
GND
DO
CS
SK
DI
DO
CAT93C56
CAT93C57
NC
ORG
GND
DO
DI
* TDFN 3x3mm (ZD4) and SOIC (W) rotated pin-out packages are
available for CAT93C57 and CAT93C56, Rev. E only (not
recommended for new designs of CAT93C56)
GND
PIN FUNCTION
Pin Name
CS
Function
Chip Select
SK
Clock Input
DI
Serial Data Input
Serial Data Output
Power Supply
Ground
DO
VCC
GND
ORG
NC
Note: When the ORG pin is connected to VCC, the x16 organization
is selected. When it is connected to ground, the x8 pin is selected. If
the ORG pin is left unconnected, then am internal pullup device will
select the x16 organization
Memory Organization
No Connection
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-1088 Rev. Q
CAT93C56, CAT93C57
Absolute Maximum Ratings(1)
Parameters
Ratings
Units
°C
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65 to +150
-0.5 to +6.5
V
Reliability Characteristics(3)
Symbol Parameter
NEND(4) Endurance
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
TDR
Data Retention
D.C. OPERATING CHARACTERISTICS, CAT93C56, Die Rev. G – New Product
CC = +1.8V to +5.5V, TA=-40°C to +125°C unless otherwise specified.
V
Symbol Parameter
Test Conditions
Min
Max
Units
Power Supply Current
(Write)
Power Supply Current
(Read)
fSK = 1MHz, VCC = 5.0V
ICC1
ICC2
ISB1
ISB2
1
mA
f
SK = 1MHz, VCC = 5.0V
500
µA
µA
TA = -40°C to +85°C
TA = -40°C to +125°C
TA = -40°C to +85°C
TA = -40°C to +125°C
TA = -40°C to +85°C
2
4
1
2
1
Power Supply Current
(Standby) (x8 Mode)
VIN = GND or VCC
,
CS = GND ORG = GND
Power Supply Current
(Standby) (x16 Mode)
VIN = GND or VCC, CS =
GND ORG = Float or VCC
µA
µA
Input Leakage Current
VIN = GND to VCC
ILI
TA = -40°C to +125°C
TA = -40°C to +85°C
TA = -40°C to +125°C
2
1
Output Leakage
Current
VOUT = GND to VCC
,
ILO
µA
CS = GND
2
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
4.5V ≤ VCC < 5.5V
4.5V ≤ VCC < 5.5V
1.8V ≤ VCC < 4.5V
1.8V ≤ VCC < 4.5V
VIL1
VIH1
VIL2
VIH2
-0.1
0.8
V
V
V
V
2
0
VCC + 1
VCC x 0.2
VCC + 1
VCC x 0.7
4.5V ≤ VCC < 5.5V,
IOL = 2.1mA
4.5V ≤ VCC < 5.5V,
IOH = -400µA
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
VOL1
VOH1
VOL2
VOH2
0.4
V
V
V
V
2.4
1.8V ≤ VCC < 4.5V,
0.2
I
OL = 1mA
1.8V ≤ VCC < 4.5V,
OH = -100µA
VCC - 0.2
I
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Block Mode, VCC = 5V, 25°C
Doc. No. MD-1088 Rev. Q
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C56, CAT93C57
D.C. OPERATING CHARACTERISTICS, CAT93C56/57, Die Rev. E – Mature Product
(CAT93C56, Rev. E – NOT RECOMMENDED FOR NEW DESIGNS)
VCC = +1.8V to +5.5V, TA=-40°C to +125°C unless otherwise specified.
Symbol Parameter
ICC1 Power Supply Current (Write)
ICC2
Test Conditions
Min
Max
3
Units
mA
fSK = 1MHz, VCC = 5.0V
fSK = 1MHz, VCC = 5.0V
Power Supply Current (Read)
500
µA
Power Supply Current
(Standby) (x8 Mode)
VIN = GND or VCC, CS = GND
ORG = GND
ISB1
ISB2
10
10
µA
µA
Power Supply Current
(Standby) (x16 Mode)
VIN = GND or VCC, CS = GND
ORG = Float or VCC
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND to VCC
VOUT = GND to VCC, CS = GND
4.5V ≤ VCC < 5.5V
1
1
µA
µA
V
ILO
VIL1
VIH1
VIL2
VIH2
VOL1
VOH1
VOL2
VOH2
-0.1
0.8
Input High Voltage
Input Low Voltage
4.5V ≤ VCC < 5.5V
2
0
VCC + 1
VCC x 0.2
VCC + 1
0.4
V
1.8V ≤ VCC < 4.5V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
1.8V ≤ VCC < 4.5V
VCC x 0.7
V
4.5V ≤ VCC < 5.5V, IOL = 2.1mA
4.5V ≤ VCC < 5.5V, IOH = -400µA
1.8V ≤ VCC < 4.5V, IOL = 1mA
1.8V ≤ VCC < 4.5V, IOH = -100µA
V
2.4
V
0.2
V
VCC - 0.2
V
PIN CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 5V
Symbol Test
Conditions
VOUT = 0V
VIN = 0V
Min
Typ
Max
5
Units
pF
(1)
COUT
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
(1)
CIN
5
pF
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-1088 Rev. Q
CAT93C56, CAT93C57
A.C. CHARACTERISTICS(1), CAT93C56, Die Rev. G – New Product
VCC = +1.8V to +5.5V, TA = -40°C to +125°C, unless otherwise specified.
Limits
Symbol Parameter
Units
ns
Min
50
Max
tCSS
tCSH
tDIS
CS Setup Time
CS Hold Time
0
ns
DI Setup Time
100
100
ns
tDIH
tPD1
tPD0
DI Hold Time
ns
Output Delay to 1
0.25
0.25
100
5
µs
Output Delay to 0
µs
(2)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
tEW
tCSMIN
tSKHI
ms
µs
0.25
0.25
0.25
µs
tSKLOW
tSV
µs
0.25
µs
SKMAX
DC
2000
kHz
A.C. CHARACTERISTICS (1), CAT93C56/57, Die Rev. E – Mature Product
(CAT93C56 Rev. E - NOT RECOMMENDED FOR NEW DESIGNS)
Limits
Symbol Parameter
Units
VCC = 1.8V - 5.5V
VCC = 2.5V - 5.5V
VCC = 4.5V - 5.5V
Min
200
0
Max
Min
100
0
Max
Min
50
Max
tCSS
tCSH
tDIS
CS Setup Time
ns
ns
CS Hold Time
0
DI Setup Time
400
400
200
200
100
100
ns
tDIH
tPD1
tPD0
DI Hold Time
ns
Output Delay to 1
1
1
0.5
0.5
200
10
0.25
0.25
100
10
µs
µs
ns
Output Delay to 0
(2)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
400
10
tEW
tCSMIN
tSKHI
ms
µs
µs
µs
µs
kHz
1
1
1
0.5
0.5
0.5
0.25
0.25
0.25
tSKLOW
tSV
1
0.5
0.25
SKMAX
DC
250
DC
500
DC
1000
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
Doc. No. MD-1088 Rev. Q
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C56, CAT93C57
POWER-UP TIMING(1) (2)
Symbol
tPUR
Parameter
Max
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
tPUW
1
ms
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
A.C. Test Conditions
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
50 ns
≤
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
Current Source IOLmax/IOHmax; CL=100pF
DEVICE OPERATION
The CAT93C56/57 is a 2048-bit nonvolatile memory
intended for use with industry standard micropro-
cessors. The CAT93C56/57 can be organized as
either registers of 16 bits or 8 bits. When organized as
X16, seven 10-bit instructions for 93C57 or seven 11-
bit instructions for 93C56 control the reading, writing
and erase operations of the device. When organized
as X8, seven 11-bit instructions for 93C57 or seven
12-bit instructions for 93C56 control the reading,
writing and erase operations of the device. The
CAT93C56/57 operates on a single power supply and
will generate on chip, the high voltage required during
any write operation.
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The serial communication protocol follows the timing
shown in Figure 1.
The ready/busy status can be determined after the start
of internal write cycle by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state
on the rising edge of the clock (SK). Placing the DO pin
into the high impedance state is recommended in
applications where the DI pin and the DO pin are to be
tied together to form a common DI/O pin.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
Figure 1. Sychronous Data Timing
t
t
t
CSH
SKLOW
SKHI
SK
t
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
t
CSMIN
DIS
PD0, PD1
DO
DATA VALID
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-1088 Rev. Q
CAT93C56, CAT93C57
The format for all instructions sent to the device is a
logical “1” start bit, a 2-bit (or 4-bit) opcode, 7-bit
address (CAT93C57) / 8-bit address (CAT93C56) (an
additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organi–
zations). The instruction format is shown in Instruction
Set table.
INSTRUCTION SET
Device Start
Address
Data
Instruction
Type
93C56(1)
93C57
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Opcode
10
Comments
x8
x16
x8
x16
READ
A8-A0
A7-A0
A8-A0
A7-A0
A8-A0
A7-A0
A7-A0
A6-A0
A7-A0
A6-A0
A7-A0
A6-A0
Read Address
AN–A0
10
ERASE
WRITE
EWEN
EWDS
ERAL
93C56(1)
11
Clear Address
AN–A0
93C57
11
93C56(1)
93C57
93C56(1)
01
D7-D0
D7-D0
D15-D0
D15-D0
Write Address
AN–A0
01
00
11XXXXXXX 11XXXXXX
11XXXXXX 11XXXXX
00XXXXXXX 00XXXXXX
00XXXXXX 00XXXXX
10XXXXXXX 10XXXXXX
10XXXXXX 10XXXXX
01XXXXXXX 01XXXXXX
01XXXXXX 01XXXXX
Write Enable
Write Disable
93C57
00
93C56(1)
93C57
93C56(1)
00
00
00
Clear All
Addresses
93C57
00
WRAL
93C56(1)
93C57
00
D7-D0
D7-D0
D15-D0
D15-D0
Write All
Addresses
00
Note:
(1) Address bit A8 for 256x8 organization and A7 for 128x16 organization are "Don't Care" bits, but must be kept at either a "1" or "0" for
READ, WRITE and ERASE commands.
Doc. No. MD-1088 Rev. Q
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C56, CAT93C57
address space, then loops back to address 0. In the
sequential READ mode, only the initial data word is
preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 2.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the
CAT93C56/57 will come out of the high impedance
state and, after sending an initial dummy zero bit, will
begin shifting out the data addressed (MSB first). The
output data bits will toggle on the rising edge of the
SK clock and are stable after the specified time delay
(tPD0 or tPD1).
Erase/Write Enable and Disable
The CAT93C56/57 powers up in the write disable state.
Any writing after power-up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C56/57 write and erase instructions, and will
prevent any accidental writing or clearing of the device.
Data can be read normally from the device regardless of
the write enable/disable status. The EWEN and EWDS
instructions timing is shown in Figure 3.
For the CAT93C56/57, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will auto-
matically increment to the next address and shift out
the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues
to toggle, the device will keep incrementing to the next
address automatically until it reaches to the end of the
Figure 2. READ Instruction Timing
SK
CS
Don't Care
A
A
A
0
N
N–1
DI
1
1
0
tPD0
HIGH-Z
DO
Dummy 0
D
D
Address + 1 Address + 2 Address + n
15 . . .
0
or
D
D
D
D
D
15 . . .
0
15 . . .
0
15 . . .
D
D
0
or
or
or
7 . . .
D
D
D
D
D
7 . . .
7 . . .
0
7 . . .
0
Figure 3. EWEN/EWDS Instruction Timing
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. MD-1088 Rev. Q
CAT93C56, CAT93C57
Write
Erase
After receiving a WRITE command (Figure 4), address
and the data, the CS (Chip Select) pin must be
deselected for a minimum of tCSMIN. The falling edge of
CS will start the self clocking clear and data store cycle
of the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C56/57 can be determined by
selecting the device and polling the DO pin. Since this
device features Auto-Clear before write, it is NOT
necessary to erase a memory location before it is
written into.
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a
minimum of tCSMIN (Figure 5). The falling edge of CS will
start the self clocking clear cycle of the selected
memory location. The clocking of the SaK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C56/57 can
be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Figure 4. Write Instruction Timing
SK
t
CSMIN
STANDBY
STATUS
VERIFY
CS
A
A
A
0
D
D
0
N
N-1
N
DI
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
Figure 5. Erase Instruction Timing
SK
STANDBY
STATUS VERIFY
CS
t
CS
A
A
0
A
N
N-1
DI
1
1
1
t
t
SV
HZ
HIGH-Z
DO
BUSY
EW
READY
HIGH-Z
t
Doc. No. MD-1088 Rev. Q
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C56, CAT93C57
Erase All
Write All
Upon receiving an ERAL command (Figure 6), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C56/57 can be deter-
mined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to
a logical “1” state.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 7). The falling edge of CS will start the
self clocking data write to all memory locations in the
device. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C56/57 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CS
DI
1
0
0
1
0
t
t
HZ
SV
HIGH-Z
DO
BUSY
READY
HIGH-Z
t
EW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CSMIN
D
D
0
DI
1
0
0
0
1
N
t
t
SV
HZ
DO
BUSY
READY
HIGH-Z
t
EW
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. MD-1088 Rev. Q
CAT93C56, CAT93C57
PACKAGE OUTLINE DRAWINGS
PDIP 8-Lead 300mils (L) (1)
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
5.33
0.38
2.92
0.36
1.14
0.20
9.02
7.62
3.30
0.46
4.95
0.56
1.78
0.36
10.16
8.25
b2
c
1.52
E1
0.25
D
9.27
E
7.87
e
2.54 BSC
6.35
E1
eB
L
6.10
7.87
2.92
7.11
10.92
3.80
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC standard MS-001.
Doc. No. MD-1088 Rev. Q
10
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C56, CAT93C57
SOIC 8-Lead 150mils (V, W) (1)
SYMBOL
MIN
NOM
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
A
A1
b
1.35
0.10
0.33
0.19
4.80
5.80
3.80
c
E1
E
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-012.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-1088 Rev. Q
CAT93C56, CAT93C57
(1)
SOIC 8-Lead EIAJ (208mils) (X)
SYMBOL
MIN
NOM
MAX
2.03
0.25
0.48
0.25
5.33
8.26
5.38
A
A1
b
0.05
0.36
0.19
5.13
7.75
5.13
c
E
E1
D
E
E1
e
1.27 BSC
L
0.51
0º
0.76
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
θ
e
b
L
A1
c
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320
Doc. No. MD-1088 Rev. Q
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C56, CAT93C57
(1)
TSSOP 8-Lead 4.4mm (Y)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.40
E
E1
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
θ1
0.50
0°
0.75
8°
e
TOP VIEW
D
c
A2
A1
A
θ1
L1
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. MD-1088 Rev. Q
CAT93C56, CAT93C57
TDFN 8-Pad 2 x 3mm (VP2) (1)
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
0.45
NOM
0.75
0.02
0.55
MAX
0.80
0.05
0.65
A2
A
A1
A2
A3
b
A3
0.20 REF
0.25
FRONT VIEW
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
D
2.00
D2
E
1.40
3.00
E2
e
1.30
050TYP
0.30
L
0.20
0.40
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC standard MO-229.
Doc. No. MD-1088 Rev. Q
14
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C56, CAT93C57
TDFN 8-Pad 3 x 3mm (ZD4) (1)
D
A
e
b
L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
NOM
0.75
MAX
0.80
0.05
A
A
A1
A3
b
0.70
0.00
A3
0.02
A1
0.20 REF
0.30
FRONT VIEW
0.23
2.90
2.20
2.90
1.40
0.37
3.10
2.50
3.10
1.80
D
3.00
D2
E
—
3.00
E2
e
—
0.65TYP
0.30
L
0.20
0.40
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. MD-1088 Rev. Q
CAT93C56, CAT93C57
EXAMPLE OF ORDERING INFORMATION
CAT93C56, Die Rev. G, New Product
Prefix
Device # Suffix
CAT
93C56
V
I
-G
T3
Package
L: PDIP
V: SOIC, JEDEC
X: SOIC, EIAJ(4)
Y: TSSOP
Temperature Range
I = Industrial (-40ºC to +85ºC)
E = Extended (-40ºC to +125ºC)
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Company ID
Product Number
93C56
Tape & Reel
T: Tape & Reel
VP2: TDFN (2x3mm)
2: 2,000 units/Reel(4)
3: 3,000 units/Reel
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT93C56VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C56XI-T2.
(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
CAT93C56/57, Die Rev. E, Mature Product
(CAT93C56, Rev. E – Not Recommended for new Designs)
Prefix
Device # Suffix
93C56
CAT
V
I
-1.8
-G T3
Rev E(4)
Temperature Range
I = Industrial (-40ºC to 85ºC)
A = Automotive (-40ºC to 105ºC)
E = Extended (-40ºC to 125ºC)
Die Revision
93C56: E
93C57: E
Company ID
Product Number
93C56
93C57
Tape & Reel
Package
L: PDIP
V: SOIC, JEDEC
W: SOIC, JEDEC
X: SOIC, EIAJ(5)
Y: TSSOP
Operating Voltage
Blank: VCC = 2.5V to 5.5V
1.8: VCC = 1.8V to 5.5V
T: Tape & Reel
2: 2,000 units/Reel(5)
3: 3,000 units/Reel
Lead Finish
Blank: Matte-Tin
G: NiPdAu
ZD4: TDFN (3x3mm)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard finish is NiPdAu.
(3) The device used in the above example is a CAT93C56VI-1.8-GT3 (SOIC green package, Industrial Temperature, 1.8 Volt to 5.5 Volt
Operating Voltage, NiPdAu finish, Tape & Reel.)
(4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE). For additional informa-
tion, please contact your Catalyst sales office.
(5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C56XI-T2.
(6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Doc. No. MD-1088 Rev. Q
16
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C56, CAT93C57
REVISION HISTORY
Date
Rev. Comments
05/14/04
L
New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56,
CAT93C57, CAT93C56/57, CAT93C76 and CAT93C86 have been separated into
single data sheets
10/13/06
03/18/05
10/13/06
M
N
O
Updated Instruction Set
Updated Description
Update Features
Update Pin Configuration
Update Functional Symbol
Update Pin Functions
Update D.C. Operating Characteristics (VCC Range)
Update A.C. Characteristics (VCC Range)
Update Ordering Information
Updated Features/Description
08/21/07
P
Remove "Die Rev E" from the title
Update Pin Configuration / Packages
Update Absolute Maximum Rating
Update Reliability Characteristics
Update D.C. Operating Characteristics
Added D.C. / A.C. Characteristics for CAT93C56 Die Rev G
Rearrange / Format Text and Figures
Update Package Outline Drawings
Added Example of Ordering Information for CAT93C56 Die Rev. G
Add MD- to document number
Add Extended Temperature Range
Update Package Outline Drawings
04/10/08
Q
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
17
Doc. No. MD-1088 Rev. Q
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™
I2C™ is a trademark of Philips Corporation. Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where
personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Document No: MD-1088
Revision:
Q
Issue date:
04/10/08
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