CAT93C86LI-1.8C [ONSEMI]
IC,SERIAL EEPROM,1KX16/2KX8,CMOS,DIP,8PIN,PLASTIC;
| 型号： | CAT93C86LI-1.8C |
| 厂家： | 
ONSEMI |
| 描述： | IC,SERIAL EEPROM,1KX16/2KX8,CMOS,DIP,8PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总13页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT93C86 (Rev. C)
16K-Bit Microwire Serial EEPROM
FEATURES
DESCRIPTION
High speed operation: 3MHz
Low power CMOS technology
1.8 to 5.5 volt operation
The CAT93C86 is a 16K-bit Serial EEPROM memory
device which is configured as either registers of 16
bits (ORG pin at VCC) or 8 bits (ORG pin at GND).
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT93C86 is manufactured
using Catalyst’s advanced CMOS EEPROM floating
gate technology. The device is designed to endure
1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, 8-pin SOIC and 8-pad TDFN packages.
Selectable x8 or x16 memory organization
Self-timed write cycle with auto-clear
Hardware and software write protection
Power-up inadvertant write protection
Sequential read
Program enable (PE) pin
1,000,000 Program/erase cycles
100 year data retention
Commercial, industrial and automotive
temperature ranges
RoHS-compliant packages
PIN CONFIGURATION
FUNCTIONAL SYMBOL
VCC
PDIP (L)
SOIC (V, X)
TDFN (ZD4)
SOIC (W)
ORG
CS
DI
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
PE
VCC
CS
SK
1
2
3
4
8
7
6
5
ORG
GND
DO
DO
PE
SK
ORG
GND
PE
DO
DI
GND
PIN FUNCTION (1)
Pin Name
CS
Function
Chip Select
Clock Input
SK
For Ordering Information details, see page 12.
DI
Serial Data Input
Serial Data Output
Power Supply
Ground
DO
VCC
GND
ORG
PE
Memory Organization
Program Enable
Notes:
(1) When the ORG pin is connected to VCC, x16 organization is
selected. When it is connected to ground, x8 pin is selected.
If the ORG pin is left unconnected, then an internal pull-up
device will select the x16 organization.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
1
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
ABSOLUTE MAXIMUM RATINGS (1)
Parameters
Ratings
–55 to +125
–65 to 150
-2.0 to +VCC +2.0
-2.0 to +7.0
1.0
Units
ºC
ºC
V
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground(2)
VCC with Respect to Ground
V
Package Power Dissipation Capability (TA = 25ºC)
Lead Soldering Temperature (10 seconds)
Output Short Circuit Current(3)
W
300
ºC
mA
100
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Units
(4)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1,000,000
100
Cycles/Byte
(4)
TDR
Data Retention
ESD Susceptibility
Latch-Up
Years
V
(4)
VZAP
2000
(4)(5)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V unless otherwise specified.
Symbol
ICC1
Parameter
Test Conditions
Min
Typ
Max
3
Units
fSK = 1MHz; VCC = 5.0V
fSK = 1MHz; VCC = 5.0V
Power Supply Current (Write)
Power Supply Current (Read)
mA
µA
ICC2
500
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
CS = 0V ORG = GND
ISB1
10
µA
CS = 0V ORG = Float or VCC
VIN = 0V to VCC
ISB2
ILI
0
10
1
µA
µA
µA
Input Leakage Current
Output Leakage Current
(Including ORG pin)
VOUT = 0V to VCC, CS = 0V
ILO
1
4.5V ≤ VCC < 5.5V
VIL1
VIH1
VIL2
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
-0.1
0.8
VCC + 1
VCC x 0.2
VCC + 1
0.4
V
V
V
V
V
V
V
V
4.5V ≤ VCC < 5.5V
2
0
1.8V ≤ VCC < 4.5V
1.8V ≤ VCC < 4.5V
VIH2
VOL1
VOH1
VOL2
VOH2
VCC x 0.7
4.5V ≤ VCC < 5.5V; IOL = 2.1mA
4.5V ≤ VCC < 5.5V; IOH = -400µA
1.8V ≤ VCC < 4.5V; IOL = 1mA
1.8V ≤ VCC < 4.5V; IOH = -100µA
2.4
0.2
VCC - 0.2
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) These parameters are tested initially and after a design or process change that affects the parameter.
(5) Latch-up protection is provided for stresses up to 100 mA pn address and data pins from –1V to VCC +1V.
Doc. No. MD-1091 Rev. R
2
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT93C86 (Rev. C)
PIN CAPACITANCE (1)
Symbol Test
Conditions
VOUT = 0V
VIN = 0V
Min
Typ
Max
5
Units
pF
COUT
CIN
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
5
pF
POWER-UP TIMING (1)(2)
Symbol
tPUR
Parameter
Max
Units
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
tPUW
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
A.C. CHARACTERISTICS
VCC
=
VCC
=
VCC
=
1.8V-5.5V
2.5V-5.5V
4.5V-5.5V
Test
Symbol Parameter
Conditions
Units
ns
Min
Max
Min
Max
Min Max
tCSS
tCSH
tDIS
CS Setup Time
200
0
100
0
50
0
CS Hold Time
ns
DI Setup Time
200
200
100
100
50
50
ns
tDIH
tPD1
tPD0
DI Hold Time
ns
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
1
1
0.5
0.5
200
5
0.15
0.15
100
5
µs
CL = 100pF(3)
µs
(1)
tHZ
400
5
ns
tEW
ms
µs
tCSMIN Minimum CS Low Time
tSKHI Minimum SK High Time
tSKLOW Minimum SK Low Time
tSV Output Delay to Status Valid
SKMAX Maximum Clock Frequency
1
1
1
0.5
0.5
0.5
0.15
0.15
0.15
µs
µs
1
0.5
0.1
µs
DC
500
DC
1000
DC
3000
kHz
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
3
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
INSTRUCTION SET
Start
Address
Data
Instruction
Bit
Opcode
10
Comments
x8
x16
x8
x16
READ
1
A10-A0
A10-A0
A10-A0
A9-A0
A9-A0
A9-A0
Read Address AN– A0
Clear Address AN– A0
ERASE
WRITE
EWEN
EWDS
ERAL
1
11
1
01
D7-D0 D15-D0 Write Address AN– A0
Write Enable
1
00
11XXXXXXXXX 11XXXXXXXX
00XXXXXXXXX 00XXXXXXXX
10XXXXXXXXX 10XXXXXXXX
1
00
Write Disable
1
00
Clear All Addresses
WRAL
1
00
01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0 Write All Addresses
DEVICE OPERATION
The CAT93C86 is a 16,384-bit nonvolatile memory
intended for use with industry standard
is in Program Enabled mode. For Write Enable and
Write Disable instruction PE = don’t care.
microprocessors. The CAT93C86 can be organized
as either registers of 16 bits or 8 bits. When organized
as X16, seven 13-bit instructions control the reading,
writing and erase operations of the device. When
organized as X8, seven 14-bit instructions control the
reading, writing and erase operations of the device.
The CAT93C86 operates on a single power supply
and will generate on chip, the high voltage required
during any write operation.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C86
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data
bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (tPD0 or tPD1).
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to
toggle, the device will automatically increment to the
next address and shift out the next data word in a
sequential READ mode. As long as CS is
continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches to the end of the address
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The ready/busy status can be determined after the
start of a write operation by selecting the device (CS
high) and polling the DO pin; DO low indicates that the
write operation is not completed, while DO high
indicates that the device is ready for the next
instruction. If necessary, the DO pin may be placed
back into a high impedance state during chip select by
shifting a dummy “1” into the DI pin. The DO pin will
enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high
impedance state is recommended in applications
where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
space, then loops back to address 0.
In the
sequential READ mode, only the initial data word is
preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for
a minimum of tCSMIN. The falling edge of CS will start
the self clocking clear and data store cycle of the
memory location specified in the instruction. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO
pin. Since this device features Auto-Clear before
write, it is NOT necessary to erase a memory location
before it is written into.
The format for all instructions sent to the device is a
logical “1” start bit, a 2-bit (or 4-bit) opcode, 10-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations).
Note: The Write, Erase, Write all and Erase all
instructions require PE=1. If PE is left floating, 93C86
Doc. No. MD-1091 Rev. R
4
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT93C86 (Rev. C)
t
t
t
CSH
SKLOW
SKHI
SK
t
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
t
CSMIN
DIS
PD0, PD1
DO
DATA VALID
Figure 1. Sychronous Data Timing
SK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CS
DI
Don't Care
A
A
A
0
N
-–1
1
1
0
HIGH-Z
DO
Dummy 0
D
D
Address + 1 Address + 2 Address + n
15 . . .
0
or
D
D
D
D
D
15 . . .
0
15 . . .
0
15 . . .
D
D
0
or
or
D
or
7 . . .
D
D
D
D
7 . . .
7 . . .
0
7 . . .
0
Figure 2. Read Instruction Timing
SK
t
CSMIN
STANDBY
STATUS
VERIFY
CS
DI
A
N
A
N-1
A
0
D
D
0
N
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
Figure 3. Write Instruction Timing
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
5
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
Erase All
Erase
Upon receiving an ERAL command, the CS (Chip
Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO
pin. Once cleared, the contents of all memory bits
return to a logical “1” state.
Upon receiving an ERASE command and address,
the CS (Chip Select) pin must be deasserted for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear cycle of the selected memory
location. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO
pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Write All
Erase/Write Enable and Disable
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
The CAT93C86 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the
EWEN (write enable) instruction. Once the write
instruction is enabled, it will remain enabled until
power to the device is removed, or the EWDS
instruction is sent. The EWDS instruction can be used
to disable all CAT93C86 write and clear instructions,
and will prevent any accidental writing or clearing of
the device. Data can be read normally from the device
regardless of the write enable/disable status.
SK
CS
STANDBY
STATUS VERIFY
t
CS
A
A
0
A
N
N-1
DI
1
1
1
t
t
SV
HZ
HIGH-Z
DO
BUSY
EW
READY
HIGH-Z
t
Figure 4. Erase Instruction Timing
Doc. No. MD-1091 Rev. R
6
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT93C86 (Rev. C)
PACKAGE OUTLINE DRAWINGS
PDIP 8-Lead 300mils (L) (1)(2)
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
5.33
0.38
2.92
0.36
1.14
0.20
9.02
7.62
3.30
0.46
4.95
0.56
1.78
0.36
10.16
8.25
b2
c
1.52
E1
0.25
D
9.27
E
7.87
e
2.54 BSC
6.35
E1
eB
L
6.10
7.87
2.92
7.11
10.92
3.80
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-001.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
7
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
SOIC 8-Lead 150mils (V) (1)(2)
SYMBOL
MIN
NOM
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
A
A1
b
1.35
0.10
0.33
0.19
4.80
5.80
3.80
c
E1
E
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-012.
Doc. No. MD-1091 Rev. R
8
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT93C86 (Rev. C)
SOIC 8-Lead EIAJ 208mils (X) (1)(2)
SYMBOL
MIN
NOM
MAX
2.03
0.25
0.48
0.25
5.33
8.26
5.38
A
A1
b
0.05
0.36
0.19
5.13
7.75
5.13
c
E
E1
D
E
E1
e
1.27 BSC
L
0.51
0º
0.76
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
θ
e
b
L
A1
c
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ standard EDR-7320.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
9
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
TDFN 8-Pad 3 x 3mm (ZD4) (1)(2)
D
A
e
b
L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
NOM
0.75
MAX
0.80
0.05
A
A
A1
A3
b
0.70
0.00
A3
0.02
A1
0.20 REF
0.30
FRONT VIEW
0.23
2.90
2.20
2.90
1.40
0.37
3.10
2.50
3.10
1.80
D
3.00
D2
E
—
3.00
E2
e
—
0.65TYP
0.30
L
0.20
0.40
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-229.
Doc. No. MD-1091 Rev. R
10
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT93C86 (Rev. C)
EXAMPLE OF ORDERING INFORMATION(1)
Prefix
Device # Suffix
CAT
93C86
V
I
-1.8
-G
T3 Rev C (4)
Temperature Range
I = Industrial (-40°C - 85°C)
A = Automotive (-40°C - 105°C)
E = Extended (-40°C to + 125°C)
Company ID
Die Revision
93C86: C
Product Number
93C86
Tape & Reel
T: Tape & Reel
2: 2,000/Reel(5)
3: 3,000/Reel
Operating Voltage
Blank (VCC = 2.5V to 5.5V)
1.8 (VCC = 1.8V to 5.5V)
Package
L = PDIP
V = SOIC, JEDEC
W = SOIC, JEDEC
X = SOIC, EIAJ(5)
Lead Finish
Blank: Matte-Tin
G: NiPdAu
ZD4 = TDFN (3x3mm)
For Product Top Mark Codes, click here:
http://www.catsemi.com/techsupport/producttopmark.asp
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a 93C86VI-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V, NiPdAu, Tape & Reel, 3,000/Reel)
(4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional
information, please contact your ON Semiconductor sales office.
(5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000/Reel, i.e., CAT93C86XI-T2.
(6) For additional package and temperature options, please contact your nearest ON Semiconductor sales office.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
11
Doc. No. MD-1091 Rev. R
CAT93C86 (Rev. C)
REVISION HISTORY
Date
Rev. Comments
New Data Sheet Created From CAT93C46/56/57/66/86. Parts
CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and
CAT93C86 have been separated into single data sheets
Add Die Revision ID Letter
Update Features
Update Description
Update Pin Condition
Add Functional Diagram
14-May-04
L
Update Pin Function
Update D.C. Operating Characteristics
Update Pin Capacitance
Update Instruction Set
Update Device Operation
Update Ordering Information
Added TDFN Package pin out
Minor changes
10-Aug-04
03-Sep-04
M
N
Update Features
Update Pin Configuration
Update Pin Functions
13-Oct-06
O
Update D.C. Operating Characteristics (VCC Range)
Update A.C. Characteristics (VCC Range)
Update Ordering Information
Update Package Outline Drawings
Add Top Mark Code Link
Update Document Layout
21-May-08
29-Oct-08
P
R
Change logo and fine print to ON Semiconductor
Doc. No. MD-1091 Rev. R
12
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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