CAT93C86PA [ONSEMI]
1KX16 MICROWIRE BUS SERIAL EEPROM, PDIP8, PLASTIC, DIP-8;
| 型号： | CAT93C86PA |
| 厂家： | 
ONSEMI |
| 描述： | 1KX16 MICROWIRE BUS SERIAL EEPROM, PDIP8, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT93C86
16 Kb Microwire Serial
EEPROM
Description
The CAT93C86 is a 16 Kb Serial EEPROM memory device which
is configured as either registers of 16 bits (ORG pin at V ) or 8 bits
CC
http://onsemi.com
(ORG pin at GND). Each register can be written (or read) serially by
using the DI (or DO) pin. The CAT93C86 is manufactured using
ON Semiconductor’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000 program/erase
cycles and has a data retention of 100 years. The device is available in
8−pin DIP and 8−pin SOIC packages.
SOIC−8
V, W SUFFIX
CASE 751BD
Features
• High Speed Operation: 3 MHz / V = 5 V
CC
• Low Power CMOS Technology
• 1.8 V to 5.5 V Operation
• Selectable x8 or x16 Memory Organization
• Self−timed Write Cycle with Auto−clear
• Hardware and Software Write Protection
• Power−up Inadvertent Write Protection
• Sequential Read
PDIP−8
L SUFFIX
CASE 646AA
SOIC−8
X SUFFIX
CASE 751BE
PIN CONFIGURATION
• Program Enable (PE) Pin
1
1
CS
SK
DI
V
PE
ORG
GND
DO
CC
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
PE
V
CC
ORG
GND
CS
• Industrial and Extended Temperature Ranges
• 8−lead PDIP and SOIC Packages
DO
SK
DI
PDIP (L), SOIC (V, X)
SOIC (W)*
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
PIN FUNCTION
V
CC
Pin Name
Function
CS
SK
DI
Chip Select
Clock Input
ORG
CS
DI
Serial Data Input
Serial Data Output
Power Supply
Ground
CAT93C86
DO
SK
DO
PE
V
CC
GND
ORG
PE
Memory Organization
Program Enable
GND
Figure 1. Functional Symbol
Note: When the ORG pin is connected to V , the x16 organization
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
is selected. When it is connected to ground, the x8 pin is selected. If
the ORG pin is left unconnected, then an internal pull−up device will
select the x16 organization.
* Not Recommended for New Designs
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
October, 2013 − Rev. 12
CAT93C86/D
CAT93C86
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
°C
V
Temperature Under Bias
−55 to +125
−65 to +150
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
−2.0 to +V +2.0
CC
V
with Respect to Ground
−2.0 to +7.0
1.0
V
CC
Package Power Dissipation Capability (T = 25°C)
W
A
Lead Soldering Temperature (10 seconds)
Output Short Circuit Current (Note 2)
300
°C
mA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns.
CC
CC
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
(Note 3)
Parameter
Endurance
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Units
Cycles/Byte
Years
N
END
T
(Note 3)
(Note 3)
Data Retention
ESD Susceptibility
Latch−Up
DR
V
2000
V
ZAP
I
(Notes 3, 4)
100
mA
LTH
3. These parameters are tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V +1 V.
CC
Table 3. D.C. OPERATING CHARACTERISTICS (V = +1.8 V to +5.5 V unless otherwise specified.)
CC
Symbol
Parameter
Test Conditions
= 1 MHz; V = 5.0 V
Min
Typ
Max
Units
I
Power Supply Current (Write)
Power Supply Current (Read)
f
f
3
mA
mA
mA
CC1
CC2
SK
CC
I
= 1 MHz; V = 5.0 V
500
10
SK
CC
I
Power Supply Current
(Standby) (x8 Mode)
CS = 0 V ORG = GND
SB1
I
Power Supply Current
(Standby) (x16 Mode)
CS = 0 V ORG = Float or V
0
10
mA
SB2
CC
I
Input Leakage Current
V
V
= 0 V to V
CC
1
1
mA
mA
LI
IN
I
LO
Output Leakage Current
(Including ORG pin)
= 0 V to V , CS = 0 V
OUT CC
V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
4.5 V ≤ V < 5.5 V
−0.1
2
0.8
V
V
V
V
V
V
V
V
IL1
CC
V
IH1
4.5 V ≤ V < 5.5 V
V
+ 1
CC
CC
V
1.8 V ≤ V < 4.5 V
0
V
x 0.2
IL2
IH2
CC
CC
V
1.8 V ≤ V < 4.5 V
V
V
x 0.7
V
+ 1
CC
CC
CC
V
4.5 V ≤ V < 5.5 V; I = 2.1 mA
0.4
OL1
OH1
CC
OL
V
4.5 V ≤ V < 5.5 V; I = −400 mA
2.4
CC
OH
V
1.8 V ≤ V < 4.5 V; I = 1 mA
0.2
OL2
OH2
CC
OL
V
1.8 V ≤ V < 4.5 V; I = −100 mA
− 0.2
CC
CC
OH
http://onsemi.com
2
CAT93C86
Table 4. PIN CAPACITANCE (Note 5)
Symbol Test
Conditions
= 0 V
Min
Typ
Max
5
Units
pF
C
Output Capacitance (DO)
V
OUT
OUT
C
Input Capacitance (CS, SK, DI, ORG)
V
IN
= 0 V
5
pF
IN
Table 5. POWER−UP TIMING (Notes 5, 6)
Symbol Parameter
Max
1
Units
t
Power−up to Read Operation
Power−up to Write Operation
ms
ms
PUR
t
1
PUW
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
4.5 V ≤ V ≤ 5.5 V
CC
Timing Reference Voltages
Input Pulse Voltages
4.5 V ≤ V ≤ 5.5 V
CC
0.2 x V to 0.7 x V
1.8 V ≤ V ≤ 4.5 V
CC
CC
CC
Timing Reference Voltages
0.5 x V
1.8 V ≤ V ≤ 4.5 V
CC
CC
Table 7. A.C. CHARACTERISTICS
V
CC
=
V
CC
=
V
CC
=
1.8 V − 5.5 V
2.5 V − 5.5 V
4.5 V − 5.5 V
Min
200
0
Max
Min
100
0
Max
Min
50
0
Max
Symbol
Parameter
CS Setup Time
Test Conditions
Units
ns
t
CSS
t
CS Hold Time
ns
CSH
t
DI Setup Time
200
200
100
100
50
50
ns
DIS
t
DI Hold Time
ns
DIH
t
Output Delay to 1
1
1
0.5
0.5
200
5
0.15
0.15
100
5
ms
PD1
PD0
t
Output Delay to 0
C = 100 pF (Note 7)
L
ms
t
(Note 5)
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
400
5
ns
HZ
t
ms
ms
EW
t
1
1
1
0.5
0.5
0.5
0.15
0.15
0.15
CSMIN
t
ms
SKHI
t
ms
SKLOW
t
1
0.5
0.1
ms
SV
SK
DC
500
DC
1000
DC
3000
kHz
MAX
5. These parameters are tested initially and after a design or process change that affects the parameter.
6. t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW CC
7. The input levels and timing reference points are shown in the “A.C. Test Conditions” table.
http://onsemi.com
3
CAT93C86
Table 8. INSTRUCTION SET
Start
Address
Data
x8
x16
x8
x16
Bit
Instruction
Opcode
Comments
Read Address AN– A0
Clear Address AN– A0
Write Address AN– A0
Write Enable
READ
1
10
A10−A0
A9−A0
ERASE
WRITE
EWEN
EWDS
ERAL
1
11
A10−A0
A9−A0
1
01
A10−A0
A9−A0
D7−D0
D15−D0
1
00
11XXXXXXXXX
00XXXXXXXXX
10XXXXXXXXX
01XXXXXXXXX
11XXXXXXXX
00XXXXXXXX
10XXXXXXXX
01XXXXXXXX
1
00
Write Disable
1
00
Clear All Addresses
Write All Addresses
WRAL
1
00
D7−D0
D15−D0
Read
Device Operation
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C86 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
The CAT93C86 is a 16,384−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C86 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 13−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
14−bit instructions control the reading, writing and erase
operations of the device. The CAT93C86 operates on a
single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
specified time delay (t
or t ).
PD0
PD1
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
device will automatically increment to the next address and
shift out the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues to
toggle, the device will keep incrementing to the next address
automatically until it reaches to the end of the address space,
then loops back to address 0. In the sequential READ mode,
only the initial data word is preceeded by a dummy zero bit.
All subsequent data words will follow without a dummy
zero bit.
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of t
. The falling edge of CS will start the self clocking
CSMIN
clear and data store cycle of the memory location specified
in the instruction. The clocking of the SK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO pin.
Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
Note: The Write, Erase, Write all and Erase all instructions
require PE = 1. If PE is left floating, 93C86 is in Program
Enabled mode. For Write Enable and Write Disable
instruction PE = don’t care.
http://onsemi.com
4
CAT93C86
t
t
t
SKHI
SKLOW
CSH
SK
t
t
DIH
DIS
VALID
VALID
DI
t
CSS
CS
t
, t
t
CSMIN
t
PD0 PD1
DIS
DO
DATA VALID
Figure 2. Synchronous Data Timing
SK
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
CS
DI
Don’t Care
A
N
A
A
N−1
0
1
HIGH−Z
DO
Dummy 0
D
D
0
Address + 1 Address + 2 Address + n
15 . . .
or
D
D
0
D
D
0
D
15 . . .
15 . . .
15 . . .
D
D
0
or
or
or
7 . . .
D
D
0
D
D
0
D
7 . . .
7 . . .
7 . . .
Figure 3. Read Instruction Timing
SK
t
CSMIN
STANDBY
CS
DI
STATUS
VERIFY
A
N
A
N−1
A
0
D
D
0
N
1
0
1
t
SV
t
HZ
BUSY
HIGH−Z
DO
READY
HIGH−Z
t
EW
Figure 4. Write Instruction Timing
http://onsemi.com
5
CAT93C86
Erase
Erase All
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAT93C86
can be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t . The falling
CSMIN
t
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
CSMIN
Erase/Write Enable and Disable
Write All
The CAT93C86 powers up in the write disable state. Any
writing after power−up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled, it
will remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can be
used to disable all CAT93C86 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
. The falling edge of CS will start the self clocking
CSMIN
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C86 can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
STANDBY
STATUS
VERIFY
t
CS
A
N
A
N−1
A
0
DI
1
1
1
t
t
SV
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 5. Erase Instruction Timing
http://onsemi.com
6
CAT93C86
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
http://onsemi.com
7
CAT93C86
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
http://onsemi.com
8
CAT93C86
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
b
2.03
0.25
0.48
0.25
5.33
8.26
5.38
0.05
0.36
0.19
5.13
7.75
5.13
c
E
E1
D
E
E1
e
1.27 BSC
0.51
0.76
L
0º
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
q
e
b
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
http://onsemi.com
9
CAT93C86
ORDERING INFORMATION
Specific Device
Lead
Marking
Finish
OPN
Pkg Type
Temperature Range
Shipping
CAT93C86LI−G
93C86L
PDIP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 50 Units / Tube
CAT93C86VI−G
93C86V
93C86V
93C86W
93C86W
93C86X
93C86X
SOIC−8, JEDEC
SOIC−8, JEDEC
SOIC−8, JEDEC
SOIC−8, JEDEC
SOIC−8, EIAJ
SOIC−8, EIAJ
I = Industrial
NiPdAu
Tube, 100 Units / Tube
(−40°C to +85°C)
CAT93C86VI−GT3
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
CAT93C86WI−G
(Note 10)
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 100 Units / Tube
CAT93C86WI−GT3
(Note 10)
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
CAT93C86XI
I = Industrial
(−40°C to +85°C)
Matte−Tin
Matte−Tin
Tube, 94 Units / Tube
CAT93C86XI−T2
I = Industrial
(−40°C to +85°C)
Tape & Reel,
2000 Units / Reel
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. The standard lead finish is NiPdAu.
10.Not recommended for new designs.
11. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
12.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
13.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
CAT93C86/D
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明