CAV93C76VE-GT3 [ONSEMI]
EEPROM Serial 8-Kb Microwire - Automotive Grade;
| 型号： | CAV93C76VE-GT3 |
| 厂家： | 
ONSEMI |
| 描述： | EEPROM Serial 8-Kb Microwire - Automotive Grade 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAV93C76
EEPROM Serial 8-Kb
Microwire - Automotive
Grade 1
Description
www.onsemi.com
The CAV93C76 is an EEPROM Serial 8−Kb Microwire
Automotive Grade 1 device, which is configured as either registers of
16 bits (ORG pin at V or Not Connected) or 8 bits (ORG pin at
CC
GND). Each register can be written (or read) serially by using the DI
(or DO) pin. The CAV93C76 is manufactured using ON
Semiconductor’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000 program/erase
cycles and has a data retention of 100 years. The device is available in
8−pin SOIC and TSSOP packages.
SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
Features
1
V
CC
CS
• Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified
• High Speed Operation: 2 MHz
• 2.5 V to 5.5 V Supply Voltage Range
• Selectable x8 or x16 Memory Organization
• Self−timed Write Cycle with Auto−clear
• Software Write Protection
• Power−up Inadvertant Write Protection
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
SK
NC
DI
ORG
DO
GND
SOIC (V), TSSOP (Y)
(Top View)
PIN FUNCTION
Pin Name
Function
CS
SK
DI
Chip Select
Serial Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
• Sequential Read
• 8−pin SOIC and TSSOP Packages
• This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant†
DO
V
CC
GND
ORG
NC
V
CC
Memory Organization
No Connection
NOTE: When the ORG pin is connected to V , the
ORG
CS
CC
x16 organization is selected. When it is connected to
ground, the x8 organization is selected. If the ORG pin
is left unconnected, then an internal pull−up device will
select the x16 organization.
DI
CAV93C76
DO
SK
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
GND
Figure 1. Functional Symbol
†For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
April, 2019 − Rev. 2
CAV93C76/D
CAV93C76
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns.
CC
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V = 5 V, 25°C
CC
Table 3. D.C. OPERATING CHARACTERISTICS
(V = +2.5 V to +5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
Min
Max
2
Units
mA
mA
I
I
Supply Current (Write)
Supply Current (Read)
Write, V = 5.0 V
CC
CC1
CC2
Read, DO open, f = 2 MHz, V = 5.0 V
500
5
SK
CC
I
Standby Current
(x8 Mode)
V
IN
= GND or V
CC
mA
SB1
CS = GND, ORG = GND
I
Standby Current
(x16 Mode)
V
= GND or V
3
mA
SB2
IN
CC
CS = GND,
ORG = Float or V
CC
I
Input Leakage Current
V
V
= GND to V
2
2
mA
mA
LI
IN
CC
I
LO
Output Leakage
Current
= GND to V
OUT
CS = GND
CC
V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
4.5 V ≤ V < 5.5 V
−0.1
2
0.8
V
V
V
V
V
V
V
V
IL1
CC
V
IH1
4.5 V ≤ V < 5.5 V
V
+ 1
CC
CC
V
2.5 V ≤ V < 4.5 V
0
V
x 0.2
IL2
IH2
CC
CC
V
2.5 V ≤ V < 4.5 V
V
V
x 0.7
V
+ 1
CC
CC
CC
V
4.5 V ≤ V < 5.5 V, I = 3 mA
0.4
OL1
OH1
CC
OL
V
4.5 V ≤ V < 5.5 V, I = −400 mA
2.4
CC
OH
V
2.5 V ≤ V < 4.5 V, I = 1 mA
0.2
OL2
OH2
CC
OL
V
2.5 V ≤ V < 4.5 V, I = −100 mA
− 0.2
CC
CC
OH
Table 4. PIN CAPACITANCE (Note 4)
Symbol Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
= 0 V
Min
Typ
Max
5
Units
C
V
pF
pF
OUT
OUT
C
V
IN
= 0 V
5
IN
4. These parameters are tested initially and after a design or process change that affects the parameter.
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2
CAV93C76
Table 5. POWER−UP TIMING (Notes 6, 5)
Symbol
Parameter
Max
1
Units
ms
t
Power−up to Read Operation
Power−up to Write Operation
PUR
t
1
ms
PUW
5. t
and t are the delays required from the time V is stable until the specified operation can be initiated.
PUW CC
PUR
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
4.5 V v V v 5.5 V
CC
Timing Reference Voltages
Input Pulse Voltages
4.5 V v V v 5.5 V
CC
0.2 V to 0.7 V
2.5 V v V v 4.5 V
CC
CC
CC
Timing Reference Voltages
Output Load
0.5 V
2.5 V v V v 4.5 V
CC
CC
Current Source I
/I
; CL = 100 pF
OLmax OHmax
Table 7. A.C. CHARACTERISTICS
(V = +2.5 V to +5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Min
Max
Units
ns
t
CS Setup Time
50
0
CSS
CSH
t
CS Hold Time
ns
t
DI Setup Time
100
100
ns
DIS
t
DI Hold Time
ns
DIH
t
Output Delay to 1
0.25
0.25
100
5
ms
PD1
PD0
t
Output Delay to 0
ms
t
(Note 6)
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
HZ
t
ms
ms
EW
t
0.25
0.25
0.25
CSMIN
t
ms
SKHI
t
ms
SKLOW
t
0.25
ms
SV
SK
DC
2000
kHz
MAX
6. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. INSTRUCTION SET (Note 7)
Address
Data
Start
Bit
x8
x16
x8
x16
Instruction
READ
Opcode
10
Comments
1
1
1
1
1
1
1
A10−A0
A10−A0
A10−A0
A9−A0
Read Address AN– A0
Clear Address AN– A0
Write Address AN– A0
Write Enable
ERASE
WRITE
EWEN
EWDS
ERAL
11
A9−A0
01
A9−A0
D7−D0
D15−D0
00
11XXXXXXXXX
00XXXXXXXXX
10XXXXXXXXX
01XXXXXXXXX
11XXXXXXXX
00XXXXXXXX
10XXXXXXXX
01XXXXXXXX
00
Write Disable
00
Clear All Addresses
Write All Addresses
WRAL
00
D7−D0
D15−D0
7. Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or “0” for READ, WRITE
and ERASE commands.
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3
CAV93C76
Read
Device Operation
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAV93C76 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
The CAV93C76 is a 8192−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAV93C76 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 13−bit
instructions control the read, write and erase operations of
the device. When organized as X8, seven 14−bit instructions
control the read, write and erase operations of the device.
The CAV93C76 operates on a single power supply and will
generate on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The most significant bit of the address is “don’t care” but it
must be present.
specified time delay (t
or t ).
PD0
PD1
For the CAV93C76, after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit.
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of t
. The falling edge of CS will start the self clocking
CSMIN
clear and data store cycle of the memory location specified
in the instruction. The clocking of the SK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAV93C76 can be
determined by selecting the device and polling the DO pin.
Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
t
t
SKLOW
t
SKHI
CSH
SK
t
t
DIH
DIS
VALID
VALID
DI
t
CSS
CS
t
t
, t
t
DIS
PD0 PD1
CSMN
DO
DATA VALID
Figure 2. Synchronous Data Timing
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4
CAV93C76
SK
CS
DI
Don’t Care
A
N
A
N−1
A
0
1
1
0
HIGH−Z
DO
Dummy 0
D
. . . D
Address + 1 Address + 2 Address + n
15
0
or
D . . . D
D
. . . D
D
. . . D
D
or
D . . .
. . .
15
0
15
0
15
or
D . . . D
or
D . . . D
7
0
7
0
7
0
7
Figure 3. READ Instruction Timing
SK
t
CSMIN
STANDBY
CS
DI
STATUS
VERIFY
A
N
A
N−1
A
0
D
D
0
N
1
0
1
t
SV
t
HZ
BUSY
HIGH−Z
DO
READY
HIGH−Z
t
EW
Figure 4. WRITE Instruction Timing
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5
CAV93C76
Erase
determined by selecting the device and polling the DO pin.
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAV93C76
can be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Once cleared, the contents of all memory bits return to a
logical “1” state.
t
CSMIN
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
. The falling edge of CS will start the self clocking
CSMIN
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAV93C76 can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
Erase/Write Enable and Disable
The CAV93C76 powers up in the write disable state. Any
writing after power−up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled, it
will remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can be
used to disable all CAV93C76 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
Note 1: After the last data bit has been sampled, Chip Select
(CS) must be brought Low before the next rising edge of the
clock (SK) in order to start the self−timed high voltage cycle.
This is important because if CS is brought low before or after
this specific frame window, the addressed location will not
be programmed or erased.
Power−On Reset (POR)
The CAV93C76 incorporates Power−On Reset (POR)
circuitry which protects the device against malfunctioning
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAV93C76 can be
. The falling
CSMIN
while V
voltage.
is lower than the recommended operating
CC
The device will power up into a read−only state and will
power−down into a reset state when V crosses the POR
level of ~1.3 V.
CC
SK
CS
STANDBY
STATUS VERIFY
t
CS
A
N
A
N−1
A
0
DI
1
1
1
t
SV
t
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 5. ERASE Instruction Timing
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6
CAV93C76
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 6. EWEN/EWDS Instruction Timing
SK
CS
DI
STATUS VERIFY
STANDBY
t
CS
1
0
0
1
0
t
SV
t
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 7. ERAL Instruction Timing
SK
CS
DI
STATUS VERIFY STANDBY
t
CSMIN
1
0
0
0
1
D
D
0
N
t
SV
t
HZ
BUSY
DO
READY
HIGH−Z
t
EW
Figure 8. WRAL Instruction Timing
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7
CAV93C76
ORDERING INFORMATION
Specific
Device
Lead
†
Finish
Marking
Device Order Number
Package Type
Temperature Range
Shipping
CAV93C76VE−GT3
93C76D
SOIC−8, JEDEC
−40°C to +125°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAV93C76YE−GT3
M76D
TSSOP−8
−40°C to +125°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. The standard lead finish is NiPdAu.
10.For additional package and temperature options, please contact your nearest ON Semiconductor sales office.
11. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8, 150 mils
CASE 751BD
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
θ
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34272E
SOIC 8, 150 MILS
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3.0, 0.65P
CASE 948AL
ISSUE A
DATE 20 MAY 2022
q
q
GENERIC
MARKING DIAGRAM*
XXX
YWW
AG
XXX = Specific Device Code
Y
= Year
WW = Work Week
A
G
= Assembly Location
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34428E
TSSOP8, 4.4X3.0, 0.65P
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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