CS5322GDW28 [ONSEMI]
Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC; 两相降压控制器,集成了栅极驱动器和5位DAC型号: | CS5322GDW28 |
厂家: | ONSEMI |
描述: | Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC |
文件: | 总21页 (文件大小:406K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CS5322
Two−Phase Buck Controller
with Integrated Gate
Drivers and 5−Bit DAC
The CS5322 is a two−phase step down controller which
incorporates all control functions required to power high performance
processors and high current power supplies. Proprietary multi−phase
architecture guarantees balanced load current distribution and reduces
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2
overall solution cost in high current applications. Enhanced V ™
control architecture provides the fastest possible transient response,
excellent overall regulation, and ease of use.
28
1
The CS5322 multi−phase architecture reduces output voltage and
input current ripple, allowing for a significant reduction in inductor
values and a corresponding increase in inductor current slew rate. This
approach allows a considerable reduction in input and output capacitor
requirements, as well as reducing overall solution size and cost.
SO−28L
DW SUFFIX
CASE 751F
PIN CONNECTIONS AND
MARKING DIAGRAM
Features
• Enhanced V Control Method
2
1
• 5−Bit DAC with 1.0% Accuracy
• Adjustable Output Voltage Positioning
• 4 On−Board Gate Drivers
• 200 kHz to 800 kHz Operation Set by Resistor
• Current Sensed through Buck Inductors, Sense Resistors, or V−S
Control
• Hiccup Mode Current Limit
• Individual Current Limits for Each Phase
• On−Board Current Sense Amplifiers
• 3.3 V, 1.0 mA Reference Output
• 5.0 V and/or 12 V Operation
28
COMP
R
OSC
CCL
V
V
V
FB
V
DRP
CCL1
CS1
CS2
GATE(L)1
GND
GATE(H)1
CS
REF
PWRGD
V
CCH1
V
V
V
V
V
LGND
SS
V
GATE(L)2
GND2
GATE(H)2
ID0
ID1
ID2
ID3
ID4
LIM
CCL2
I
REF
V
CCH2
• On/Off Control (through Soft Start Pin)
• Power Good Output with Internal Delay
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
CS5322GDW28
27 Units/Rail
SO−28L
SO−28L
CS5322GDWR28
1000 Tape & Reel
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 7
CS5322/D
CS5322
300 nH
+12 V
+
+5.0 V
3 ×
16SP270M
1.0 μF
1.0 μF
1.0 μF
ENABLE
600 nH
61.9 k
1.0 nF
1.0 nF
4.12 k
R
+
8 ×
4SP820M
COMP
OSC
V
CCL
V
FB
V
CCL1
V
DRP
34.8 k
12.7 k
GATE(L)1
CS1
CS2
GND1
GATE(H)1
CS
REF
V
OUT
V
CCH1
PWRGD
PWRGD
LGND
SS
V
V
V
ID0
ID1
ID2
12 ×10 μF
V
CCL2
0.1 μF
V
V
GATE(L)2
GND2
GATE(H)2
ID0
ID1
ID2
V
ID3
ID4
V
I
LIM
V
CCH2
REF
V
V
V
ID3
ID4
2.80 k
1.0 k
0.1 μF
600 nH
1.0 μF
25.5 k
.01 μF
25.5 k
.01 μF
.01 μF
Figure 1. Application Diagram, 12 V to 1.6 V, 35 A Converter
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CS5322
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
150
Unit
°C
Operating Junction Temperature
Lead Temperature Soldering:
Storage Temperature Range
Reflow: (SMD styles only) (Note 1)
230 peak
−65 to +150
2.0
°C
°C
ESD Susceptibility (Human Body Model)
kV
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ABSOLUTE MAXIMUM RATINGS
Pin Name
Pin Symbol
V
V
I
I
SINK
MAX
MIN
SOURCE
Power for Logic
V
16 V
16 V
16 V
20 V
20 V
6.0 V
6.0 V
6.0 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
N/A
50 mA
CCL
Power for GATE(L)1
Power for GATE(L)2
Power GATE(H)1
Power for GATE(H)2
Power Good Output
Soft Start Capacitor
V
V
N/A
N/A
1.5 A, 1.0 μs 200 mA DC
1.5 A, 1.0 μs 200 mA DC
1.5 A, 1.0 μs 200 mA DC
1.5 A, 1.0 μs 200 mA DC
20 mA
CCL1
CCL2
CCH1
CCH2
V
V
N/A
N/A
PWRGD
SS
1.0 mA
1.0 mA
1.0 mA
1.0 mA
Voltage Feedback Compensation
Network
COMP
1.0 mA
Voltage Feedback Input
V
6.0 V
6.0 V
−0.3 V
−0.3 V
1.0 mA
1.0 mA
1.0 mA
1.0 mA
FB
Output for Adjusting Adaptive
Voltage Position
V
DRP
Frequency Resistor
Reference Output
R
6.0 V
6.0 V
20 V
−0.3 V
−0.3 V
1.0 mA
1.0 mA
1.0 mA
50 mA
OSC
REF
High−Side FET Drivers
GATE(H)1−2
−0.3 V DC
−2.0 V for 100
ns
1.5 A, 1.0 μs
200 mA DC
1.5 A, 1.0 μs
200 mA DC
Low−Side FET Drivers
GATE(L)1−2
16 V
−0.3 V DC
−2.0 V for 100
ns
1.5 A, 1.0 μs
200 mA DC
1.5 A, 1.0 μs
200 mA DC
Return for Logic
Return for #1 Driver
LGND
GND1
N/A
N/A
50 mA
2.0 A, 1.0 μs 200 mA DC
2.0 A, 1.0 μs 200 mA DC
1.0 mA
N/A
N/A
0.3 V
0.3 V
6.0 V
6.0 V
6.0 V
6.0 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
Return for #2 Driver
GND2
N/A
Current Sense for Phases 1−2
Current Limit Set Point
Current Sense Reference
Voltage ID DAC Inputs
CS1−CS2
1.0 mA
1.0 mA
1.0 mA
1.0 mA
I
1.0 mA
LIM
CS
1.0 mA
REF
V
1.0 mA
ID0−4
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CS5322
ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V
< 14 V; 8.0 V < V
< 20 V;
A
J
CCL
CCH
C
= 3.3 nF, C
= 3.3 nF, R
= 32.4 k, C
= 1.0 nF, C = 0.1 μF, C
= 0.1 μF, DAC Code 10000, C = 1.0 μF,
VCC
GATE(H)
GATE(L)
R(OSC)
COMP
SS
REF
I
≥ 1.0 V; unless otherwise specified.)
LIM
Characteristic
Test Conditions
Min
Typ
Max
Unit
Voltage Identification DAC (0 = Connected to V ; 1 = Open or Pull−up to 3.3 V)
SS
Accuracy (all codes)
Measure V = COMP
± 1.0
%
FB
V
V
V
V
V
ID0
ID4
ID3
ID2
ID1
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1.064
1.089
1.114
1.139
1.163
1.188
1.213
1.238
1.262
1.287
1.312
1.337
1.361
1.386
1.411
1.436
1.460
1.485
1.510
1.535
1.559
1.584
1.609
1.634
1.658
1.683
1.708
1.733
1.757
1.782
1.807
1.832
1.00
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.25
1.086
1.111
1.136
1.162
1.187
1.212
1.237
1.263
1.288
1.313
1.338
1.364
1.389
1.414
1.439
1.465
1.490
1.515
1.540
1.566
1.591
1.616
1.641
1.667
1.692
1.717
1.742
1.768
1.793
1.818
1.843
1.869
1.50
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
kΩ
V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Input Threshold
V
V
, V , V , V , V
ID3 ID2 ID1
ID4
ID0
Input Pull−up Resistance
Pull−up Voltage
, V , V , V , V
25
50
100
ID4
ID3
ID2
ID1
ID0
−
3.15
3.30
3.45
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CS5322
ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V
< 14 V; 8.0 V < V
= 0.1 μF, DAC Code 10000, C = 1.0 μF,
< 20 V;
A
J
CCL
CCH
C
= 3.3 nF, C
= 3.3 nF, R
= 32.4 k, C
= 1.0 nF, C = 0.1 μF, C
GATE(H)
GATE(L)
R(OSC)
COMP
SS
REF
VCC
I
≥ 1.0 V; unless otherwise specified.)
LIM
Characteristic
Test Conditions
Min
Typ
Max
Unit
Power Good Output
Power Good Fault Delay
Output Low Voltage
CS
CS
CS
= V
to V
± 15%
25
−
50
0.25
0.1
−11
11
125
0.40
10
μs
V
REF
REF
REF
DAC
DAC
= 1.0 V, I
= 4.0 mA
PWRGD
Output Leakage Current
Lower Threshold
= 1.45 V, PWRGD = 5.5 V
−
μA
%
%
% of Nominal VID Code
% of Nominal VID Code
−14
8
−8.0
14
Upper Threshold
Voltage Feedback Error Amplifier
V
Bias Current (Note 2)
9.0
15
10.3
30
11.5
60
μA
μA
1.0 V < V < 1.9 V
FB
FB
COMP Source Current
COMP = 0.5 V to 2.0 V;
V
= 1.8 V; DAC = 00000
FB
COMP Sink Current
15
30
60
μA
COMP = 0.5 V to 2.0 V;
V
= 1.9 V; DAC = 00000
FB
COMP Max Voltage
COMP Min Voltage
Transconductance
2.4
−
2.7
0.1
32
−
0.2
−
V
V
V
V
= 1.8 V COMP Open; DAC = 00000
= 1.9 V COMP Open; DAC = 00000
FB
FB
−
mmho
−10 μA < I
< +10 μA
COMP
Output Impedance
Open Loop DC Gain
Unity Gain Bandwidth
−
−
60
−
2.5
90
−
−
−
MΩ
dB
Note 3
400
kHz
0.01 μF COMP Capacitor
−
−
70
−
dB
PSRR @ 1.0 kHz
Soft Start
Soft Start Charge Current
Soft Start Discharge Current
Hiccup Mode Charge/Discharge Ratio
Peak Soft Start Charge Voltage
Soft Start Discharge Threshold Voltage
PWM Comparators
0.2 V ≤ SS ≤ 3.0 V
15
4.0
30
7.5
50
13
μA
μA
−
0.2 V ≤ SS ≤ 3.0 V
−
−
−
3.0
4.0
−
3.3
4.0
4.2
0.34
V
0.20
0.27
V
Minimum Pulse Width
Measured from CSx to GATE(H)
−
350
0.4
515
0.5
ns
V
X
V(V ) = V(CS
) = 1.0 V, V(COMP) = 1.5 V
REF
FB
60 mV step applied between V
and V
CREF
CSX
Channel Start Up Offset
0.3
V(CS1) = V(CS2) = V(V ) = V(CS
) = 0 V;
REF
FB
Measure V(COMP) when GATE(H)1,
GATE(H)2, switch high
GATE(H) and GATE(L)
High Voltage (AC)
Note 3 Measure V
− GATE(L) or
−
0
1.0
V
CCLX
X
V
− GATE(H)
CCHX
X
Low Voltage (AC)
Note 3 Measure GATE(L)
GATE(H)
−
−
−
0
0.5
80
80
V
X or
X
Rise Time GATE(H)
1.0 V < GATE < 8.0 V; V
1.0 V < GATE < 8.0 V; V
= 10 V
= 10 V
35
35
ns
ns
X
CCHX
CCLX
Rise Time GATE(L)
X
2. The V Bias Current changes with the value of R
per Figure 4.
OSC
FB
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CS5322
ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V
< 14 V; 8.0 V < V
< 20 V;
A
J
CCL
CCH
C
= 3.3 nF, C
= 3.3 nF, R
= 32.4 k, C
= 1.0 nF, C = 0.1 μF, C
= 0.1 μF, DAC Code 10000, C = 1.0 μF,
GATE(H)
GATE(L)
R(OSC)
COMP
SS
REF
VCC
I
≥ 1.0 V; unless otherwise specified.)
LIM
Characteristic
Test Conditions
Min
Typ
Max
Unit
GATE(H) and GATE(L)
3. Guaranteed by design. Not tested in production.
Fall Time GATE(H) 8.0 V > GATE > 1.0 V; V
= 10 V
−
−
35
35
65
65
1.2
80
80
ns
ns
ns
ns
V
X
CCHX
CCLX
Fall Time GATE(L)
8.0 V > GATE > 1.0 V; V
= 10 V
X
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE Pull−down
GATE(H) < 2.0 V, GATE(L) > 2.0 V
30
30
−
110
110
1.6
X
X
GATE(L) < 2.0 V, GATE(H) > 2.0 V
X
X
Force 100 μA into GATE Driver with no power
applied to V and V = 2.0 V.
CCHX
CCLX
Oscillator
Switching Frequency
Switching Frequency
Switching Frequency
Measure any phase (R
= 32.4 k)
300
150
600
−
400
200
800
1.0
500
250
1000
−
kHz
kHz
kHz
V
OSC
Note 4 Measure any phase (R
= 63.4 k)
OSC
OSC
Note 4 Measure any phase (R
= 16.2 k)
R
OSC
Voltage
−
−
Phase Delay
165
180
195
deg
Adaptive Voltage Positioning
V
Output Voltage to DAC
Offset
CS1 = CS2 = CS , V = COMP
REF FB
−15
240
2.4
−
15
380
3.8
mV
mV
V/V
DRP
OUT
Measure V
− COMP
DRP
Maximum V
Voltage
(CS1 = CS2) − C
= 50 mV,
310
3.0
DRP
REF
V
= COMP, Measure V
− COMP
FB
DRP
Current Sense Amp to V
Gain
−
DRP
Current Sensing and Sharing
CS Input Bias Current
V(CSx) = V(CS
V(CSx) = V(CS
) = 0 V
) = 0 V
−
−
−
0.5
0.2
3.15
−
4.0
2.0
μA
μA
V/V
mV
V
REF
REF
CS1−CS2 Input Bias Current
Current Sense Amplifiers Gain
Current Sense Amp Mismatch
REF
2.8
−5.0
0
3.53
5.0
Note 4, 0 ≤ (CSx − CS
) ≤ 50 mV
REF
Current Sense Amplifiers Input
Common Mode Range Limit
Note 4
−
V
− 2
CCL
Current Sense Input to I
Gain
0.25 V < I
< 1.20 V
LIM
5.0
4.0
−
6.25
10
8.0
V/V
mV/μs
μA
LIM
Current Limit Filter Slew Rate
Bias Current
Note 4
26
1.0
135
I
0 < I
< 1.0 V
0.1
105
LIM
LIM
Single Phase Pulse by Pulse
−
90
mV
Current Limit: V(CSx) − V(CS
)
REF
Current Share Amplifier Bandwidth
Note 4
1.0
3.2
−
−
MHz
V
Reference Output
V
Output Voltage
3.3
3.4
0 mA < I(V
) < 1.0 mA
REF
REF
4. Guaranteed by design. Not tested in production.
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CS5322
ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V
< 14 V; 8.0 V < V
< 20 V;
A
J
CCL
CCH
C
= 3.3 nF, C
= 3.3 nF, R
= 32.4 k, C
= 1.0 nF, C = 0.1 μF, C
= 0.1 μF, DAC Code 10000, C = 1.0 μF,
GATE(H)
GATE(L)
R(OSC)
COMP
SS
REF
VCC
I
≥ 1.0 V; unless otherwise specified.)
LIM
Characteristic
Test Conditions
Min
Typ
Max
Unit
General Electrical Specifications
V
V
V
V
V
V
V
V
V
V
V
Operating Current
V
V
V
V
V
= COMP (no switching)
= COMP (no switching)
= COMP (no switching)
= COMP (no switching)
= COMP (no switching)
−
−
20
4.0
4.0
2.8
2.5
4.4
4.2
200
2.0
1.75
200
24.5
5.5
mA
mA
mA
mA
mA
V
CCL
FB
FB
FB
FB
FB
Operating Current
Operating Current
Operating Current
Operating Current
CCL1
CCL2
CCH1
CCH2
−
5.5
−
4.0
−
3.5
Start Threshold
Stop Threshold
Hysteresis
GATEs switching, Soft Start charging
4.05
3.75
100
1.8
1.55
100
4.7
CCL
GATEs stop switching, Soft Start discharging
GATEs not switching, Soft Start not charging
GATEs switching, Soft Start charging
4.6
V
CCL
300
2.2
mV
V
CCL
Start Threshold
Stop Threshold
Hysteresis
CCH1
CCH1
CCH1
GATEs stop switching, Soft Start discharging
GATEs not switching, Soft Start not charging
1.90
300
V
mV
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO−28L
PIN SYMBOL
FUNCTION
1
COMP
Output of the error amplifier and input for the PWM
comparators.
2
3
V
Voltage Feedback Pin. To use Adaptive Voltage Positioning
(AVP) select an offset voltage at light load and connect a
FB
resistor between V and V
. The input current of the V
FB
OUT
FB
pin and the resistor value determine output voltage offset for
zero output current. Short V to V for no AVP.
FB
OUT
V
Current sense output for AVP. The offset of this pin above the
DAC voltage is proportional to the output current. Connect a
DRP
resistor from this pin to V to set amount AVP or leave this
FB
pin open for no AVP.
4−5
CS1−CS2
Current sense inputs. Connect current sense network for the
corresponding phase to each input.
6
CS
Reference for Current Sense Amplifiers. To balance input
offset voltages between the inverting and noninverting inputs
of the Current Sense Amplifiers, connect a resistor between
REF
CS
and the output voltage. The value should be 1/3 of
REF
the value of the resistors connected to the CSx pins.
7
PWRGD
Power Good Output. Open collector output goes low when
CS
is out of regulation.
REF
8−12
V
−V
Voltage ID DAC inputs. These pins are internally pulled up to
3.3 V if left open.
ID4
ID0
13
I
Sets threshold for current limit. Connect to reference through
a resistive divider.
LIM
Reference output. Decouple with 0.1 μF to LGND.
Power for GATE(H)2.
14
15
16
17
18
REF
V
CCH2
GATE(H)2
GND2
High side driver #2.
Return for #2 driver.
GATE(L)2
Low side driver #2.
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7
CS5322
PACKAGE PIN DESCRIPTION (continued)
PACKAGE PIN #
SO−28L
19
PIN SYMBOL
FUNCTION
V
Power for GATE(L)2.
CCL2
20
SS
Soft Start capacitor pin. The Soft Start capacitor controls
both Soft Start time and hiccup mode frequency. The COMP
pin is clamped below Soft Start during Start−Up and hiccup
mode.
21
22
LGND
Return for internal control circuits and IC substrate connection.
V
Power for GATE(H)1. UVLO Sense for High Side Driver sup-
ply connects to this pin.
CCH1
23
24
25
26
27
GATE(H)1
GND1
High side driver #1.
Return #1 drivers.
Low side driver #1.
Power for GATE(L)1.
GATE(L)1
V
CCL1
V
Power for internal control circuits. UVLO Sense for Logic
connects to this pin.
CCL
28
R
OSC
A resistor from this pin to ground sets operating frequency
and V bias current.
FB
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8
CS5322
−
V
CCL
Start
Stop
+
3.3 V
REF
PWRGD
+
−
REF
4.4 V
4.2 V
−
V
CCH1
Start
Stop
+
V
V
V
ID0
ID1
ID2
DAC
+
−
OUT
S
R
PH 1
GATE(H)1
2.0 V
1.8 V
Gate
DAC
Delay
Nonoverlap
V
−
CCL1
PWMC1
V
V
ID3
ID4
+
GATE(L)1
GND1
CO1
+
MAXC1
LGND
−
+
−
+11%
V
FAULT
CCH2
−
−
+
−
CO1
0.33 V
S
R
AVPA
PH 2
V
GATE(H)2
DRP
+
Gate
Nonoverlap
V
−
CCL2
CS
REF
PWMC2
+
GATE(L)2
GND2
CO2
+
+
MAXC2
+
−
CO1
CS1
CS2
CSA1
−11%
+
−
−
FAULT
CO2
0.33 V
−
CSA2 CO2
+
−
× 2
+
Offset
I
LIM
Filter
+
−
I
−
LIM
Current
Source
Gen
EA
+
BIAS
DAC
OUT
SS
Charge
Current
FAULT
FAULT
S
R
PH 1
+
−
+
−
SS
Discharge
Threshold
SS
Discharge
Current
OSC
+
PH 2
−
R
OSC
V
COMP
SS
FB
Figure 2. Block Diagram
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CS5322
TYPICAL PERFORMANCE CHARACTERISTICS
900
800
700
25
20
15
600
500
400
10
5
300
200
100
0
10
20
30
40
50
60
70
10
20
30
40
50
60
70
80
R
OSC
Value, kΩ
R
OSC
Value, kΩ
Figure 3. Oscillator Frequency
Figure 4. VFB Bias Current vs. ROSC Value
120
100
80
120
100
80
60
60
40
40
20
0
20
0
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Load Capacitance, nF
Load Capacitance, nF
Figure 5. Gate(H) Rise−time vs. Load Capacitance
Figure 6. Gate(H) Fall−time vs. Load Capacitance
measured from 1.0 V to 4.0 V with VCC at 5.0 V.
measured from 4.0 V to 1.0 V with VCC at 5.0 V.
120
100
80
120
100
80
60
60
40
40
20
0
20
0
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Load Capacitance, nF
Load Capacitance, nF
Figure 7. Gate(L) Rise−time vs. Load Capacitance
Figure 8. Gate(L) Fall−time vs. Load Capacitance
measured from 4.0 V to 1.0 V with VCC at 5.0 V.
measured from 4.0 V to 1.0 V with VCC at 5.0 V.
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CS5322
APPLICATIONS INFORMATION
FIXED FREQUENCY MULTI−PHASE CONTROL
inductor starts the cycle with a higher current, the PWM
cycle will terminate earlier providing negative feedback.
The CS5322 provides a Cx input for each phase, but the
In a multi−phase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the apparent ripple frequency. Because several
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
CS , V and COMP inputs are common to all phases.
REF FB
Current sharing is accomplished by referencing all phases to
the same V and COMP pins, so that a phase with a larger
FB
current signal will turn off earlier than phases with a smaller
current signal.
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. When the average output
current is zero, the COMP pin will be only 1/2 of the steady
state ramp height plus the OFFSET above the output
voltage. If the COMP pin is held steady and the inductor
current changes, there must also be a change in the output
voltage. Or, in a closed loop configuration when the output
current changes, the COMP pin must move to keep the same
output voltage. The required change in the output voltage or
COMP pin depends on the scaling of the current feedback
signal and is calculated as
The CS5322 uses a two−phase, fixed frequency,
2
Enhanced V architecture. Each phase is delayed 180° from
the previous phase. Normally Gate(H) transitions high at the
beginning of each oscillator cycle. Inductor current ramps
up until the combination of the current sense signal and the
output ripple trip the PWM comparator and bring Gate(H)
low. Once Gate(H) goes low, it will remain low until the
beginning of the next oscillator cycle. While Gate(H) is
2
high, the enhanced V loop will respond to line and load
transients. Once Gate(H) is low, the loop will not respond
again until the beginning of the next cycle. Therefore,
2
DV + R CSA Gain DI
S
constant frequency Enhanced V will typically respond
The single−phase power stage output impedance is:
within the off−time of the converter.
The Enhanced V architecture measures and adjusts
current in each phase. An additional input (Cx) for inductor
current information has been added to the V loop for each
2
Single Stage Impedance + DVńDI + R CSA Gain.
S
The multi−phase power stage output impedance is the
single−phase output impedance divided by the number of
phases. The output impedance of the power stage determines
how the converter will respond during the first few μs of a
transient before the feedback loop has repositioned the
COMP pin.
2
phase as shown in Figure 9.
SWNODE
C
X
L
R
L
+
CSA
+
+
+
The peak output current of each phase can also be
calculated from;
R
S
OFFSET
CS
V
REF
V
* V
FB
* V
OFFSET
PWM-
COMP
COMP
R
I
(per phase) +
pkout
CSA Gain
S
V
+
OUT
Figure 10 shows the step response of a single phase with
the COMP pin at a fixed level. Before T1 the converter is in
normal steady state operation. The inductor current provides
the PWM ramp through the Current Sense Amplifier. The
PWM cycle ends when the sum of the current signal, voltage
signal and OFFSET exceed the level of the COMP pin. At
T1 the output current increases and the output voltage sags.
The next PWM cycle begins and the cycle continues longer
than previously while the current signal increases enough to
FB
+
E.A.
+
DAC
OUT
+
COMP
Figure 9. Enhanced V2 Feedback and Current
Sense Scheme
make up for the lower voltage at the V pin and the cycle
FB
The inductor current is measured across R , amplified by
S
ends at T2. After T2 the output voltage remains lower than
at light load and the current signal level is raised so that the
sum of the current and voltage signal is the same as with the
original load. In a closed loop system the COMP pin would
CSA and summed with the OFFSET and Output Voltage at
the non−inverting input of the PWM comparator. The
inductor current provides the PWM ramp and as inductor
current increases the voltage on the positive pin of the PWM
comparator rises and terminates the PWM cycle. If the
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11
CS5322
move higher to restore the output voltage to the original
level.
winding resistance at higher temperatures should be
considered when setting the I threshold. If a more
LIM
accurate current sense is required than inductive sensing can
provide, current can be sensed through a resistor as shown
in Figure 9.
SWNODE
Current Sharing Accuracy
PCB traces that carry inductor current can be used as part
of the current sense resistance depending on where the
current sense signal is picked off. For accurate current
sharing, the current sense inputs should sense the current at
the same point for each phase and the connection to the
V
(V
OUT
)
FB
CS
should be made so that no phase is favored. (In some
REF
CSA Out
cases, especially with inductive sensing, resistance of the
pcb can be useful for increasing the current sense
resistance.) The total current sense resistance used for
calculations must include any pcb trace between the CS
COMP − Offset
CSA Out + V
FB
inputs and the CS
input that carries inductor current.
REF
T1
T2
Current Sense Amplifier Input Mismatch and the value of
the current sense element will determine the accuracy of
current sharing between phases. The worst case Current
Sense Amplifier Input Mismatch is 5.0 mV and will
typically be within 3.0 mV. The difference in peak currents
between phases will be the CSA Input Mismatch divided by
the current sense resistance. If all current sense elements are
of equal resistance a 3.0 mV mismatch with a 2.0 mΩ sense
resistance will produce a 1.5 A difference in current between
phases.
Figure 10. Open Loop Operation
Inductive Current Sensing
For lossless sensing, current can be sensed across the
inductor as shown in Figure 11. In the diagram L is the output
inductance and R is the inherent inductor resistance. To
L
compensate the current sense signal the values of R1 and C1
are chosen so that L/R = R1 × C1. If this criteria is met the
L
current sense signal will be the same shape as the inductor
current, the voltage signal at Cx will represent the
instantaneous value of inductor current and the circuit can be
Operation at > 50% Duty Cycle
For operation at duty cycles above 50% Enhanced V will
2
analyzed as if a sense resistor of value R was used as a sense
L
resistor (R ).
exhibit subharmonic oscillation unless a compensation
ramp is added to each phase. A circuit like the one on the left
side of Figure 12 can be added to each current sense network
to implement slope compensation. The value of R1 can be
varied to adjust the ramp size.
S
R1
SWNODE
CS
+
L
+
+
+
CSA
C1
R
OFFSET
L
Switch Node
GATE(L)X
CS
REF
PWM-
COMP
+
V
OUT
V
FB
E.A.
+
DAC
25 k
R1
3 k
OUT
COMP
CS
X
1.0 nF
0.1 μF
.01 μF
Figure 11. Lossless Inductive Current Sensing with
Enhanced V2
CS
REF
MMBT2222LT1
When choosing or designing inductors for use with
inductive sensing tolerances and temperature, effects should
be considered. Cores with a low permeability material or a
large gap will usually have minimal inductance change with
temperature and load. Copper magnet wire has a
temperature coefficient of 0.39% per °C. The increase in
Existing Current
Sense Circuit
Slope Comp
Circuit
Figure 12. External Slope Compensation Circuit
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CS5322
Ramp Size and Current Sensing
Because the current ramp is used for both the PWM ramp
and to sense current, the inductor and sense resistor values
will be constrained. A small ramp will provide a quick
transient response by minimizing the difference over which
the COMP pin must travel between light and heavy loads,
but a steady state ramp of 25 mVp−p or greater is typically
required to prevent pulse skipping and minimize pulse width
jitter. For resistive current sensing, the combination of the
inductor and sense resistor values must be chosen to provide
a large enough steady state ramp. For large inductor values
the sense resistor value must also be increased.
For inductive current sensing, the RC network must meet
the requirement of L/R = R × C to accurately sense the AC
L
and DC components of the current the signal. Again the
values for L and R will be constrained in order to provide
L
a large enough steady state ramp with a compensated current
sense signal. A smaller L, or a larger R than optimum might
L
Figure 13. Inductive Sensing waveform during a Step
be required. But unlike resistive sensing, with inductive
sensing, small adjustments can be made easily with the
values of R and C to increase the ramp size if needed.
with Fast RC Time Constant (50 μs/div)
Current Limit
If RC is chosen to be smaller (faster) than L/R , the AC
L
Two levels of overcurrent protection are provided. Any
portion of the current sensing signal will be scaled larger
than the DC portion. This will provide a larger steady state
ramp, but circuit performance will be affected and must be
evaluated carefully. The current signal will overshoot during
transients and settle at the rate determined by R × C. It will
eventually settle to the correct DC level, but the error will
decay with the time constant of R × C. If this error is
excessive it will effect transient response, adaptive
positioning and current limit. During transients the COMP
pin will be required to overshoot along with the current
time the voltage on a Current Sense pin exceeds CS
by
REF
more than the Single Phase Pulse by Pulse Current Limit, the
PWM comparator for that phase is turned off. This provides
fast peak current protection for individual phases. The
outputs of all the currents are also summed and filtered to
compare an averaged current signal to the voltage on the
I
pin. If this voltage is exceeded, the fault latch trips and
LIM
the Soft Start capacitor is discharged by a 7.5 μA source until
the COMP pin reaches 0.2 V. Then Soft Start begins. The
converter will continue to operate in this mode until the fault
condition is corrected.
signal in order to maintain the output voltage. The V
pin
DRP
will also overshoot during transients and possibly slow the
response. Single phase overcurrent will trip earlier than it
would if compensated correctly and hiccup mode current
limit will have a lower threshold for fast rise step loads than
for slowly rising output currents.
Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of
2
the normal operation of the Enhanced V control topology
with synchronous rectifiers. The control loop responds to an
overvoltage condition within 400 ns, causing the top
MOSFET’s to shut off and the synchronous MOSFET’s to
turn on. This results in a “crowbar” action to clamp the
output voltage and prevent damage to the load. The regulator
will remain in this state until the overvoltage condition
ceases or the input voltage is pulled low.
The waveforms in Figure 13 show a simulation of the
current sense signal and the actual inductor current during a
positive step in load current with values of L = 500 nH, R
L
= 1.6 mΩ, R1 = 20 k and C1 = .01 μF. For ideal current signal
compensation the value of R1 should be 31 kΩ. Due to the
faster than ideal RC time constant there is an overshoot of
50% and the overshoot decays with a 200 μs time constant.
With this compensation the I
pin threshold must be set
LIM
more than 50% above the full load current to avoid
triggering hiccup mode during a large output load step.
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CS5322
Transient Response and Adaptive Positioning
size and the error amp compensation. If the ramp size is too
large or the error amp too slow there will be a long transition
to the final voltage after a transient. This will be most
apparent with lower capacitance output filters.
Note: Large levels of adaptive positioning can cause pulse
width jitter.
For applications with fast transient currents the output
filter is frequently sized larger than ripple currents require in
order to reduce voltage excursions during transients.
Adaptive voltage positioning can reduce peak−peak output
voltage deviations during load transients and allow for a
smaller output filter. The output voltage can be set higher
than nominal at light loads to reduce output voltage sag
when the load current is stepped up and set lower than
nominal during heavy loads to reduce overshoot when the
load current is stepped up. For low current applications a
droop resistor can provide fast accurate adaptive
positioning. However, at high currents the loss in a droop
resistor becomes excessive. For example; in a 50 A
converter a 1.0 mΩ resistor to provide a 50 mV change in
output voltage between no load and full load would dissipate
2.5 Watts.
Lossless adaptive positioning is an alternative to using a
droop resistor, but must respond quickly to changes in load
current. Figure 14 shows how adaptive positioning works.
The waveform labeled normal shows a converter without
adaptive positioning. On the left, the output voltage sags
when the output current is stepped up and later overshoots
when current is stepped back down. With fast (ideal)
adaptive positioning the peak to peak excursions are cut in
half. In the slow adaptive positioning waveform the output
voltage is not repositioned quickly enough after current is
stepped up and the upper limit is exceeded.
Error Amp Compensation
The transconductance error amplifier requires a capacitor
between the COMP pin and GND. Use of values less than 1
nF may result in error amp oscillation of several MHz.
The capacitor between the COMP pin and the inverting
error amplifier input and the parallel resistance of the V
FB
resistor and the V
resistor are used to roll off the error
DRP
amp gain. The gain is rolled off at a high enough frequency
to give a quick transient response, but low enough to cross
zero dB well below the switching frequency to minimize
ripple and noise on the COMP pin.
UVLO
The CS5322 has undervoltage lockout functions
connected to two pins. One, intended for the logic and
low−side drivers, with a 4.4 V turn−on threshold is
connected to the V
pin. A second, for the high side
CCL
drivers, has a 2.0 V threshold and is connected to the V
pin.
CCH1
The UVLO threshold for the high side drivers was chosen
at a low value to allow for flexibility in the part and an input
voltage as low as 3.3 V. In many applications this will be
disabled or will only check that the applicable supply is on
− not that is at a high enough voltage to run the converter.
For the 12 V converter in the application diagram on
IN
page 2, the UVLO pin for the high side driver is pulled up
by the 5.0 V supply (through two diode drops) and the
function is not used. The diode between the Soft Start pin
near GND and prevents start−up while the 12 V supply is off.
In an application where a higher UVLO threshold is
necessary a circuit like the one in Figure 15 will lock out the
converter until the 12 V supply exceeds 9 V.
Normal
FastAdaptive Positioning
SlowAdaptive Positioning
Limits
Figure 14. Adaptive Positioning
The CS5322 can be configured to adjust the output
voltage based on the output current of the converter. (Refer
to the application diagram on page 2)
+12 V
+5 V
To set the no−load positioning, a resistor is placed
50 k
Soft Start
between the output voltage and V pin. The V bias
FB
FB
current will develop a voltage across the resistor to increase
the output voltage. The V bias current is dependent on the
FB
value of R
. See Figure 4.
OSC
During no load conditions the V
pin is at the same
100 k
DRP
voltage as the V pin, so none of the V bias current flows
FB
FB
100 k
through the V
resistor. When output current increases
DRP
the V
pin increases proportionally and the V
pin
DRP
DRP
current offsets the V bias current and causes the output
voltage to decrease.
FB
Figure 15. External UVLO Circuit
The V and V
pins take care of the slower and DC
FB
DRP
Soft Start and Hiccup Mode
A capacitor between the Soft Start pin and GND controls
Soft Start and hiccup mode slopes. A 0.1 μF capacitor with
voltage positioning. The first few μs are controlled primarily
by the ESR and ESL of the output filter. The transition
between fast and slow positioning is controlled by the ramp
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CS5322
the 30 μA charge current will allow the output to ramp up at
DESIGN PROCEDURE
0.3 V/ms or 1.5 V in 5.0 ms at start−up.
Current Sensing, Power Stage and
Output Filter Components
When a fault is detected due to overcurrent or UVLO the
converter will enter a low duty cycle hiccup mode. During
hiccup mode the converter will not switch from the time a
fault is detected until the Soft Start capacitor has discharged
below the Soft Start Discharge Threshold and then charged
back up above the Channel Start Up Offset.
1. Choose the output filter components to meet peak
transient requirements. The formula below can be
used to provide an approximate starting point for
capacitor choice, but will be inadequate to calculate
actual values.
The Soft Start pin will disable the converter when pulled
below 0.3 V.
DV
+ (DIńDT) ESL ) DI ESR
PEAK
Ideally the output filter should be simulated with
models including ESR, ESL, circuit board parasitics
and delays due to switching frequency and converter
response. Typically both bulk capacitance
(electrolytic, Oscon, etc.,) and low impedance
capacitance (ceramic chip) will be required. The bulk
capacitance provides “hold up” during the converter
response. The low impedance capacitance reduces
steady state ripple and bypasses the bulk capacitance
during slewing of output current.
Layout Guidelines
With the fast rise, high output currents of microprocessor
applications, parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically, a multi−layer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to reroute the currents away from the
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Gate drives experience high di/dt during switching and the
inductance of gate drive traces should be minimized. Gate
drive traces should be kept as short and wide as practical and
should have a return path directly below the gate trace.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
2. For inductive current sensing (only) choose the
current sense network RC to provide a 25 mV
minimum ramp during steady state operation.
V
ńV
OUT IN
R + (V * V
)
IN OUT
F C 25 mV
Then choose the inductor value and inherent
resistance to satisfy L/R = R × C.
L
For ideal current sense compensation the ratio of L and
R
L
is fixed, so the values of L and R will be a
L
compromise typically with the maximum value R
L
limited by conduction losses or inductor temperature
rise and the minimum value of L limited by ripple
current.
Voltage feedback should be taken from a point of the
output or the output filter that doesn’t favor any one phase.
If the feedback connection is closer to one inductor than the
others the ripple associated with that phase may appear
larger than the ripple associated with the other phases and
poor current sharing can result.
3. For resistive current sensing choose L and R to
S
provide a steady state ramp greater than 25 mV.
LńR + (V * V
IN OUT
) T
ń25 mV
ON
S
Again the ratio of L and R is fixed and the values of
L
L and R will be a compromise.
S
The current sense signal is typically tens of milli−volts.
Noise pick−up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as switch nodes and gate drive signals. The paths
should be matched as well as possible. It is especially
important that all current sense signals be picked off at
similar points for accurate current sharing. If the current
signal is taken from a place other than directly at the inductor
any additional resistance between the pick−off point and the
inductor appears as part of the inherent inductor resistance
and should be considered in design calculations. Capacitors
for the current feedback networks should be placed as close
to the current sense pins as practical.
4. Calculate the high frequency output impedance
(ConverterZ) of the converter during transients. This
is the impedance of the Output filter ESR in parallel
with the power stage output impedance (PwrstgZ)
and will indicate how far from the original level
(ΔVR) the output voltage will typically recover to
within one switching cycle. For a good transient
response ΔVR should be less than the peak output
voltage overshoot or undershoot.
DVR + ConverterZ ESR
PwrstgZ ESR
ConverterZ +
PwrstgZ ) ESR
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CS5322
where:
source enough current across R ( ) for the desired
V FB
change in output voltage.
PwrstgZ + R CSA Gainń2.0
S
DV
+ I
R CS to V
Gain
DRP
V(DRP)
OUTFL
Multiply the converterZ by the output current step
size to calculate where the output voltage should
recover to within the first switching cycle after a
transient. If the ConverterZ is higher than the value
required to recover to where the adaptive positioning
is set the remainder of the recovery will be controlled
by the error amp compensation and will typically
recover in 10−20 μs.
where:
R = R or R for one phase;
OUTFL
L
S
I
is the full load output current.
R
+ DV
DRP
R
ńDV
V(FB) OUT
V(DRP)
Calculate Input Filter Capacitor Current Ripple
The procedure below assumes that phases do not overlap
and output inductor ripple current (P−P) is less than the
average output current of one phase.
DVR + DI
ConverterZ
OUT
Make sure that ΔVR is less than the expected peak
transient for a good transient response.
9. Calculate Input Current
5. Adjust L and R or R as required to meet the best
V
I
OUT
L
S
OUT
Efficiency V
I
+
IN
(
)
combination of transient response, steady state output
voltage ripple and pulse width jitter.
IN
10. Calculate Duty Cycle (per phase).
Current Limit
When the sum of the Current Sense amplifiers (V
V
OUT
Efficiency V
Duty Cycle +
)
(
)
ITOTAL
IN
exceeds the voltage on the I
mode. For inductive sensing the I
set based on the inductor resistance (or current sense
resistor) at max temperature and max current. To set the level
pin the part will enter hiccup
LIM
11. Calculate Apparent Duty Cycle.
pin voltage should be
LIM
Apparent Duty Cycle + Duty Cycle # of Phases
12. Calculate Input Filter Capacitor Ripple Current. Use
the chart in Figure 16 to calculate the normalized
of the I
pin:
LIM
ripple current (K ) based on the reciprocal of
RMS
6. V
+ R I
CS to I
Gain
LIM
I(LIM)
OUT(LIM)
Apparent Duty Cycle. Then multiply the input current
by K to obtain the Input Filter Capacitor Ripple
where:
RMS
R is R or R
L
S;
Current.
I
is the current limit threshold.
OUT(LIM)
Ripple (RMS) + I K
IN
RMS
For the overcurrent to work properly the inductor
time constant (L/R) should be ≤ the Current sense RC.
If the RC is too fast, during step loads the current
waveform will appear larger than it is (typically for a
few hundred μs) and may trip the current limit at a
level lower than the DC limit.
4.00
3.50
3.00
2.50
2.00
1.50
Adaptive Positioning
7. To set the amount of voltage positioning below the
DAC setting at no load connect a resistor (R
1.00
0.50
0.00
)
V(FB)
between the output voltage and the V pin. Choose
FB
15
10
5
0
R
V(FB)
as;
1/ Apparent Duty Cycle
Figure 16. Normalized Input Filter Capacitor
Ripple Current
R
+ NL PositionńV Bias Current
FB
V(FB)
See Figure 4 for V Bias Current.
FB
8. To set the difference in output voltage between no
load and full load, connect a resistor (R
DESIGN EXAMPLE
)
V(DRP)
Choose the component values for a 12 V to 1.6 V, 35 A
converter with lossless current sensing, adaptive positioning
and a 45 A current limit. The adaptive positioning is chosen
between the V
and V pins. R
can be
DRP
FB
V(DRP)
calculated in two steps. First calculate the difference
between the V and V pin at full load. (The V
FB
DRP
FB
30 mV above the nominal V
at no load and 40 mV below
OUT
voltage should be the same as the DAC voltage during
closed loop operation.) Then choose the R to
the no−load position with 35 A out. The peak output voltage
transient is 70 mV max during a 32 A step current.
V(DRP)
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16
CS5322
Current Sensing, Power Stage and
Output Filter Components
1. Assume 1.5 mΩ of output filter ESR.
2.
Adaptive Positioning
7.
R
V(FB)
+ NL PositionńV
Bias Current
FB
+ 30 mVń6.0 mA + 5.0 kW
V
ńV
OUT IN
+ (V * V
)
R
IN
OUT
8.
F C 25 mV
1.6ń12
250 k 0.01 mF 25 mV
+ R I
Current Sense to V
DV
L
OUT
DRP
+ (12 * 1.6)
+ 22 kW
Gain
DRP
+ 2.0 mW 35 A 3.0
+ 210 mV
LńR + .01 mF 20 kW + 200 ms
L
+ DV
DRP
+ 210 mV 5.0 kWń40 mV
R
ńDV
V(FB) OUT
R
V(DRP)
Choose R + 2.0 mW
L
L + 2.0 mW 200 ms + 400 nH
+ 26 kW
3. n/a
4.
9.
41 A
0.85 12V
PwrstgZ+ R CSA Gainń2.0
I
+ 1.52 V
+ 6.1 A
L
IN
IN
+ 2.0 mW 3.15ń2.0 + 3.1 mW
10.
PwrstgZ ESR
1.52 V
0.85 12 V
Duty Cycle +
+ 0.15
+
+
ConverterZ
IN
PwrstgZ ) ESR
3.1 mW 1.5 mW
3.1 mW ) 1.5 mW
11.
^ 1.0 mW
Apparent Duty Cycle + 0.15 2.0 + 0.3
12.
DVR + 1.0 mW 32 A + 32 mV
RMS ripple + 6.1 A 1.5 + 9.2 A
5. n/a
Current Limit
6.
V
I(LIM)
+ R I
L
OUT(LIM)
CS to I Gain
LIM
+ 2.0 mW 45 A 6.25
+ 562 mV
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17
CS5322
ADDITIONAL APPLICATION DIAGRAMS
300 nH
+5.0 V
+
3 ×
1.0 μF
1.0 μF
6SP680M
1.0 μF
ENABLE
470 nH
61.9 k
1.0 nF
1.0 nF
COMP
R
+
OSC
CCL
V
8 ×
V
FB
7.5 k
12.7 k
V
V
4SP820M
CCL1
DRP
25.5 k
CS1
CS2
GATE(L)1
GND1
GATE(H)1
CS
V
OUT
REF
V
CCH1
PWRGD
PWRGD
LGND
SS
V
V
V
ID0
ID1
ID2
12 ×10 μF
V
V
CCL2
ID0
0.1 μF
GATE(L)2
V
V
ID3
ID4
GND2
V
V
ID1
ID2
I
GATE(H)2
LIM
V
CCH2
REF
V
V
ID3
ID4
4.82 k
1.0 k
0.1 μF
1.0 μF
470 nH
25.5 k
.01 μF
25.5 k
.01 μF
.01 μF
Figure 17. 5.0 V only to 1.6 V, 35 A
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18
CS5322
ADDITIONAL APPLICATION DIAGRAMS
300 nH
+5.0 V
+
3 ×
6SP680M
1.0 μF
1.0 μF
1.0 μF
ENABLE
3.3 nF
4.12 k
10 k
1.2 μH
61.9 k
1.0 nF
1.0 nF
R
COMP
FB
+
3 ×
4SP820M
OSC
V
V
V
CCL
4.12 k
V
CCL1
DRP
34.8 k
CS1
GATE(L)1
GND1
CS2
CS
25.5 k
GATE(H)1
V
REF
OUT
V
PWRGD
CCH1
PWRGD
LGND
SS
V
V
V
ID0
ID1
ID2
ID3
ID4
3 ×10 μF
V
V
CCL2
ID0
0.1 μF
GATE(L)2
V
V
GND2
V
V
ID1
ID2
GATE(H)2
I
LIM
V
CCH2
REF
V
V
ID3
ID4
2.80 k
1.0 k
0.1 μF
1.0 μF
1.2 μH
49.9 k
49.9 k
.01 μF
.01 μF
.01 μF
820 Ω
2.0 k
820 Ω
1.0 nF
1.0 nF
0.1 μF
0.1 μF
GATE(L)1
2.0 k
GATE(L)2
MMBT2222LT1
MMBT2222LT1
Figure 18. 5.0 V only to 2.5 V Converter
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19
CS5322
ADDITIONAL APPLICATION DIAGRAMS
300 nH
1.0 μF
+5.0 V
+
+
+
+12 V
6SP680M
Q1
Q3
Q2
Q4
1.0 μF
V
OUT
ENABLE
470 nH
61.9 k
1.0 nF
7.5 k
1.0 nF
U1
R
COMP
OSC
V
V
8 ×
4SP820M
CCL
FB
V
V
CCL1
DRP
CS1
CS2
25.5 k
12.7 k
GATE(L)1
GND1
GATE(H)1
CS
PWRGD
REF
V
PWRGD
CCH1
LGND
SS
V
V
V
ID0
ID1
ID2
12 ×10 μF cer
V
V
ID0
V
CCL2
0.1 μF
GATE(L)2
V
V
ID3
ID4
GND2
ID1
ID2
I
GATE(H)2
LIM
V
CCH2
REF
V
V
Q5
Q7
Q6
ID3
4.32 k
1.0 k
0.1 μF
V
ID4
470 nH
Q8
25.5 k
.01 μF
25.5 k
.01 μF
0.1 μF
Figure 19. 5.0 V only to 1.2 V Bias to 1.6 V, 35 A
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20
CS5322
PACKAGE DIMENSIONS
SOIC
DW SUFFIX
CASE 751F−05
ISSUE F
D
NOTES:
A
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
28
15
1
14
MILLIMETERS
B
PIN 1 IDENT
DIM MIN
MAX
2.65
0.29
0.49
0.32
18.05
7.60
A
A1
B
C
D
E
2.35
0.13
0.35
0.23
17.80
7.40
L
0.10
e
1.27 BSC
H
L
10.05
0.41
0
10.55
0.90
8
e
C
q
_
_
SEATING
PLANE
B
C
q
M
S
S
B
0.025
C A
PACKAGE THERMAL DATA
Parameter
28 Lead SO Wide
Unit
R
R
Typical
Typical
15
75
°C/W
°C/W
Θ
JC
JA
Θ
2
V
is a trademark of Switch Power, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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