E7111-0-102A19-AG [ONSEMI]
音频处理器，用于助听器的 DSP;
| 型号： | E7111-0-102A19-AG |
| 厂家： | 
ONSEMI |
| 描述： | 音频处理器，用于助听器的 DSP |
| 文件： | 总16页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Audio Processor for Digital
Hearing Aids
SIP19
CASE 127ES
EZAIRO 7111 HYBRID
Introduction
MARKING DIAGRAM
®
Ezairo 7111 is an open−programmable DSP−based hybrid
specifically designed for use in high−performance hearing aid and
hearing implant devices. The Ezairo 7111 hybrid includes the
Ezairo 7100 System−on−Chip (SoC), with its high−precision
quad−core architecture that delivers 375 MIPS, without sacrificing
power consumption.
E7111−0
ZZZZZZ
NNNNN
(Top View)
The highly integrated Ezairo 7100 includes an optimized,
dual−Harvard CFX Digital Signal Processor (DSP) core and HEAR
Configurable Accelerator signal processing engine. It also features an
Arm Cortex −M3 Processor Subsystem that supports various types
of protocols for wireless communication. This block combines an
open−programmable controller with hardware accelerators for audio
coding and error correction support.
E7111−0 = Specific Device Code
ZZZZZZ
NNNNN
= Assembly Lot Code
= Serial Number
®
ꢀ
ORDERING INFORMATION
Ezairo 7100 also includes a programmable Filter Engine that
enables time domain filtering and supports an ultra−low−delay audio
path. When combined with non−volatile memory and wireless
transceivers, Ezairo 7100 forms a complete hardware platform.
The Ezairo 7111 hybrid contains the Ezairo 7100 SoC, 2 Mb
EEPROM storage and the necessary passive components to directly
interface with the transducers required in a hearing aid.
†
Device
E7111−0-102A19-AG
Package
Shipping
SIP19
(RoHS
Compliant)
250 / Tape &
Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications Bro-
chure, BRD8011/D.
Development Tools
Ezairo Preconfigured Suite (Pre Suite)*
The Ezairo Pre Suite provides a complete framework to easily
develop Ezairo−based hearing aids and fitting software. Included in
the Ezairo Pre Suite is a firmware bundle, configuration software, and
a cross−platform Software Development Kit (SDK) to develop your
own fitting software.
Open−Programmable Evaluation and Development Kit (EDK)
To develop your own firmware on Ezairo 7111, the Ezairo 7100
Evaluation and Development Kit (EDK) includes optimized hardware,
programming interface, and a comprehensive Integrated Development
Environment (IDE).
Note: This datasheet describes all features of the Ezairo 7111 hybrid
module. Not all of these features are available using the Ezairo
Preconfigured Suite.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
April, 2022 − Rev. 4
E7111/D
EZAIRO 7111 HYBRID
KEY FEATURES
• Programmable Flexibility: the open−programmable
• Ultra−low Delay: programmable Filter Engine
supports an ultra−low−delay audio path of 0.044 ms
(44 ms) for superior performance of features such as
occlusion management.
DSP−based system can be customized to the specific
signal processing needs of manufacturers. Algorithms
and features can be modified or completely new
concepts implemented without having to modify the
chip.
• Ultra−high Fidelity: 85 dB system dynamic range with
up to 110 dB input signal dynamic range,
• Fully Integrated Hybrid: includes the Ezairo 100
SoC, 2 Mbit EEPROM storage and the necessary
passive components to directly interface with the
transducers required in a hearing aid.
• Quad−core Architecture: includes a CFX DSP, a
HEAR Configurable Accelerator, an Arm Cortex−M3
Processor Subsystem and a programmable Filter
Engine. The system also includes an efficient
input/output controller (IOC), system memories, input
and output stages along with a full complement of
peripherals and interfaces.
• CFX DSP: a highly cycle−efficient, programmable core
that uses a 24−bit fixed−point, dual−MAC,
dual−Harvard architecture.
• HEAR Configurable Accelerator: a highly optimized
signal processing engine designed to perform common
signal processing operations and complex standard
filterbanks.
exceptionally−low system noise and low group delay.
• Ultra−low Power Consumption: <0.7 mA @
10.24 MHz system clock (executing a tight MAC−loop
in the CFX DSP core plus a typical hearing aid
filterbank on the HEAR Configurable Accelerator).
• High Output Level: output levels of ~139 dB SPL
possible with low impedance receiver (measured using
IEC 711 coupler).
• Diverse Memory Architecture: a total of 40 kwords of
program memory and 44 kwords of data memory,
shared between the four cores included on the
Ezairo 7100 chip.
• Data Security: sensitive program data can be encrypted
for storage in EEPROM to prevent unauthorized parties
from gaining access to proprietary algorithm
intellectual property.
• Signal Detection Unit: ultra−low−power detection
system for signals on any analog inputs.
• Arm Cortex−M3 Processor Subsystem: a complete
subsystem that supports efficient data transfer to and
from a wireless transceiver. The subsystem includes
hardwired CODECS (G.722, CVSD) and Error
Correction support (Reed−Solomon, Hamming), as well
as a fully programmable Arm Cortex−M3 processor and
dedicated interfaces. It is compatible with various
wireless technologies (NFMI, RF).
• Programmable Filter Engine: a filtering system that
allows applying a various range of pre− or
post−processing filtering, such as IIR, FIR and biquad
filters.
• Configurable System Clock Speeds: 1.28 MHz,
1.92 MHz, 2.56 MHz, 3.84 MHz, 5.12 MHz, 6.4 MHz,
7.68 MHz, 8.96 MHz, 9.60 MHz, 10.24 MHz* (default
clock calibration), 12.80 MHz and 15.36 MHz to
optimize the computing performance versus power
consumption ratio. The calibration for these 12 clock
speeds are stored in the manufacturing area of the
EEPROM.
• High Throughput Communication Interface: fast
2
I C−based interface for quick download, debugging and
general communication.
• Highly Configurable Interfaces: two PCM interfaces,
2
two I C interfaces, two SPI interfaces, a UART
interface as well as multiple GPIOs can be used to
stream configuration, control or signal data into and out
of the Ezairo 7111 hybrid.
• On−chip PLL: support for communication
synchronization with wireless transceiver.
• Glueless MMI: link to various analog and digital user
interfaces such as analog or digital volume control
potentiometers, push buttons for program selection and
microphone/telecoil switching.
• Fitting Support: support for Microcard, HI−PRO 2,
HI−PRO USB, QuickCom, and NOAHlink, including
NOAHlink’s audio streaming feature.
• These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
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2
EZAIRO 7111 HYBRID
Table 1. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
2
Unit
V
VBAT
VBATOD
Vin
Power supply voltage
Output drivers power supply voltage
Voltage at any input pin
2
V
GNDC−0.3
VDDO +
0.3
V
GNDC, GNDA
T functional
T operational
T storage
Digital and Analog Grounds
0
−
V
Functional temperature range (Note 1)
Operational temperature range (Note 1)
Storage temperature range
−40
0
85
50
85
°C
°C
°C
−40
Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Electrical Specification may exceed listed tolerances when out of the temperature range 0°C to 50°C.
Electrical Performance Specifications
The tests were performed at 20°C with a 1.25 V supply voltage and 4.7 W series resistor to simulate a nominal hearing aid
battery. The system clock (SYS_CLK) was set to 5.12 MHz and an audio input sampling frequency of 16 kHz was used.
Parameters marked as screened are tested on each chip.
Table 2. ELECTRICAL SPECIFICATIONS
Description
OVERALL
Symbol
Conditions
Min
Typ
Max
Unit
Screened
Supply Voltage
VBAT
Supply voltage measured
at the VBAT pin
1.05
1.25
700
2.0
V
Current consumption
I
Filterbank: 30% load CFX:
100% load SYS_CLK:
10.24 MHz
−
−
mA
VBAT
Ezairo Pre Suite firmware
bundle running at 10.24
MHz, all algorithms active,
no transducers connected.
−
1090
−
mA
Stand by current
Istb
Using ON’s macro
40
120
mA
VREG
Regulated voltage
output
VREG
Trimmed bandgap
load
0.96
0.97
0.98
V
√
I
= 100 mA
Regulator PSRR
Load current
Load regulation
Line regulation
VDDA
VREG
1 kHz, VBAT = 1.25 V
76
−
80
−
−
2
dB
mA
PSRR
I
LOAD
LOAD
5 mA < I
< 2 mA
−
4
10
5
mV/mA
mV/V
REG
load
LINE
I
= 1 mA
−
2
REG
load
Output voltage
trimming range
VDDA
Control register
configured, typical values
1.8
2.0
2.1
V
√
Regulator PSRR
Load current
VDDA
1 kHz, VBAT = 1.25 V
40
−
50
−
−
1
dB
mA
PSRR
I
LOAD
Load regulation
LOAD
VBAT = 1.2 V; 100 mA <
load
−
4
10
mV/mA
REG
I
< 1 mA
Line regulation
LINE
1.2 V < VBAT < 1.86 V;
= 100 mA
−
6
20
mV/V
REG
I
load
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3
EZAIRO 7111 HYBRID
Table 2. ELECTRICAL SPECIFICATIONS
Description
VDBL
Symbol
Conditions
Min
Typ
Max
Unit
Screened
Output voltage
trimming range
VDBL
Control register
configured, typical values,
unloaded
1.6
2.0
2.2
V
√
Regulator PSRR
Load current
VDBL
1 kHz, VBAT = 1.25 V
30
40
−
dB
PSRR
I
ITRIM
(A_CP_VDBL_CTRL) =
0x7
−
−
15
mA
LOAD
Load regulation
Line regulation
VDDC
LOAD
VBAT = 1.2 V; 100 mA <
load
−
−
4
6
10
20
mV/mA
mV/V
REG
I
< 3 mA
LINE
VBAT > 1.2 V; I
=
REG
load
100 mA
Digital supply output
voltage trimming
range
VDDC
Control register
configured, typical values,
unloaded
0.72
1.5
−
1.32
3
V
√
√
(Note 2)
VDDC output level
adjustment
VDDC
VDDC
2.5
mV
STEP
Regulator PSRR
Load current
1 kHz, VBAT = 1.25 V
Delivered by LDO
25
−
30
−
−
5
dB
mA
PSRR
I
LOAD
Load regulation
Line regulation
LOAD
−
5
10
12
mV/mA
mV/V
REG
LINE
−
6
REG
2. Recommended VDDC values depend on the system clock (SYS_CLK) frequency. Table 3 gives the recommended VDDC values for
different system clocks.
VDDM
Memory supply
output voltage
trimming range
VDDM
Control register
configured, typical values,
unloaded
0.82
1.5
−
1.32
3
V
√
√
(Note 3)
VDDM output level
adjustment
VDDM
2.5
mV
STEP
Regulator PSRR
Load current
VDDM
1 kHz, VBAT = 1.25 V
Delivered by LDO
25
−
30
−
−
5
dB
mA
PSRR
I
LOAD
Load regulation
Line regulation
LOAD
−
5
10
12
mV/mA
mV/V
REG
REG
LINE
−
6
3. The minimum VDDM value required for proper system functioning is 0.90 V.
POWER−ON−RESET
POR startup voltage
VBAT
−
−
0.9
−
−
V
V
√ (Note 4)
√ (Note 5)
STARTUP
POR shutdown
voltage
VBAT
0.88
SHUTDOWN
4. Pass fail test with 0.855 V and 0.945 V
5. Pass fail test with 0.835 V and 0.925 V
INPUT STAGE
Analog input voltage
range
V
IN
0
−
2
V
Preamplifier gain
PAG
3 dB steps
0
−
36
dB
dB
√
√
Preamplifier gain
accuracy
PAG acc
1 kHz, PAG from 0 to
36 dB
−1.5
0
1.5
Input impedance
R
Non−0 dB preamplifier
gains
370
500
725
kW
√
IN
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4
EZAIRO 7111 HYBRID
Table 2. ELECTRICAL SPECIFICATIONS
Description
INPUT STAGE
Symbol
Conditions
Min
Typ
Max
Unit
Screened
Input referred noise
IN
IRN
mVrms
AIR connected to AGND
Unweighted, 100 Hz to
10 kHz BW
Preamplifier settings:
0 dB
53
13
−
−
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB
33 dB
36 dB
9
−
6.6
4.9
4.3
3.7
3.2
3.2
3.2
10.6
−
√
−
−
−
−
−
Input Dynamic Range
IN
DR
dB
AIR connected to AGND
Unweighted, 100 Hz to
10 kHz BW
Preamplifier settings:
86
86
86
86
85
82
82
80
77
74
0 dB
−
−
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB
33 dB
36 dB
−
81
−
√
−
−
−
−
−
Any preamplifier gain
−10 dBFS signal at
preamp output, 1kHz.
Input peak THD+N
IN
THD+N
−
−
−68
dB
√
OUTPUT DRIVER
Maximum peak
current
I
High Power mode
−
−
25
mA
DO
Output impedance
Output impedance
R
R
Normal mode, I
= 1 mA
−
−
4.5
2.5
−
5.5
4
W
W
DO
DO
load
High Power mode
Output dynamic
range
DO
Normal mode,
VBAT = 1.25 V
90
−
dB
DR
Output THD+N
DO
At 1 kHz, −6 dBFS, 8 kHz
bandwidth, VBAT = 1.25 V,
normal mode
−
−78
−76
dB
THDN
10−BIT LOW−SPEED A/D
Input voltage range
INL
LSAD
LSAD
Peak input voltage
0
−4
−2
−
−
−
1.94
+4
+2
−
V
√
RANGE
LSAD
From GND to 2*VREG
From GND to 2*VREG
All channels sequentially
LSB
LSB
kHz
kHz
INL
DNL
−
DNL
Sampling frequency
LSAD
12.8
1.6
SF
Channel sampling
frequency
LSAD
−
−
CH_SF
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5
EZAIRO 7111 HYBRID
Table 2. ELECTRICAL SPECIFICATIONS
Description
Symbol
Conditions
Min
Typ
Max
Unit
Screened
SIGNAL DETECTION UNIT
Preamplifier gain
SDU
3dB steps
0
−
−
36
20
dB
√
√
PAG
Equivalent IRN
SDU
Non−weighted, 30 dB
gain, 100 Hz − 10 kHz
−
mVrms
IRN
Input impedance
SDU
370
−1
1
500
50
725
+1
64
-
kW
√
R
Low Pass Filter
Bandwidth
SDU
kHz
LPF
ADC input signal
range
SDU
Referred to VREG
V
RANGE
ADC resolution
SDU
12
bits
RES
ADC sampling
frequency
SDU
At slow_clock = 1.28 MHz
kHz
SF
DIGITAL
Voltage level for high
input
V
IH
V
V
*
*
-
-
V
V
√
√
√
√
√
DDO
0.8
Voltage level for low
input
V
IL
-
V
DDO
* 0.2
Voltage level for high
output
V
OH
2mA source current
2mA sink current
-
V
DDO
0.8
Voltage level for low
output
V
OL
-
-
V
V
DDO
* 0.2
Oscillator frequency
trimming precision
SYS_CLK
SYS_CLK
−1
−
−
+1
%
%
Oscillator frequency
stability over
temperature
Over temperature range of
0°C to 50°C
−1.5
+1.5
Recommended
SYS_CLK
For recommended VDDC
and VDDM
1.28
−
−
15.36
400
MHz
ps
working frequency
Oscillator period jitter
RMS at System clock:
1.28 MHz, before
multiplication
−
PLL lock time
For an input phase error
<2%, input reference clock
of 128 kHz, output clock of
2.56 MHz
−
−
10
ms
√
PLL tracking range
LOW DELAY PATH
Group Delay
−2
−
2
%
Using the low delay path
of the Filter Engine
−
44
−
ms
EEPROM
EEPROM burn cycles
Per EA2M datasheet
1’000’000
−
−
Cycles
mA
Current consumption
– writing to EEPROM
I
W
V
DBL
= 1.6 V,
0.7
SPI_CLK = 5 MHz
Current consumption
– read from
EEPROM
I
R
V
= 1.6 V,
0.4
mA
DBL
SPI_CLK = 5 MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
EZAIRO 7111 HYBRID
Table 3. RECOMMENDED MINIMUM VDDC LEVELS
Operating Frequency (MHz)
1.28 to 5.12
Minimum VDDC Voltage (V)
0.73
5.13 to 10.24
0.82 (Note 6)
0.85
10.25 to 12.80
12.81 to 15.36
0.88 (Note 7)
6. The default VDDC calibration entry, stored in the manufacturing area of the EEPROM at address 0x0064, should be used for operation at
0.82 V.
7. An alternate VDDC calibration entry, stored in the manufacturing area of the EEPROM at address 0x00E8, should be used for operation at
0.88 V.
PACKAGING AND MANUFACTURING
• Ultra−miniature form factor: suitable for all hearing aid
styles including CIC, ITE, RITE, BTE, and mini−BTE.
• Can easily be soldered by hand.
• RoHS compliant: the Ezairo 7111 hybrid complies with
the RoHS directive.
SYSTEM DIAGRAM
• Re−flowable: the Ezairo 7111 hybrid is re−flowable
Figure 1 is a simplified diagram of the hybrid system that
shows the major internal functional blocks and possible
external peripherals.
onto FR4 and other substrates.
• Bump metallization: SAC305 (Sn96.5/Ag3.0/Cu0.5)
Down-
Preamplifier
Up-
sampling
Output
Driver
sampling
A/D
Zero-bias
Receiver
System
Memories
A/D
A/D
A/D
DAI
Interfaces
GPIO
Telecoil
Pushbuttons/
Switches
Signal
Detection Unit
CFX
HEAR
I2C
24-bit DSP
Configurable Accelerator
Fitting Connector
Volume Control
LSAD
On-Chip Peripherals
Power
Timers
ARM® Cortex® -M3
Processor
Filter Engine
Programmable Filters
UART
Management
Battery
Interrupt
Controller
IP
SPI
PCM
Protection
EEPROM
Advanced CODECs
Error Correction Blocks
VCO
PLL
I2C
PCM
SPI
GPIO
Figure 1. Ezairo 7111 Hybrid System Diagram
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7
EZAIRO 7111 HYBRID
Ezairo 7111 HYBRID INTERFACE SPECIFICATIONS
A total of 19 pads are present on the Ezairo 7111 hybrid. These pads are the interfaces between the hybrid and the other
components in the hearing aid. They are listed in Table 4 along with the internal connections.
Table 4. PAD DESCRIPTION
Ball Number
Hybrid Pad Name
AI0
Hybrid Pad Description
Analog Input 0: Microphone or Telecoil Input
A1
A2
A3
A4
A5
A6
A7
A8
B1
B3
B8
C1
C2
C3
C4
C5
C6
C7
C8
MIC_VREG
GND_MIC
DIO24
DIO23
DIO22
DIO21
VBAT
Regulated voltage for microphone
Input Transducer Ground
Digital Input Output 24
Digital Input Output 23
Digital Input Output 22
Digital Input Output 21
Power Supply
AI1
Analog Input 1: Microphone or Telecoil Input
Analog Input 3: Direct Analog Input
Output Stage Power Supply
Analog Input 2: Microphone or Telecoil Input
Regulated voltage output
Ground
AI3
RCVR_BAT
AI2
VREG
GND
DIO25
RCVR0P
RCVR0N
SCL
Digital Input Output 25
Receiver Output 0 Positive
Receiver Output 0 Negative
Debug Port Clock
SDA
Debug Port Data
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EZAIRO 7111 HYBRID
Ezairo 7111 HYBRID SCHEMATICS
V D B L
2 5
V D D M
V D D C
V B A T
V D D A
4 8
V D D 4 2 C
2 4
G N D C
4 4
G N D O
4 0
2 6
Figure 2. Ezairo 7111 Hybrid Schematics
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9
EZAIRO 7111 HYBRID
CONNECTION DIAGRAM
The following connections are typical when Ezairo 7111 is used in a hearing aid application. For details on the connections
required by the preconfigured firmware bundle refer to AND9677/D.
Figure 3. Connection Diagram (hybrid view: bottom view)
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10
EZAIRO 7111 HYBRID
ARCHITECTURE OVERVIEW
The Ezairo 7100 system is an asymmetric quad−core
• Directional processing
• Feedback cancellation
architecture, mixed−signal system−on−chip designed
specifically for audio processing. It centers around four
processing cores: the CFX Digital Signal Processor (DSP),
the HEAR Configurable Accelerator, the Arm Cortex−M3
Processor Subsystem, and the Filter Engine.
• Noise reduction
To execute these and other algorithms efficiently, the
HEAR excels at the following:
• Processing using a weighted overlap add (WOLA)
filterbank
CFX DSP Core
The CFX DSP core is used to configure the system and the
other cores, and it coordinates the flow of signal data
progressing through the system. The CFX DSP can also be
used for custom signal processing applications that can’t be
handled by the HEAR or the Filter Engine.
The CFX DSP is a user−programmable general−purpose
DSP core that uses a 24−bit fixed−point, dual−MAC,
dual−Harvard architecture. It is able to perform two MACs,
two memory operations and two pointer updates per cycle,
making it well−suited to computationally intensive
algorithms.
• Time domain filtering
• Subband filtering
• Attack/release filtering
• Vector addition/subtraction/multiplication
• Signal statistics (such as average, variance and
correlation)
Arm Cortex−M3 Processor Subsystem
The Arm Cortex−M3 Processor Subsystem provides
support for data transfer to and from the wireless transceiver.
The subsystem includes hardwired CODECS (G.722,
CVSD), Error Correction support (Reed−Solomon,
Hamming), interfaces (SPI, I C, PCM, GPIOs), as well as an
open−programmable Arm Cortex−M3 processor.
The CFX features:
• Dual−MAC 24−bit load−store DSP core
• Four 56−bit accumulators
• Four 24−bit input registers
2
Arm Cortex−M3 Processor
• Support for hardware loops nested up to four deep
• Combined XY memory space (48 bits wide)
• Dual address generator units
The Arm Cortex−M3 processor is a low−power processor
that features low gate count, low interrupt latency, and
low−cost debugging. It is intended for deeply embedded
applications that require fast interrupt response features.
GNU tools provide build and link support C programs that
run on the Arm Cortex−M3 processor.
• A wide range of addressing modes:
− Direct
− Indirect with post−modification
− Modulo addressing
− Bit reverse
Filter Engine
The Filter Engine is a core that provides low−delay path
and basic filtering capabilities for the Ezairo 7100 system.
The Filter Engine can implement filters (either FIR or IIR)
with a total of up to 160 coefficients. FIR filters are
implemented using a direct−form structure. IIR filters are
implemented with a cascade of second−order sections
(biquads), each implemented as a direct−form I filter.
The Filter Engine is programmable, but does not include
direct debugging access. The CFX can monitor the Filter
Engine state through control and configuration registers on
the program memory bus.
For further information on the usage of the CFX DSP,
please refer to the Hardware Reference Manual and to the
CFX DSP Architecture Manual available in the Ezairo 7100
Evaluation and Development Kit (EDK).
HEAR Configurable Accelerator
The HEAR coprocessor is designed to perform both
common signal processing operations and complex standard
filterbanks such as the WOLA filterbank, reducing the load
on the CFX DSP core.
The HEAR Configurable Accelerator is a highly
optimized signal processing engine that is configured
through the CFX. It offers high speed, high flexibility and
high performance, while maintaining low power
consumption. For added computing precision, the HEAR
supports block floating point processing. Configuration of
the HEAR is performed using the HEAR configuration tool
(HCT). For further information on the usage of the HEAR,
please refer to the HEAR Configurable Accelerator
Reference Manual available in the Ezairo 7100 EDK.
The HEAR is optimized for advanced hearing aid
algorithms including but not limited to the following:
Digital Input/Output (DIO) Pads
A total of 5 DIOs are available on the Ezairo 7111 hybrid.
These pads can all be configured for a variety of digital input
and output modes or as LSADs. The user can configure
DIOs signal to be, for example:
• CFX PCM interface
• CFX UART interface
• CFX SPI interface
• LSAD input
• GPIOs data for the CFX
• Dynamic range compression
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11
EZAIRO 7111 HYBRID
PRE SUITE FIRMWARE BUNDLE
• Arm Cortex−M3 processor PCM interface
• Arm Cortex−M3 processor SPI interface
The Pre Suite Firmware Bundle of Ezairo 7111 comprises
a real−time framework and suite of advanced sound
processing algorithms ideal for high−end, full featured
hearing aids (available under NDA). For additional details
about the Pre Suite firmware bundle for Ezairo 7111 refer to
Ezairo 7111 Firmware Bundle User’s Guide.
2
• Arm Cortex−M3 processor I C interface
• Arm Cortex−M3 processor GPIOs
More details on the Ezairo 7111 external interfaces can be
found in the Ezairo 7100 Hardware Reference Manual
available in the Ezairo 7100 EDK.
The 5 DIOs are brought out of the Ezairo 7111 hybrid:
DIO21, DIO22, DIO23, DIO24 and DIO25. The associated
power domain is defined by VDDO3. VDDO3 is connected
to Vbat inside the hybrid.
The SDA and SCL pads are on the VDDO3 power
domain.
DEFAULT APPLICATION ON EZAIRO 7111
The default application includes functionality that allows
the application of the Ezairo 7111 to be updated to the latest
Pre Suite version using Sound Designer/SDK. It leaves the
debug port of Ezairo 7111 in Restricted Mode.
For customers using the Ezairo 7111 as an
open−programmable device, it is possible to erase the
default application and replace it with your own firmware
image. This can be done using the Ezairo 7100 IDE or in a
script using the Jump ROM functions ”Wipe” and ”Unlock”
to place the device in Unrestricted Mode. Refer to the
Communication Protocols Manual for Ezairo 7100 for more
information.
Debug Ports
2
2
The CFX’s I C interfaces share the same I C bus within
the Ezairo 7100 chip with two other I C interfaces:
2
2
CFX Debug Port I C
The CFX debug port I C interface is a hardware debugger
2
for the Ezairo 7100 system that is always enabled regardless
2
of the configuration of the general−purpose I C interface.
The debug port implements the debug port protocol
command set and is tightly coupled with the CFX DSP and
the memory components attached to the CFX. The default
address is 0x60.
FREQUENCY RESPONSE GRAPH
Conditions
SYS_CLK = 10.24 Mhz
Firmware: Simple FIFO copy application
Gain normalized to 0 dB at 1 kHz
2
Arm Cortex−M3 Processor Debug Port I C
The Arm Cortex−M3 processor debug port I C interface
2
is a hardware debugger for the Ezairo 7100 system that is
always enabled regardless of the configuration of the
general−purpose I C interface. The debug port implements
Measurements taken electrically with a two−pole RC
filter on the output with a cutoff frequency (−3 dB point) of
8 kHz. From 2 kHz to 8 kHz, the roll−off is due to the RC
filter.
2
an
Arm Cortex−M3 processor debug port protocol command
set that is tightly coupled with the Arm Cortex−M3
processor and the memory components attached to this core.
The default address is 0x40.
Figure 4. Frequency Response Graph
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12
EZAIRO 7111 HYBRID
System Identification
Solder Information
System identification is used to identify different system
components. This information can be retrieved using the
Promira Serial Platform from TotalPhase, Inc. Or the
Communications Accelerator Adaptor (CAA) and some
protocol software provided by ON Semiconductor (see
CAA instruction manual). For the Ezairo 7100 chip, the key
identifier components and values are as follows:
• Chip Family: 0x06
• Chip Version:0x01
• Chip Revision: 0x0200
The Ezairo 7111 hybrid is constructed with all RoHS
compliant material and should therefore be reflowed
accordingly.
This hybrid device is Moisture Sensitive Class MSL3 and
must be stored and handled accordingly. Re−flow according
to IPC/JEDEC standard J−STD−020C, Joint Industry
Standard: Moisture/Re−flow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices.
For soldering guidelines, please refer to the Soldering and
Mounting
Techniques
Reference
Manual
(SOLDERRM/D).
The hybrid ID can be found in the manufacturing area of the
EEPROM at address 0x00F1 to 0x00F2 (2 bytes => 16 bits)
• Hybrid ID: 0x00B0
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13
EZAIRO 7111 HYBRID
Electrostatic Discharge (ESD) Device
Company or Product Inquiries
CAUTION: ESD sensitive device. Permanent damage
may occur on devices subjected to high−energy electrostatic
discharges. Proper ESD precautions in handling, packaging
and testing are recommended to avoid performance
degradation or loss of functionality.
For more information about ON Semiconductor products
or services visit our web site at http://onsemi.com.
Technical Contact Information
dsp.support@onsemi.com
Development Tools
For more information on which development tools best
suit your product development, contact your local sales
representative or authorized distributor.
EZAIRO is a registered trademark of Semiconductor Components Industries, LLC. NOAHlink is a trademark of HIMSA A/S.
Bluetooth is a registered trademark of Bluetooth SIG, Inc. Arm and Cortex are registered trademarks of Arm Limited.
Promira is a trademark of Total Phase, Inc.
RHYTHM is a trademark of Semiconductor Components Industries, LLC.
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14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP19 5.25x2.90
CASE 127ES
ISSUE C
DATE 10 MAR 2022
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BUMPS.
E
A
B
MILLIMETERS
DIM
A
A1
A2
b
D
E
MIN
−−−
0.060
1.200
0.400
2.775
5.125
MAX
1.525
0.125
1.400
0.500
3.025
5.375
D
PIN 1
INDICATOR
e
e1
f
0.625 BSC
1.200 BSC
0.850 BSC
0.788 BSC
TOP VIEW
SIDE VIEW
g
L
0.800
0.900
0.13
0.05
C
C
RECOMMENDED
SOLDERING FOOTPRINT*
A2
A
5.125
15X
0.450
18X
1.000
1.213
A1
4X
0.600
SEATING
C
NOTE 3
0.850
PLANE
e
2.850
e/2
f
A1
A
B
0.625
PITCH
PACKAGE
OUTLINE
19X L
DIMENSIONS: MILLIMETERS
C
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1
2
3
4
5
6
7
8
19X b
0.05
0.03
e1
g
C
C
A B
GENERIC
MARKING DIAGRAM*
BOTTOM VIEW
XXXXXXXXXXXX
ZZZZZZ
NNNNN
XXXX = Specific Device Code
ZZZ = Assembly Lot Code
NNN = Serial Number
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30115G
SIP19 5.25X2.90
PAGE 1 OF 1
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