E7150-102A49-AG [ONSEMI]
音频处理器，用于助听器的无线功能 DSP;
| 型号： | E7150-102A49-AG |
| 厂家： | 
ONSEMI |
| 描述： | 音频处理器，用于助听器的无线功能 DSP 无线 |
| 文件： | 总19页 (文件大小：572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EZAIRO 7150 SL HYBRID
Wireless-Enabled Audio
Processor for Digital
Hearing Aids
Introduction
®
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EZAIRO 7150 SL is an open−programmable DSP−based hybrid
specifically designed for use in wirelessly connected,
high−performance hearing aids and hearing implant devices. The
Ezairo 7150 SL hybrid includes the Ezairo 7100 System−on−Chip
(SoC) with its high−precision quad−core architecture that delivers 375
MIPS, without sacrificing power consumption.
The highly−integrated Ezairo 7100 includes an optimized,
dual−Harvard CFX Digital Signal Processor (DSP) core and HEAR
Configurable Accelerator signal processing engine. It also features an
Arm Cortex −M3 Processor Subsystem that supports various types
of protocols for wireless communication. This block combines an
open−programmable controller with hardware accelerators for audio
coding and error correction support.
SIP49
EZAIRO
CASE 127DQ
®
®
MARKING DIAGRAM
Ezairo 7100 also includes a programmable Filter Engine that
enables time domain filtering and supports an ultra−low−delay audio
path. When combined with non−volatile memory and wireless
transceivers, Ezairo 7100 forms a complete hardware platform.
The Ezairo 7150 SL hybrid includes the nRF51822 wireless
transceiver from Nordic Semiconductor. The nRF51822 is a powerful,
E7150−102
XXXXXX
(Top View)
E7150−102 = Specific Device Code
XXXXXX = Work Order Number
®
highly flexible multi−protocol SoC ideally suited for Bluetooth Low
Energy (BLE) and 2.4 GHz ultra−low−power wireless applications.
Ezairo 7150 SL also contains 2 Mb EEPROM storage and the
necessary passive components to directly interface with the
transducers required in a hearing aid.
ORDERING INFORMATION
†
Device
Package
Shipping
E7150−102A49−AG
SIP49
(Pb−Free)
250 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
December, 2017 − Rev. 5
E7150/D
EZAIRO 7150 SL HYBRID
Key Features
• Programmable Flexibility: the open−programmable
• Ultra−low Power Consumption: <0.7 mA @ 10.24
MHz system clock (executing a tight MAC−loop in the
CFX DSP core plus a typical hearing aid filterbank on
the HEAR Configurable Accelerator).
DSP−based system can be customized to the specific
signal processing needs of manufacturers. Algorithms
and features can be modified or completely new
concepts implemented without having to modify the
chip.
• High Output Level: output levels of ~139 dB SPL
possible with low impedance receiver (measured using
IEC 711 coupler).
• Fully Integrated Hybrid: includes the Ezairo 7100
SoC, nRF51822 radio IC, 2 Mb EEPROM storage, and
the necessary passive components to directly interface
with the transducers required in a hearing aid.
• Diverse Memory Architecture: a total of 40 kwords of
program memory and 44 kwords of data memory,
shared between the four cores included on the Ezairo
7100 chip.
• Data Security: sensitive program data can be
encrypted for storage in EEPROM to prevent
unauthorized parties from gaining access to proprietary
algorithm intellectual property.
• Quad−core Architecture: includes a CFX DSP, a
HEAR Configurable Accelerator, an ARM Cortex−M3
Processor Subsystem, and a programmable Filter
Engine. The system also includes an efficient
Input/Output Controller (IOC), system memories, input
and output stages, along with a full complement of
peripherals and interfaces.
• Signal Detection Unit: ultra−low−power detection
system for signals on any analog inputs.
• CFX DSP: a highly cycle−efficient, programmable
core that uses a 24−bit fixed−point, dual−MAC,
dual−Harvard architecture.
• High Speed Communication Interface: fast
2
I C−based interface for quick download, debugging and
general communication.
• HEAR Configurable Accelerator: a highly optimized
signal processing engine designed to perform common
signal processing operations and complex standard
filterbanks.
• ARM Cortex−M3 Processor Subsystem: a complete
subsystem that supports efficient data transfer to and
from the wireless transceiver or multiple transceivers.
The subsystem includes hardwired CODECS (G.722,
CVSD) and Error Correction support (Reed−Solomon,
Hamming), as well as a fully programmable ARM
Cortex−M3 processor and dedicated interfaces.
• Highly Configurable Interfaces: two PCM interfaces,
2
two I C interfaces, two SPI interfaces, a UART
interface as well as multiple GPIOs can be used to
stream configuration, control or signal data into and out
of the Ezairo 7150 SL hybrid.
• On−chip PLL: support for communication
synchronization with wireless transceiver.
• Glueless MMI: link to various analog and digital user
interfaces such as analog or digital volume control
potentiometers, push buttons for program selection and
microphone/telecoil switching.
• Fitting Support: support for Microcard, HI−PRO 2,
HI−PRO USB, QuickCom, and NOAHlinkt, including
NOAHlink’s audio streaming feature.
• Programmable Filter Engine: a filtering system that
allows applying a various range of pre− or post−
processing filtering, such as IIR, FIR and biquad filters.
• Configurable System Clock Speeds: 1.28 MHz, 1.92
MHz, 2.56 MHz, 3.84 MHz, 5.12 MHz, 6.4 MHz, 7.68
MHz, 8.96 MHz, 9.60 MHz, 10.24 Mhz (default clock
calibration), 12.80MHz and 15.36MHz to optimize the
computing performance versus power consumption
ratio. The calibration entires for these 12 clock speeds
are stored in the manufacturing area of the EEPROM.
• Development Tools: The Ezairo Preconfigured Suite
provides a software application to fine−tune and
customize the firmware bundle pre−loaded on Ezairo
7150 SL. A cross−platform Software Development Kit
(SDK) to develop fitting software and wireless
applications is also provided. To program the Ezairo
7150 SL with your own firmware, the Ezairo 7100
Evaluation and Development Kit (EDK) includes
optimized hardware, programming interface, and a
comprehensive Integrated Development Environment
(IDE).
• Ultra−low Delay: programmable Filter Engine
supports an ultra−low−delay audio path of 0.044 ms (44
ms) for superior performance of features such as
occlusion management.
• Ultra−high Fidelity: 85 dB system dynamic range with
• These Devices are Pb−Free, Halogen Free/BFR Free
up to 110 dB input signal dynamic range,
and are RoHS Compliant.
exceptionally−low system noise and low group delay.
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2
EZAIRO 7150 SL HYBRID
Table 1. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Unit
V
VBAT
Power supply voltage
2
VBATOD
Output drivers power supply voltage
I/O supply voltage
2
V
VDDO
Vin
3.3 (Note 1)
V
1,2,3
Voltage at any input pin
GNDC−0.3
VDDO + 0.3
V
DGND, AGND, HGND
T functional
Digital and Analog Grounds
Functional temperature range (Note 2)
Operational temperature range (Note 2)
Storage temperature range
0
−
V
−40
0
85
50
85
°C
°C
°C
T operational
T storage
−40
Caution: Class 2 ESD Sensitivity, JESD22*A114*B (2000 V)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. In some applications, VDDO can be higher than 2.1 V (maximum 3.3 V). In such cases, the user must set the VDDM voltage at a minimum
of 1.1 V
2. Electrical Specification may exceed listed tolerances when out of the temperature range 0 to 50°C
Electrical Performance Specifications
The tests were performed at 20°C with a 1.25 V supply voltage and 4.7 W series resistor to simulate a nominal hearing aid
battery. The system clock (SYS_CLK) was set to 5.12 MHz and an audio input sampling frequency of 16 kHz was used.
Parameters marked as screened are tested on each chip.
Table 2. ELECTRICAL SPECIFICATIONS
Description
OVERALL
Symbol
Conditions
Min
Typ
Max
Units
Screened
Supply Voltage
VBAT
Supply voltage measured
at the VBAT pin
1.05
1.05
1.05
−
1.25
−
2.0
3.3
Vbat
−
V
V
I/O Supply Voltage
Domain 1,2
VDDO
1,2
I/O Supply Voltage
Domain 3
VDDO
−
V
3
Current consumption
I
Filterbank: 30% load CFX:
100% load SYS_CLK:
10.24 MHz. No activity on
the nRF51822
700
mA
VBAT
Ezairo Pre Suite firmware
bundle running at 10.24
MHz, all algorithms active,
no transducers connected,
no activity on the nRF51822.
−
1090
70
−
mA
mA
Stand by current
I
stb
Using ON’s macro to put
the Ezairo 7100 DSP in
Standby Mode. Include
30 mA coming from the
nRF51822 standby current.
150
VREG
Regulated voltage output
Regulator PSRR
Load current
VREG
VREG
I
=100 mA
0.96
76
−
0.97
80
−
0.98
−
V
dB
n
load
1 kHz, VBAT=1.25 V
PSRR
I
2
mA
LOAD
Load regulation
Line regulation
VDDA
LOAD
5 mA < Iload < 2 mA
−
4
10
5
mV/mA
mV/V
REG
REG
LINE
Iload = 1 mA
−
2
Output voltage trimming
range
VDDA
Control register configured,
typical values
1.8
40
2.0
50
2.1
−
V
n
Regulator PSRR
VDDA
1 kHz, VBAT=1.25V
dB
PSRR
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3
EZAIRO 7150 SL HYBRID
Table 2. ELECTRICAL SPECIFICATIONS
Description
Symbol
Conditions
Min
Typ
Max
Units
Screened
VDDA
Load current
I
−
−
−
4
1
mA
LOAD
Load regulation
LOAD
VBAT = 1.2 V; 100 _A <
Iload < 1 mA
10
mV/mA
REG
Line regulation
LINE
1.2 V < VBAT < 1.86 V;
Iload = 100 uA
−
6
20
mV/V
V
REG
VDBL
Output voltage trimming
range
VDBL
Control register configured,
typical values, unloaded
1.6
2.0
2.2
n
Regulator PSRR
Load current
VDBL
1 kHz, VBAT=1.25 V
30
−
40
−
−
dB
PSRR
I
ITRIM (A_CP_VDBL_CTRL)
= 0x7
15
mA
LOAD
Load regulation
LOAD
VBAT = 1.2 V; 100 mA <
Iload < 3 mA
−
−
4
6
10
20
mV/mA
mV/V
REG
Line regulation
LINE
VBAT > 1.2 V; Iload = 100 mA
REG
VDDC
Digital supply output volt-
age trimming range
VDDC
Control register configured,
typical values, unloaded
0.72
1.5
−
1.32
3
V
n
n
(Note 3)
VDDC output level adjust-
ment
VDDC
2.5
mV
STEP
Regulator PSRR
Load current
Load regulation
Line regulation
VDDM
VDDC
1 kHz, VBAT=1.25 V
Delivered by LDO
25
−
30
−
−
5
dB
mA
PSRR
I
LOAD
LOAD
−
5
10
12
mV/mA
mV/V
REG
REG
LINE
−
6
Memory supply output volt-
age trimming range
VDDM
Control register configured,
typical values, unloaded
0.82
1.5
−
1.32
3
V
n
n
(Note 4)
VDDM output level adjust-
ment
VDDM
2.5
mV
STEP
Regulator PSRR
Load current
VDDM
1 kHz, VBAT=1.25 V
Delivered by LDO
25
−
30
−
−
5
dB
mA
PSRR
I
LOAD
Load regulation
LOAD
−
5
10
12
mV/mA
mV/V
REG
REG
Line regulation
LINE
−
6
POWER−ON−RESET
POR startup voltage
POR shutdown voltage
VBAT
−
−
0.9
−
−
V
V
n (Note 5)
n (Note 6)
STARTUP
VBAT
0.88
SHUTDOWN
INPUT STAGE
Analog input voltage range
Preamplifier gain
V
0
0
−
−
2
V
IN
PAG
3 dB steps
36
dB
dB
kW
n
n
n
Preamplifier gain accuracy
Input impedance
PAG acc
1 kHz, PAG from 0 to 36 dB
Non−0dB preamplifier gains
−1.5
370
0
1.5
725
R
500
IN
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4
EZAIRO 7150 SL HYBRID
Table 2. ELECTRICAL SPECIFICATIONS
Description
INPUT STAGE
Symbol
Conditions
Min
Typ
Max
Units
Screened
Input referred noise
IN
IRN
AIR connected to AGND
mVrms
Unweighted, 100 Hz to
10 kHz BW
Preamplifier settings:
0 dB
53
13
−
−
12 dB
15 dB
9
−
18 dB
6.6
4.9
4.3
3.7
3.2
3.2
3.2
10.6
−
n
21 dB
24 dB
−
27 dB
−
30 dB
−
33 dB
−
36 dB
−
Input Dynamic Range
(Note 7)
IN
DR
AIR connected to AGND
dB
Unweighted, 100 Hz to 10
kHz BW
Preamplifier settings:
0 dB
−
−
86
86
86
86
85
82
82
80
77
74
−
12 dB
15 dB
−
18 dB
81
−
n
21 dB
24 dB
−
27 dB
−
30 dB
−
33 dB
−
36 dB
−
Input peak THD+N
IN
THD+N
Any preamplifier gain
−
−68
dB
n
−10 dBFS signal at preamp
output, 1kHz.
OUTPUT DRIVER
Maximum peak current
Output impedance
Output impedance
Output dynamic range
Output THD+N
I
High Power mode
−
−
−
4.5
2.5
−
25
5.5
4
mA
W
DO
R
R
Normal mode, Iload = 1 mA
High Power mode
DO
DO
−
W
DO
Normal mode, VBAT=1.25V
90
−
−
dB
dB
DR
DO
At 1 kHz, −6 dBFS, 8 kHz
bandwidth, VBAT=1.25V,
normal mode
−78
−76
THDN
10−BIT LOW−SPEED A/D
Input voltage range
INL
LSAD
LSAD
Peak input voltage
0
−4
−2
−
−
−
1.94
+4
+2
−
V
n
RANGE
LSAD
From GND to 2*VREG
From GND to 2*VREG
All channels sequentially
LSB
LSB
kHz
kHz
INL
DNL
−
DNL
Sampling frequency
LSAD
12.8
1.6
SF
Channel sampling frequency LSAD
−
−
CH_SF
SIGNAL DETECTION UNIT
Preamplifier gain
SDU
3 dB steps
0
−
36
dB
n
PAG
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EZAIRO 7150 SL HYBRID
Table 2. ELECTRICAL SPECIFICATIONS
Description
SIGNAL DETECTION UNIT
Equivalent IRN
Symbol
Conditions
Min
Typ
Max
Units
Screened
SDU
Non−weighted, 30 dB gain,
100 Hz − 10 kHz
−
−
20
mVrms
n
n
IRN
Input impedance
SDU
370
500
50
725
kOhm
kHz
V
R
Low Pass Filter Bandwidth
ADC input signal range
ADC resolution
SDU
LPF
SDU
Referred to VREG
−1
1
+1
64
RANGE
SDU
12
bits
kHz
RES
ADC sampling frequency
DIGITAL
SDU
At slow_clock = 1.28 MHz
SF
Voltage level for high input
V
IH
VDD
O*0.8
−
−
V
n
Voltage level for low input
Voltage level for high output
V
−
−
−
VDDO*0.2
V
V
n
n
IL
V
OH
2 mA source current
2 mA sink current
VDD
O*0.8
Voltage level for low output
V
OL
−
−
−
VDDO*0.2
+1
V
n
n
Oscillator frequency trim-
ming precision
SYS_CLK
SYS_CLK
SYS_CLK
−1
%
Oscillator frequency stabili-
ty over temperature
Over temperature range of
0 to 50°C
−1.5
1.28
−
−
−
−
−
+1.5
15.36
400
%
MHz
ps
Recommended working
frequency
For recommended VDDC
and VDDM
Oscillator period jitter
RMS at System clock: 1.28
MHz, before multiplication
PLL lock time
For an input phase error
<2%, input reference clock
of 128 kHz, output clock of
2.56MHz
−
10
ms
n
PLL tracking range
LOW DELAY PATH
Group Delay
−2
−
−
2
−
%
Using the low delay path of
the Filter Engine
44
ms
EEPROM
EEPROM burn cycles
Per EA2M datasheet
1’000
000
−
−
Cycles
mA
Current consumption –
writing to EEPROM
I
0.7
0.4
W
Current consumption –
read from EEPROM
I
mA
R
RADIO ANTENNA MATCHING NETWORK
Optimum differential im-
pedance at 2.4 Ghz seen
into the matching network
from pin ANT1 and ANT2
ZANT1,
ANT2
−
12.6 +
j106
−
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Recommended VDDC values depend on the system clock (SYS_CLK) frequency. Table 3 gives the recommended VDDC values for different
system clocks.
4. The minimum VDDM value required for proper system functioning is 0.90V
5. Pass fail test with 0.855 V and 0.945 V
6. Pass fail test with 0.835 V and 0.925 V
7. The audio performance might be slightly impacted when the nRF51822 radio is turned on. Degradation depends on the duty cycle of the
communication, on the external components,...
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6
EZAIRO 7150 SL HYBRID
Table 3. RECOMMENDED MINIMUM VDDC LEVEL
Operating Frequency (MHz)
1.28 to 5.12
Minimum VDDC Voltage (V)
0.73
5.13 to 10.24
0.82 (Note 8)
0.85
10.25 to 12.8
12.81 to 15.36
0.88 (Note 9)
8. The default VDDC calibration entry, stored in the manufacturing area of the EEPROM at address 0x0064, should be used for operation at
0.82V.
9. An alternate VDDC calibration entry, stored in the manufacturing area of the EEPROM at address 0x00E8, should be used for operation at
0.88V.
Packaging and Manufacturing
• Ultra−Miniature Form Factor: suitable for all hearing
aid styles including CIC, ITE, RITE, BTE, and
mini−BTE.
• RoHS compliant: the Ezairo 7150 SL hybrid complies
with the RoHS directive.
• Reflowable: the Ezairo 7150 SL hybrid is reflowable
onto FR4 and other substrates.
System Diagram
Figure 1 is a simplified diagram of the hybrid system that shows the major internal functional blocks and possible external
peripherals.
Figure 1. Ezairo 7150 SL Hybrid System Diagram
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EZAIRO 7150 SL HYBRID
Ezairo 7150 SL Hybrid Interface Specifications
A total of 49 pads are present on the Ezairo 7150 SL hybrid. These pads are the interfaces between the hybrid and the other
components in the hearing aid. They are listed in Table 4 along with the internal connections.
Table 4. PAD DESCRIPTION
Ball Number
A1
Hybrid Pad Name
DGND
Hybrid Pad Descritpion
Digital ground
A2
HGND
Output Driver Ground
Charge pump capacitor 0
A3
CAP0
A4
RCVR0N
RCVR1N
DIO24
Output Driver: Receiver Output 0 Negative
Output Driver: Receiver Output 1 Negative
Digital Input Output 24
A5
A6
A7
DIO23
Digital Input Output 23
A8
SDA
Debug Port Data
A9
SCL
Debug Port Clock
B1
VBAT
Power Supply
B2
RCVRBAT
CAP1
Output Stage Power Supply
Charge pump capacitor 1
B3
B4
RCVR0P
RCVR1P
DIO29
Output Driver: Receiver Output 0 Positive
Output Driver: Receiver Output 1 Positive
Digital Input Output 29
B5
B6
B7
DIO22
Digital Input Output 22
B8
DIO21
Digital Input Output 21
B9
VDDO3
VDDO2
VREG
IO Power Supply for DIO20 to DIO29
IO Power Supply for DIO10 to DIO19
Regulated voltage output
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
AGND
Analog Ground
DIO5
Digital Input Output 5
DIO9
Digital Input Output 9
VDBL
Regulated doubled voltage output
nRF51822: chip reset (active low) / hardware debug and flash programming I/O.
External clock input / Internal
Digital Input Output 20
RF_SWDIO
EXTCLK
DIO20
RF_SWDCLK
RF_VDD
AI3
nRF51822: Hardware debug and flash programming I/O.
nRF51822: Power supply.
Analog Input 3: Direct Analog Input
Analog Input 1: Microphone or Telecoil Input
Input Transducer Ground
AI1
GND_MIC
DIO8
Digital Input Output 8
RFGND
RFGND
RFGND
RFGND
RFGND
RF_AVDD
AI2
RF Ground
RF Ground
RF Ground
RF Ground
RF Ground
nRF51822: Analog power supply (Radio).
Analog Input 2: Microphone or Telecoil Input
Analog Input 0: Microphone or Telecoil Input
Regulated voltage for microphone
Digital Input Output 6
E2
AI0
E3
VMIC
E4
DIO6
E5
RFGND
ANT1
RF Ground
E6
nRF51822: Differential antenna connection (TX and RX).
nRF51822: Differential antenna connection (TX and RX).
RF Ground
E7
ANT2
E8
RFGND
VDDPA
RFGND
E9
nRF51822: Power supply output (+1.6 V) for on−chip RF power amp.
RF Ground
E10
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EZAIRO 7150 SL HYBRID
Figure 2. Ezairo 7150 SL Hybrid Schematics
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9
EZAIRO 7150 SL HYBRID
Figure 3. Ezairo 7150 SL Hybrid Schematics
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EZAIRO 7150 SL HYBRID
Connection Diagram
The following connections are typical when Ezairo 7150 SL is used in a hearing aid application. For details on the connections
required by the preconfigured firmware bundle refer to AND9651/D.
Figure 4. Connection Diagram
NOTE: For the purposes of wireless certification, it is recommended that the following signals are accessible or brought out
to solderable test points: VBAT, GND, VDBL, DIO6, DIO8.
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11
EZAIRO 7150 SL HYBRID
EZAIRO 7100 ARCHITECTURE OVERVIEW
The Ezairo 7100 system is an asymmetric quad−core
• Directional processing
• Feedback cancellation
• Noise reduction
To execute these and other algorithms efficiently, the HEAR
excels at the following:
architecture, mixed−signal system−on−chip designed
specifically for audio processing. It centers around four
processing cores: the CFX Digital Signal Processor (DSP),
the HEAR Configurable Accelerator, the ARM Cortex−M3
Processor Subsystem, and the Filter Engine.
• Processing using a weighted overlap add (WOLA)
filterbank
CFX DSP Core
The CFX DSP core is used to configure the system and the
other cores, and it coordinates the flow of signal data
progressing through the system. The CFX DSP can also be
used for custom signal processing applications that can’t be
handled by the HEAR or the Filter Engine.
The CFX DSP is a user−programmable general−purpose
DSP core that uses a 24−bit fixed−point, dual−MAC,
dual−Harvard architecture. It is able to perform two MACs,
two memory operations and two pointer updates per cycle,
making it well−suited to computationally intensive
algorithms.
• Time domain filtering
• Subband filtering
• Attack/release filtering
• Vector addition/subtraction/multiplication
• Signal statistics (such as average, variance and
correlation)
ARM Cortex−M3 Processor Subsystem
The ARM Cortex−M3 Processor Subsystem provides
support for data transfer to and from the wireless transceiver.
The subsystem includes hardwired CODECS (G.722,
CVSD), Error Correction support (Reed−Solomon,
The CFX features:
• Dual−MAC 24−bit load−store DSP core
• Four 56−bit accumulators
• Four 24−bit input registers
2
Hamming), interfaces (SPI, I C, PCM, GPIOs), as well as an
open−programmable ARM Cortex−M3 processor.
ARM Cortex−M3 Processor
• Support for hardware loops nested up to four deep
• Combined XY memory space (48 bits wide)
• Dual address generator units
The ARM Cortex−M3 processor is a low−power
processor that features low gate count, low interrupt latency,
and low−cost debugging. It is intended for deeply embedded
applications that require fast interrupt response features.
GNU tools provide build and link support C programs that
run on the ARM Cortex−M3 processor.
• A wide range of addressing modes:
♦ Direct
♦ Indirect with post−modification
♦ Modulo addressing
♦ Bit reverse
Filter Engine
The Filter Engine is a core that provides low−delay path
and basic filtering capabilities for the Ezairo 7100 system.
The Filter Engine can implement filters (either FIR or IIR)
with a total of up to 160 coefficients. FIR filters are
implemented using a direct−form structure. IIR filters are
implemented with a cascade of second−order sections
(biquads), each implemented as a direct−form I filter.
The Filter Engine is programmable, but does not include
direct debugging access. The CFX can monitor the Filter
Engine state through control and configuration registers on
the program memory bus.
For further information on the usage of the CFX DSP,
please refer to the Hardware Reference Manual and to the
CFX DSP Architecture Manual, available in the Ezairo 7100
Evaluation and Development Kit (EDK).
HEAR Configurable Accelerator
The HEAR coprocessor is designed to perform both
common signal processing operations and complex standard
filterbanks such as the WOLA filterbank, reducing the load
on the CFX DSP core.
The HEAR Configurable Accelerator is a highly
optimized signal processing engine that is configured
through the CFX. It offers high speed, high flexibility and
high performance, while maintaining low power
consumption. For added computing precision, the HEAR
supports block floating point processing. Configuration of
the HEAR is performed using the HEAR configuration tool
(HCT). For further information on the usage of the HEAR,
please refer to the HEAR Configurable Accelerator
Reference Manual, available in the Ezairo 7100 EDK.
The HEAR is optimized for advanced hearing aid
algorithms including but not limited to the following:
Digital Input/Output (DIO) Pads
A total of 10 DIOs are available on the Ezairo 7150 SL
hybrid. These pads can all be configured for a variety of
digital input and output modes or as LSADs. The user can
configure DIOs signal to be, for example:
• CFX PCM interface
• CFX UART interface
• CFX SPI interface
• LSAD input
• GPIOs data for the CFX
• Dynamic range compression
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12
EZAIRO 7150 SL HYBRID
2
CFX Debug Port I C
• ARM Cortex−M3 processor PCM interface
• ARM Cortex−M3 processor SPI interface
2
The CFX debug port I C interface is a hardware debugger
for the Ezairo 7100 system that is always enabled regardless
of the configuration of the general−purpose I C interface.
The debug port implements the debug port protocol
command set and is tightly coupled with the CFX DSP and
the memory components attached to the CFX. The default
address is 0x60.
2
• ARM Cortex−M3 processor I C interface
2
• ARM Cortex−M3 processor GPIOs
More details on the Ezairo 7150 SL external interfaces can
be found in the Ezairo 7100 Hardware Reference Manual,
available in the Ezairo 7100 EDK.
The 10 DIOs are split into two power domains as follow:
2
ARM Cortex−M3 Debug Port I C
2
• DIO5, DIO6, DIO8 and DIO9 are at the VDBL voltage.
The ARM Cortex−M3 debug port I C interface is a
hardware debugger for the Ezairo 7100 system that is always
enabled regardless of the configuration of the
• DIO20, DIO21. DIO22, DIO23, DIO24 and DIO29 are
at a IO supply defined by VDDO3
2
general−purpose I C interface. The debug port implements
The SDA and SCL pads are on the VDDO3 power domain.
an ARM Cortex−M3 processor debug port protocol
command set that is tightly coupled with the ARM
Cortex−M3 processor and the memory components attached
to this core. The default address is 0x40.
Debug Ports
2
2
The CFX’s I C interfaces share the same I C bus within
the Ezairo 7100 chip with two other I C interfaces:
2
Default Firmware Image on Ezairo 7150 SL
Pre Suite Firmware Bundle
Mode. Refer to the Communication Protocols Manual for
Ezairo 7100 for more information.
The default firmware image loaded in the EEPROM of
Ezairo 7150 SL comprises a realtime framework and suite
of advanced sound processing algorithms ideal for
high−end, full featured hearing aids (available under NDA).
For additional details about the Pre Suite firmware bundle
for Ezairo 7150 SL refer to AND9651/D.
The default application leaves the debug port of Ezairo
7150 SL in Restricted Mode. It is possible to erase the
default application and replace it with your own firmware
image provided you first use the Jump ROM functions
”Wipe” and ”Unlock” to place the device in Unrestricted
Conditions
SYS_CLK = 10.24 MHz
Firmware: Simple FIFO copy application
Gain normalized to 0 dB at 1 kHz
Measurements taken electrically with a two−pole RC filter
on the output with a cutoff frequency (−3 dB point) of 8 kHz.
From 2 kHz to 8 kHz, the roll−off is due to the RC filter.
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13
EZAIRO 7150 SL HYBRID
Frequency Response Graph
Figure 5. Frequency Response Graph
Solder Information
Chip Identification
System identification is used to identify different system
components. This information can be retrieved using the
Promirat Serial Platform from TotalPhase, Inc. or the
Communications Accelerator Adaptor (CAA) with the
protocol software provided by ON Semiconductor. For the
Ezairo 7100 chip, the key identifier components and values
are as follows:
• Chip Family: 0x06
• Chip Version:0x01
• Chip Revision: 0x0200
The Ezairo 7150 SL hybrid is constructed with all RoHS
compliant material and should therefore be reflowed
accordingly. The bump metallization is SAC305 (Sn96.5/
Ag3.0/Cu0.5).
This hybrid device is Moisture Sensitive Class MSL4 and
must be stored and handled accordingly. Re−flow according
to IPC/JEDEC standard J−STD−020C, Joint Industry
Standard: Moisture/Re−flow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices. The
typical re−flow profile is shown in Figure 6.
For soldering guidelines, please refer to the Soldering and
Mounting Techniques Reference Manual (SOLDERRM/D).
The hybrid ID can be found in the manufacturing area of the
EEPROM at address 0x00F1 to 0x00F2 (2 bytes => 16 bits)
• Hybrid ID: 0x0321
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14
EZAIRO 7150 SL HYBRID
Figure 6. Typical Reflow Profile
Tape & Reel Information
Package Orientation on Tape Dimensions
Hybrid orientation in pocket is pad side down and pin 1 in upper left corner.
Figure 7. Package Orientation
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15
EZAIRO 7150 SL HYBRID
Electrostatic Discharge (ESD) Device
Reference Design
A reference design of a wireless−enabled hearing aid
based on Ezairo 7150 SL is available. It includes source
code, design files and schematic layouts of the hearing aid
as well as a remote dongle that can be used for stereo audio
streaming. A provided sample Android phone application
demonstrates Control over BLE (CoBLE) functionality. The
reference design package is included with the purchase of
the Ezairo 7150 SL hybrid demonstrator board
(0W705001GEVK).
CAUTION: ESD sensitive device. Permanent damage may
occur on devices subjected to high−energy electrostatic
discharges. Proper ESD precautions in handling, packaging
and testing are recommended to avoid performance
degradation or loss of functionality.
Development Tools
A full suite of comprehensive tools is available to assist
software developers from the initial concept and technology
assessment through to prototyping and product launch. For
more information on available development tools, contact
your local sales representative or authorized distributor.
Company or Product Inquiries
For more information about ON Semiconductor products
or services visit our web site at http://onsemi.com.
Technical Contact Information
dsp.support@onsemi.com
EZAIRO is a registered trademark of Semiconductor Components Industries, LLC. NOAHlink is a trademark of HIMSA A/S.
Bluetooth is a registered trademark of Bluetooth SIG, Inc. Arm and Cortex are registered trademarks of Arm Limited.
Promira is a trademark of Total Phase, Inc.
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16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP49 3.94x7.39
CASE 127DQ
ISSUE O
DATE 30 APR 2015
SCALE 2:1
NOTES:
E
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b IS MEASURED AT THE
MAXIMUM BALL DIAMETER PARALLEL TO
DATUM C.
4. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
PIN A1
INDICATOR
5. DATUM C, THE SEATING PLANE, IS DEFINED
BY THE SPHERICAL CROWNS OF SOLDER
BALLS.
TOP VIEW
MILLIMETERS
DIM
A
A1
A2
b
MIN
−−−
0.07
MAX
1.778
0.17
1.608
0.456
4.040
7.490
A2
A
0.13
0.05
C
C
−−−
0.356
3.840
7.290
D
E
e
0.686 BSC
A1
SEATING
PLANE
C
NOTE 3
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
e/2
49X
b
e
0.05
0.03
C A B
e
0.686
PITCH
A
B
C
D
E
49X
0.410
C
NOTE 3
A1
0.686
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1
2
3
4
5
6
7
8
9 10
BOTTOM VIEW
98AON94173F
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
DESCRIPTION: SIP49 3.94X7.39
PAGE 1 OF2
DOCUMENT NUMBER:
98AON94173F
PAGE 2 OF 2
ISSUE
REVISION
DATE
30 APR 2015
O
RELEASED FOR PRODUCTION. REQ. BY J. STEFFLER.
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© Semiconductor Components Industries, LLC, 2015
Case Outline Number:
April, 2015 − Rev. O
127DQ
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