E7160-0-102A57-BPG_技术文档

DATA SHEET

www.onsemi.com

Wireless-Enabled Audio

Processor for Hearing Aids

EZAIRO 7160 SL HYBRID

SIP57

CASE 127EX

Introduction

®

Ezairo 7160 SL is an open−programmable DSP−based hybrid

specifically designed for wireless, high−performance hearing aids.

The Ezairo 7160 SL hybrid is based on the Ezairo 7100

System−on−Chip (SoC) and includes RSL10− the industry’s lowest

MARKING DIAGRAM

for OPN E7160−0−102A57−AG

®

power Bluetooth 5 radio SoC, EA2M a 2 Mb EEPROM, and all

E7160−0

ZZZZZZ

NNNNN

necessary passive components for interfacing with transducers.

Ezairo 7100 features a high precision quad−core architecture that

delivers 375 MIPS without sacrificing power consumption. The

dual−Harvard CFX Digital Signal Processor (DSP) core is optimized

to run advanced hearing aid algorithms, while the HEAR Configurable

Accelerator engine performs many different types of audio processing.

(Top View)

for OPN E7160−0P−102A57−AG

®

Complementing the DSP core, the Arm Cortex −M3 processor

supports wireless protocols and combines an open−programmable

controller with hardware accelerators for audio coding and error

correction support. Ezairo 7100 also includes a programmable Filter

Engine that enables time domain filtering and supports an

ultra−low−delay audio path.

E7160−0P

ZZZZZZ

NNNNN

(Top View)

E7160−0 / E7160−0P = Specific Device Code

Offering the industry’s lowest power consumption in deep sleep and

peak receiving, RSL10 is a highly flexible multi−protocol 2.4 GHz

radio specifically designed for use in high−performance wearable and

medical applications. With its Arm Cortex−M3 processor and

LPDSP32 DSP core, RSL10 supports Bluetooth low energy

technology and 2.4 GHz proprietary protocols.

ZZZZZZ

NNNNN

= Assembly Lot Code

= Serial Number

ORDERING INFORMATION

†

Device

Package

Shipping

E7160−0−102A57−AG

(RoHS Compliant)

SIP57

250 /

Development Tools

Ezairo Preconfigured Suite (Pre Suite)*

(Pb−Free) Tape & Reel

The Ezairo Pre Suite provides a complete framework to easily

develop Ezairo−based hearing aids and fitting software. Included in

the Ezairo Pre Suite is a firmware bundle, configuration software, and

a cross−platform Software Development Kit (SDK) to develop your

own fitting software.

E7160−0P−102A57−AG

(RoHS Compliant)*

SIP57 250 /

(Pb−Free) Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

RSL10 Development Tools

*Includes support for special audio protocol. Please

contact your onsemi representative for more

information

The RSL10 development tools provide an Eclipse−based SDK

complete with Bluetooth profiles and wireless audio codecs for the

RSL10’s Arm Cortex−M3 processor. The RSL10’s LPDSP32 code

can be developed using the Synopsys development tools which are

available by request.

Open−Programmable Evaluation and Development Kit (EDK)

To develop your own firmware on Ezairo 7160 SL, the Ezairo 7100

Evaluation and Development Kit (EDK) includes optimized hardware,

programming interface, and a comprehensive Integrated Development

Environment (IDE).

*This datasheet describes all features of the Ezairo 7160 SL hybrid module. Not

all of these features are available using the Ezairo Preconfigured Suite.

1

Publication Order Number:

May, 2023 − Rev. 12

E7160/D

EZAIRO 7160 SL HYBRID

KEY FEATURES

• Programmable Flexibility: The open−programmable

• Ultra−high Fidelity: 85 dB system dynamic range with

up to 110 dB input signal dynamic range,

exceptionally−low system noise and low group delay.

DSP−based system can be customized to the specific

signal processing needs of manufacturers. Algorithms

and features can be modified or completely new concepts

implemented without having to modify the chip.

• Ultra−low Power Consumption: < 0.7 mA

@

10.24 MHz system clock (executing a tight MAC−loop in

the CFX DSP core plus a typical hearing aid filterbank on

the HEAR Configurable Accelerator).

• Fully Integrated Hybrid: Includes the Ezairo 7100 SoC,

RSL10 radio SoC, 2 Mb of EEPROM memory, and the

necessary passive components to directly interface with

the transducers required in a hearing aid.

• Fitting Support: Support for Microcard, HI−PRO 2,

HI−PRO USB, QuickCom, and NOAHlinkt, including

NOAHlink’s audio streaming feature.

• Data Security: Sensitive program data can be encrypted

for storage in EEPROM to prevent unauthorized parties

from gaining access to proprietary algorithm intellectual

property.

2

• High Speed Communication Interface: Fast I C−based

• These devices are Pb−Free, Halogen Free/BFR Free and

interface for quick download, debugging and general

communication.

are RoHS Compliant

• Highly Configurable Interfaces: Two PCM interfaces,

Ezairo 7100 DSP Main Features:

2

two I C interfaces, two SPI interfaces, a UART interface

• Quad−core Architecture: Includes a CFX DSP, a HEAR

Configurable Accelerator, an Arm Cortex−M3 Processor

Subsystem and a programmable Filter Engine. The

system also includes an efficient input/output controller

(IOC), system memories, input and output stages along

with a full complement of peripherals and interfaces.

• CFX DSP: A highly cycle−efficient, programmable core

that uses a 24−bit fixed−point, dual−MAC, dual−Harvard

architecture.

as well as multiple GPIOs can be used to stream

configuration, control or signal data into and out of the

Ezairo 7160 SL hybrid.

RSL10 Main Features:

• Arm Cortex−M3 Processor: A 32−bit core for real−time

applications, specifically developed to enable

high−performance low−cost platforms for a broad range

of low−power applications.

• HEAR Configurable Accelerator: An optimized signal

processing engine designed to perform common signal

processing operations and complex standard filterbanks.

• Arm Cortex−M3 Processor Subsystem: A complete

subsystem that supports efficient data transfer to and from

the wireless transceiver or multiple transceivers.

• Programmable Filter Engine: A filtering system that

allows applying a various range of pre− or post−

processing filtering, such as IIR, FIR and biquad filters.

• LPDSP32: A 32−bit Dual Harvard DSP core that

efficiently supports audio codecs required for wireless

audio communication. Various codecs are available to

customers through libraries that are included in RSL10’s

development tools.

• Radio Frequency Front−End: Based on a 2.4 GHz RF

transceiver, the RFFE implements the physical layer of

the Bluetooth low energy technology standard and other

proprietary or custom protocols.

• Protocol Baseband Hardware: Bluetooth 5 certified

and includes support for a 2 Mbps RF link and custom

protocol options. The RSL10 baseband stack is

supplemented by support structures that enable

implementation of onsemi and customer designed

custom protocols.

• Configurable System Clock Speeds: 1.28 MHz,

1.92 MHz, 2.56 MHz, 3.84 MHz, 5.12 MHz, 6.4 MHz,

7.68 MHz, 8.96 MHz, 9.60 MHz, 10.24 MHz (default

clock calibration), 12.80 MHz and 15.36 MHz to

optimize the computing performance versus power

consumption ratio. The calibration entries for these

12 clock speeds are stored in the manufacturing area of

the EEPROM.

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2

EZAIRO 7160 SL HYBRID

Table 1. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

Unit

V

VBAT

Power supply voltage

2

RCVRBAT

Output drivers power supply voltage

I/O supply voltage

2

V

VDDO

Vin

3.3 (Note 1)

V

2

Voltage at any input pin

GNDC−0.3

VDDO + 0.3

V

DGND, AGND, HGND

T functional

Digital and Analog Grounds

Functional temperature range (Note 2)

Operational temperature range (Note 2)

Storage temperature range

0

−

V

−40

0

85

50

85

°C

T operational

T storage

−40

Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. In some applications, VDDO can be higher than 2.1 V (maximum 3.3 V). In such cases, the user must set the VDDM voltage at a minimum

of 1.1 V.

2. Electrical Specification may exceed listed tolerances when out of the temperature range 0 to 50°C.

ELECTRICAL PERFORMANCE SPECIFICATIONS

The tests were performed at 20°C with a 1.25 V supply voltage and 4.7 W series resistor to simulate a nominal hearing aid

battery. The system clock (SYS_CLK) was set to 5.12 MHz and an audio input sampling frequency of 16 kHz was used.

Parameters marked as screened are tested on each chip.

Table 2. ELECTRICAL SPECIFICATIONS

Description

OVERALL

Symbol

Conditions

Min

Typ

Max

Unit

Screened

Supply Voltage

VBAT

Supply voltage measured at the

VBAT pin

1.18

(Note

3, 4)

1.25

2.0

V

I/O Supply Voltage

Domain 2

VDDO

1.05

−

3.3

V

2

3. In order to be able to use a VBAT Min of 1.1 V, the following reduced operating conditions for the RSL10 should be observed:

− Maximum Tx power 0 dBm

− SYSCLK ≤ 24 MHz

− Functional temperature range limited to 0−50°C

The following trimming parameters should be used:

− VCC = 1.10 V

− VDDC = 0.92 V

− VDDM = 1.05 V, will be limited by VCC at end of battery life

− VDDRF = 1.05 V, will be limited by VCC at end of battery life. VDDPA should be disabled

RSL10 should enter in end−of−battery−life operating mode if VCC falls below 1.03 V. VCC will remain above 1.03 V if VBAT ≥ 1.10 V under

the restricted operating conditions described above.

4. Min VBAT = 1.05 V if RSL10 is disabled.

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3

EZAIRO 7160 SL HYBRID

Table 2. ELECTRICAL SPECIFICATIONS (continued)

Description

OVERALL

Symbol

Conditions

Min

Typ

Max

Unit

Screened

Current consumption

I

Filterbank: 30% load CFX: 100%

load SYS_CLK: 10.24 MHz,

No activity on the RSL10

−

700

−

mA

VBAT

Pre Suite FW running at 15.36 MHz.

Algorithms enabled: SG (dynamic),

EQ, WDRC, NR, FBC (with Gain

Management).

−

1.31

−

mA

No transducers connected.

RSL10 in sleep mode.

Pre Suite FW running at 15.36 MHz.

Algorithms enabled: SG (dynamic),

EQ, WDRC, NR, FBC (with Gain

Management).

−

2.18

−

mA

No transducers connected.

RSL10 enabled with BLE connection

between the Ezairo 7160 SL and

a phone or a dongle.

Pre Suite FW running at 15.36 MHz.

Algorithms enabled: SG (dynamic),

EQ, WDRC, NR, FBC (with Gain

Management).

−

2.81

−

mA

No transducers connected.

RSL10 in RX streaming audio mode

using the onsemi proprietary audio

streaming protocol

Stand by current

I

stb

Using onsemi’s macro

40

120

mA

VREG

Regulated voltage

output

VREG

I

= 100 mA

0.96

0.97

0.98

V

n

load

Regulator PSRR

Load current

Load regulation

Line regulation

VDDA

1 kHz, VBAT = 1.25 V

76

−

80

−

2

dB

mA

PSRR

LOAD

I

LOAD

5 mA < Iload < 2 mA

−

4

10

5

mV/mA

mV/V

REG

LINE

Iload = 1 mA

−

2

REG

Output voltage

trimming range

VDDA

Control register configured, typical

values

1.8

2.0

2.1

V

n

Regulator PSRR

Load current

VDDA

1 kHz, VBAT = 1.25 V

40

−

50

−

1

dB

mA

PSRR

I

LOAD

Load regulation

LOAD

VBAT = 1.2 V;

100 mA < Iload < 1 mA

−

4

10

mV/mA

REG

Line regulation

LINE

1.2 V < VBAT < 1.86 V;

Iload = 100 mA

−

6

20

mV/V

REG

VDBL

Output voltage

trimming range

VDBL

Control register configured, typical

values, unloaded

1.6

2.0

2.2

V

n

Regulator PSRR

Load current

VDBL

1 kHz, VBAT=1.25 V

30

−

40

−

dB

mA

PSRR

I

ITRIM (A_CP_VDBL_CTRL) = 0x7

15

10

LOAD

Load regulation

LOAD

VBAT = 1.2 V;

100 mA < Iload < 3 mA

−

4

mV/mA

REG

Line regulation

LINE

VBAT > 1.2 V; Iload = 100 mA

−

6

20

mV/V

REG

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4

EZAIRO 7160 SL HYBRID

Table 2. ELECTRICAL SPECIFICATIONS (continued)

Description

VDDC

Symbol

Conditions

Min

Typ

Max

Unit

Screened

Digital supply output

voltage trimming

range

VDDC

Control register configured, typical

values, unloaded

0.72

−

1.32

V

n

(Note 5)

VDDC output level

adjustment

VDDC

1.5

2.5

3

mV

n

STEP

Regulator PSRR

Load current

Load regulation

Line regulation

VDDM

1 kHz, VBAT = 1.25 V

Delivered by LDO

25

−

30

−

5

dB

mA

PSRR

I

LOAD

−

5

10

12

mV/mA

mV/V

REG

LINE

−

6

REG

Memory supply

output voltage

trimming range

VDDM

Control register configured, typical

values, unloaded

0.82

1.5

−

1.32

3

V

n

(Note 6)

VDDM output level

adjustment

VDDM

2.5

mV

STEP

Regulator PSRR

Load current

VDDM

1 kHz, VBAT = 1.25 V

Delivered by LDO

25

−

30

−

5

dB

mA

PSRR

I

LOAD

Load regulation

Line regulation

LOAD

−

5

10

12

mV/mA

mV/V

REG

LINE

−

6

POWER−ON−RESET (triggered from the RSL10 value)

POR voltage

VBAT

−

1.0

2

V

POR

INPUT STAGE

Analog input voltage

range

V

IN

0

Preamplifier gain

PAG

3 dB steps

0

−

36

dB

n

Preamplifier gain

accuracy

PAG acc

1 kHz, PAG from 0 to 36 dB

−1.5

0

1.5

Input impedance

R

Non−0dB preamplifier gains

370

500

725

kW

n

IN

Input referred noise

IN

IRN

AIR connected to AGND

mVrms

Unweighted, 100 Hz to

10 kHz BW

Preamplifier settings:

0 dB

−

53

13

−

12 dB

15 dB

9

−

18 dB

6.6

4.9

4.3

3.7

3.2

10.6

−

n

21 dB

24 dB

−

27 dB

−

30 dB

−

33 dB

−

36 dB

−

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5

EZAIRO 7160 SL HYBRID

Table 2. ELECTRICAL SPECIFICATIONS (continued)

Description

Symbol

Conditions

Min

Typ

Max

Unit

Screened

INPUT STAGE

Input Dynamic Range

(Note 7)

IN

DR

AIR connected to AGND

Unweighted, 100 Hz to

10 kHz BW

dB

Preamplifier settings:

0 dB

−

86

85

82

80

77

74

−

12 dB

15 dB

−

18 dB

81

−

n

21 dB

−

24 dB

−

27 dB

−

30 dB

−

33 dB

−

36 dB

−

Input peak THD+N

OUTPUT DRIVER

IN

Gain between 0 and 30 dB,

−10 dBFS signal, 1 kHz

−

−68

dB

n

THD+N

IN

THD+N

Gain between 33 and 36 dB,

−10 dBFS signal, 1 kHz.

−

−66

Maximum peak

current

I

High Power mode

−

25

mA

DO

Output impedance

Output dynamic range

Output THD+N

R

Normal mode, Iload = 1 mA

High Power mode

−

4.5

2.5

−

5.5

4

W

DO

Normal mode, VBAT = 1.25 V

90

−

dB

DR

DO

At 1 kHz, −6 dBFS,

8 kHz bandwidth, VBAT = 1.25 V,

normal mode

−78

−76

THDN

10−BIT LOW−SPEED A/D

Input voltage range

LSAD

Peak input voltage

0

−4

−2

−

1.94

+4

+2

−

V

n

RANGE

INL

LSAD

From GND to 2*VREG

All channels sequentially

LSB

kHz

INL

DNL

LSAD

−

DNL

Sampling frequency

LSAD

12.8

1.6

SF

Channel sampling

frequency

LSAD

−

CH_SF

SIGNAL DETECTION UNIT

Preamplifier gain

Equivalent IRN

SDU

3 dB steps

0

−

36

20

dB

n

PAG

Non−weighted, 30 dB gain,

100 Hz − 10 kHz

−

mVrms

IRN

Input impedance

SDU

370

500

50

725

kOhm

kHz

n

R

Low Pass Filter

Bandwidth

SDU

−

LPF

ADC input signal

range

SDU

Referred to VREG

−1

−

+1

V

RANGE

ADC resolution

SDU

12

−

bits

RES

ADC sampling

frequency

SDU

At slow_clock = 1.28 MHz

1

−

64

kHz

SF

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6

EZAIRO 7160 SL HYBRID

Table 2. ELECTRICAL SPECIFICATIONS (continued)

Description Symbol Conditions

DIGITAL

Min

Typ

Max

Unit

Screened

Voltage level for high

input

V

VDDO

*0.8

−

V

n

IH

Voltage level for low

input

V

−

VDDO*0.2

IL

Voltage level for high

output

V

OH

2 mA source current

VDDO

*0.8

V

Voltage level for low

output

V

OL

2 mA sink current

−

VDDO*0.2

+1

V

Oscillator frequency

trimming precision

SYS_CLK

−1

%

Oscillator frequency

stability over

temperature

Over temperature range of 0 to 50°C

−1.5

+1.5

Recommended

SYS_CLK

For recommended VDDC and VDDM

1.28

−

15.36

400

10

MHz

ps

working frequency

Oscillator period jitter

RMS at System clock: 1.28 MHz,

before multiplication

PLL lock time

For an input phase error <2%, input

reference clock of 128 kHz, output

clock of 2.56 MHz

−

ms

n

PLL tracking range

LOW DELAY PATH

Group Delay

−2

−

2

%

Using the low delay path of the

Filter Engine

−

44

−

ms

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Recommended VDDC values depend on the system clock (SYS_CLK) frequency. Table 3 gives the recommended VDDC values for different

system clocks.

6. The minimum VDDM value required for proper system functioning is 0.90 V.

7. The audio performance might be slightly impacted when the RSL10 radio is turned on. Degradation depends on the duty cycle of the

communication, on the external components.

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7

EZAIRO 7160 SL HYBRID

Table 3. RECOMMENDED MINIMUM VDDC LEVEL

Operating Frequency (MHz)

1.28 to 5.12

Minimum VDDC Voltage (V)

0.73

5.13 to 10.24

0.82 (Note 8)

0.85

10.25 to 12.8

12.81 to 15.36

0.88 (Note 9)

8. The default VDDC calibration entry, stored in the manufacturing area of the EEPROM at address 0x0064, should be used for operation at 0.82 V.

9. An alternate VDDC calibration entry, stored in the manufacturing area of the EEPROM at address 0x00E8, should be used for operation at 0.88 V.

Table 4. EA2M ELECTRICAL SPECIFICATIONS

EEPROM burn cycles

1,000,000

−

Cycles

mA

Current consumption –

writing to EEPROM

I

W

−

0.7

Current consumption – read

from EEPROM

I

R

−

0.4

−

mA

*The electrical specifications of the EA2M EEPROM can be found in the EA2M datasheet.

Table 5. RSL10 ELECTRICAL SPECIFICATIONS

Current consumption RX

I

Rx Mode, onsemi proprietary audio

streaming protocol at 7 kHz audio BW,

37 ms delay.

−

1.15

−

mA

VBAT

Standby Mode current

I

Digital blocks and memories are not clocked

and are powered at a reduced voltage.

−

30

5.6

−94

8.9

−

mA

stb

Peak Current consumption

at 1 Mbps

IBAT

VDDRF = 1.1 V, 100% duty cycle

RFRX

Rx Sensitivity, 1 Mbps, BLE

0.1% BER, Single−ended on chip antenna

match to 50 W

dBm

mA

Tx peak power consumption

at VBAT = 1.25 V (Note 10)

IBAT

Tx power 0 dBm, VDDRF = 1.07 V,

VDDPA: off, LDO mode

RFTX

*The electrical specifications of the RSL10 radio SoC can be found in the RSL10 datasheet.

10.The Ezairo 7160 SL EVB, with a +2.2dBi SMA antenna, will not pass regulatory certification for TX power > 1 dBm

11. For Open−Programmable customers (who are not using the Pre Suite FW):

The optimal settings for the RSL10 48 MHz trim are set by inserting the following commands via the RSL10 SDK:

RF_PLL_CTRL−>XTAL_TRIM_XTAL_TRIM_BYTE = 0xCB;

RF_REG05−>BANK_BYTE = 0;

RF_REG1A−>FILTER_BIAS_IQ_FI_SHORT = ((RF_REG1A−>FILTER_BIAS_IQ_FI_SHORT &

(~RF_REG1A_FILTER_BIAS_IQ_FI_FC_Mask)) | 0x0C);

after the BLE_Initialize(); command.

PACKAGING AND MANUFACTURING

• Ultra−Miniature: Suitable for all hearing aid styles

including CIC, ITE, RITE, BTE, and mini−BTE.

• Reflowable: Ezairo 7160 SL is re−flowable onto FR4 and

other substrates.

• RoHS Compliant: Ezairo 7160 SL complies with the

RoHS directive.

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8

EZAIRO 7160 SL HYBRID

SYSTEM DIAGRAM

Figure 1 is a simplified diagram of the hybrid system that shows the major internal functional blocks and possible external

peripherals.

Figure 1. Ezairo 7160 SL Hybrid System Diagram

EZAIRO 7160 SL HYBRID INTERFACE SPECIFICATIONS

A total of 57 pads are present on the Ezairo 7160 SL hybrid. These pads are the interfaces between the hybrid and the other

components in the hearing aid. They are listed in Table 6 along with the internal connections.

Table 6. PAD DESCRIPTION

Ball Number

Hybrid Pad Name

VSSRF

VBAT

Hybrid Pad Description

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

B1

B2

B3

B4

B5

B6

B7

B8

RF analog ground

Power Supply

DGND

Digital ground for the Ezairo 7100

Reset pin for the Ezairo 7100

NRESET

DIO21

Digital Input Output 21 for the Ezairo 7100

Debug Port Clock for the Ezairo 7100

Debug Port Data for the Ezairo 7100

SCL

SDA

RCVRBAT

VSSRF

RFIO12

VDDO2

DIO9

Output Stage Power Supply for the Ezairo 7100

RF analog ground

Digital Input Output 12 for the RSL10

IO Power Supply for DIO20 to DIO29 of Ezairo 7100 and for all DIO of the RSL10

Digital Input Output 9 for the Ezairo 7100

Digital Input Output 6 for the Ezairo 7100

Digital Input Output 20 for the Ezairo 7100

Receiver Output 1 Negative for the Ezairo 7100

DIO6

DIO20

RCVR1N

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EZAIRO 7160 SL HYBRID

Table 6. PAD DESCRIPTION (continued)

Ball Number

B9

Hybrid Pad Name

RCVR0N

HGND

RF

Hybrid Pad Description

Receiver Output 0 Negative for the Ezairo 7100

Output Driver Ground for the Ezairo 7100

RF signal input/output (Antenna)

B10

C1

C3

JTCK

CM3−JTAG Test Clock for the RSL10

Regulated doubled voltage output for Ezairo 7100

Digital Input Output 8 for the Ezairo 7100

Digital Input Output 5 for the Ezairo 7100

Digital Input Output 22 for the Ezairo 7100

Receiver Output 1 Positive for the Ezairo 7100

Receiver Output 0 Positive for the Ezairo 7100

Digital Input Output 29 for the Ezairo 7100

Analog ground for the RSL10

C4

VDBL

C5

DIO8

C6

DIO5

C7

DIO22

RCVR1P

RCVR0P

DIO29

VSSA

C8

C9

C10

D1

D4

JTMS

CM3−JTAG Test Mode State for the RSL10

Reset pin for the RSL10

D5

RFNRESET

DIO4

D6

Digital Input Output 4 for the Ezairo 7100

Digital Input Output 7 for the Ezairo 7100

EXT_CLK pin for the Ezairo 7100

D7

DIO7

D8

EXTCLK

DIO23

DIO24

XTAL32KN

RES

D9

Digital Input Output 23 for the Ezairo 7100

Digital Input Output 24 for the Ezairo 7100

Xtal input pin for 32 kHz xtal

D10

E1

E2

RESERVED

E3

RFGND

AOUT

RF Ground for RSL10

E4

Analog test pin

E5

RFIO0

RFIO1

GND_MIC

VMIC

Digital Input Output 0 for the RSL10

E6

Digital Input Output 1 for the RSL10

E7

Input Transducer Ground for the Ezairo 7100

Regulated voltage for microphone for the Ezairo 7100

Analog Input 3: Direct Analog Input for the Ezairo 7100

Analog Ground for the Ezairo 7100

E8

E9

AI3

E10

F1

AGND

XTAL32KP

VDCRF

RFGND

RFIO2

VCCRF

RFIO3

AI0

Xtal output pin for 32 kHz xtal

F2

DC−DC output voltage to external LC filter for RSL10

RF Ground for RSL10

F3

F4

Digital Input Output 2 for the RSL10

F5

DC−DC filtered output for the RSL10

Digital Input Output 3 for the RSL10

F6

F7

Analog Input 0: Microphone or Telecoil Input for the Ezairo 7100

Analog Input 1: Microphone or Telecoil Input for the Ezairo 7100

Analog Input 2: Microphone or Telecoil Input for the Ezairo 7100

Regulated voltage output for the Ezairo 7100

F8

AI1

F9

AI2

F10

VREG

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10

EZAIRO 7160 SL HYBRID

Figure 2. Ezairo 7160 SL Hybrid Schematics

www.onsemi.com

11

EZAIRO 7160 SL HYBRID

Figure 3. Ezairo 7160 SL Hybrid Schematics

TOP LAYER KEEPOUT

Figure 4. Ezairo 7160 SL Keep−out Area

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12

EZAIRO 7160 SL HYBRID

CONNECTION DIAGRAM

The following connections should be observed when the Ezairo 7160 SL is used in typical hearing aid applications:

Figure 5. Connection Diagram, Bottom View, Authentication Co−processor 3.0 and HPM10 not Connected

www.onsemi.com

13

EZAIRO 7160 SL HYBRID

Figure 6. Connection Diagram, Bottom View, with the Authentication Co−processor 3.0 and HPM10

General Notes:

− onsemi recommends to use the 9HT12−32.768KDZF−T SMD crystal from TXC corporation or the WMRAG32K76CS1C00R0 MEMS

resonator from Murata.

− Harmonic filter on RF pin required to pass regulatory emission tests.

− For the purposes of BT−SIG certification, the following signals must be accessible or brought out to solderable test points: VBAT, GND, and

either RFIO2 & RFIO3 (VDDO2 = VDBL domain) or DIO24 & DIO29 (VDDO3 = VBAT domain). Please refer to AND9838/D for more details.

Please note that for the VDDO2 = VDBL domain case, a voltage of VBATx2 will need to be supplied to the Level Translator.

− The Auth 3.0 CP is connected to Ezairo 7160 SL with VDBL supply, RFIO0 & RFIO1.

− VDDO2 on Ezairo 7160 SL is moved from VBAT to VDBL.

Notes on HPM10:

− Details on caps CP1, CP2, CREG, CHA and CVBAT can be found in the HPM10 datasheet

− R1 = 3K9 ohm 1%; C1 = 0.56 mF 10%

− Details for powering the interfaces and programming of HPM10 is provided in the User and Reference Manual

Connections between Ezairo 7160 SL and MFi Authentication IC:

− Connect MFi IC power supply (VCC) to VDBL

− Connect MFi IC SCL to RFIO0 and SDA to RFIO1

− Ensure Ezairo 7160 SL VDDO2 is connected to VDBL

Connections between Ezairo 7160 SL and HPM10:

− DIO22 to DS_EN: Output from Ezairo to tell HPM10 to enter Deep Sleep mode

− WARN to DIO23: Output from HPM10 to tell Ezairo that it will be shut down in XX seconds (configurable)

− SWOUT to DIO29: Output from HPM10 to Ezairo; level−shifted SWIN signal (active high)

− VHA to VBAT: Ezairo is powered by HPM10’s VHA output

Notes on Pre Suite:

− When using Pre Suite with the MMI Detection Edge set to Falling Edge, an inverter is required

− VDDO3 on Ezairo 7160 SL is internally connected to VBAT

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14

EZAIRO 7160 SL HYBRID

EZAIRO 7100 ARCHITECTURE OVERVIEW

The Ezairo 7100 system is an asymmetric quad−core

• Directional processing

• Feedback cancellation

• Noise reduction

To execute these and other algorithms efficiently, the HEAR

excels at the following:

architecture, mixed−signal system−on−chip designed

specifically for audio processing. It centers around four

processing cores: the CFX Digital Signal Processor (DSP),

the HEAR Configurable Accelerator, the Arm Cortex−M3

Processor Subsystem, and the Filter Engine.

• Processing using a weighted overlap add (WOLA)

filterbank

CFX DSP Core

The CFX DSP core is used to configure the system and the

other cores, and it coordinates the flow of signal data

progressing through the system. The CFX DSP can also be

used for custom signal processing applications that can’t be

handled by the HEAR or the Filter Engine.

The CFX DSP is a user−programmable general−purpose

DSP core that uses a 24−bit fixed−point, dual−MAC,

dual−Harvard architecture. It is able to perform two MACs,

two memory operations and two pointer updates per cycle,

making it well−suited to computationally intensive

algorithms.

• Time domain filtering

• Subband filtering

• Attack/release filtering

• Vector addition/subtraction/multiplication

• Signal statistics (such as average, variance and

correlation)

Arm Cortex−M3 Processor Subsystem

The Arm Cortex−M3 Processor Subsystem provides

support for data transfer to and from the wireless transceiver.

The subsystem includes hardwired CODECS (G.722,

CVSD), Error Correction support (Reed−Solomon,

The CFX features:

• Dual−MAC 24−bit load−store DSP core

• Four 56−bit accumulators

• Four 24−bit input registers

2

Hamming), interfaces (SPI, I C, PCM, GPIOs), as well as an

open−programmable Arm Cortex−M3 processor.

Arm Cortex−M3 Processor

• Support for hardware loops nested up to four deep

• Combined XY memory space (48 bits wide)

• Dual address generator units

The Arm Cortex−M3 processor is a low−power processor

that features low gate count, low interrupt latency, and

low−cost debugging. It is intended for deeply embedded

applications that require fast interrupt response features.

GNU tools provide build and link support C programs that

run on the Arm Cortex−M3 processor.

• A wide range of addressing modes:

♦ Direct

♦ Indirect with post−modification

♦ Modulo addressing

♦ Bit reverse

Filter Engine

The Filter Engine is a core that provides low−delay path

and basic filtering capabilities for the Ezairo 7100 system.

The Filter Engine can implement filters (either FIR or IIR)

with a total of up to 160 coefficients. FIR filters are

implemented using a direct−form structure. IIR filters are

implemented with a cascade of second−order sections

(biquads), each implemented as a direct−form I filter.

The Filter Engine is programmable, but does not include

direct debugging access. The CFX can monitor the Filter

Engine state through control and configuration registers on

the program memory bus.

For further information on the usage of the CFX DSP,

please refer to the Hardware Reference Manual and to the

CFX DSP Architecture Manual.

HEAR Configurable Accelerator

The HEAR coprocessor is designed to perform both

common signal processing operations and complex standard

filterbanks such as the WOLA filterbank, reducing the load

on the CFX DSP core.

The HEAR Configurable Accelerator is a highly

optimized signal processing engine that is configured

through the CFX. It offers high speed, high flexibility and

high performance, while maintaining low power

consumption. For added computing precision, the HEAR

supports block floating point processing. Configuration of

the HEAR is performed using the HEAR configuration tool

(HCT). For further information on the usage of the HEAR,

please refer to the HEAR Configurable Accelerator

Reference Manual.

Ezairo 7160 SL IOs

Digital Input/Output (DIO) Pads

A total of 12 DIOs of the Ezairo 7100 are available on the

Ezairo 7160 SL hybrid. These pads can all be configured for

a variety of digital input and output modes or as LSADs. The

user can configure DIOs signal to be, for example:

• CFX PCM interface

• CFX UART interface

• CFX SPI interface

The HEAR is optimized for advanced hearing aid

algorithms including but not limited to the following:

• Dynamic range compression

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15

EZAIRO 7160 SL HYBRID

The Arm Cortex−M3 processor of the RSL10 can be

• LSAD input

debugged through the SWJ−DP which can be configured to

either serial wire or JTAG debug port communications. By

default, the SWJ−DP is accessed using the JTAG dedicated

pads (JTCK, JTMS). It is advisable to include JTAG test

points on your PCB in the event that the RSL10 should

require re−programming or debugging at the hearing aid

level (see Figure 5: Connection Diagram).

• GPIOs data for the CFX

• Arm Cortex−M3 processor PCM interface

• Arm Cortex−M3 processor SPI interface

2

• Arm Cortex−M3 processor I C interface

• Arm Cortex−M3 processor GPIOs

More details on the Ezairo 7160 SL external interfaces can

be found in the Ezairo 7100 Hardware Reference Manual.

The 12 DIOs are split into two power domains as follow:

• DIO4, DIO5, DIO6, DIO7, DIO8 and DIO9 are at the

VDBL voltage.

PRE SUITE FIRMWARE BUNDLE

The Pre Suite Firmware Bundle of Ezairo 7160 SL

comprises a real−time framework and suite of advanced

sound processing algorithms ideal for high−end, full

featured hearing aids (available under NDA). For additional

details about the Pre Suite firmware bundle for Ezairo 7160

SL refer to Ezairo 7160 SL Firmware Bundle User’s Guide.

• DIO20, DIO21. DIO22, DIO23, DIO24 and DIO29 are

at the VBAT voltage.

5 DIOs of the RSL10 are routed out of the Ezairo 7160 SL

hybrid:

DEFAULT APPLICATION ON EZAIRO 7160 SL

The default application includes functionality that allows

the applications of the Ezairo 7100 and the RSL10 to be

updated to the latest Pre Suite versions using Sound

Designer/SDK. It leaves the debug port of Ezairo 7100 in

Restricted Mode.

For customers using the Ezairo 7160 SL as an

open−programmable device, it is possible to erase the

default application and replace it with your own firmware

image for both the Ezairo 7100 and the RSL10. For the

Ezairo 7100, this can be done using the Ezairo 7100 IDE or

in a script using the Jump ROM functions “Wipe” and

“Unlock” to place the device in Unrestricted Mode. Refer to

the Communication Protocols Manual for Ezairo 7100 for

more information. For the RSL10, onsemi has developed a

utility that erases the Pre Suite application and unlocks the

RSL10. Please contact your onsemi sales representative to

access this utility.

• RFIO0, shared with DIO11 of the Ezairo 7100

• RFIO1, shared with DIO12 of the Ezairo 7100

• RFIO2, shared with DIO13 of the Ezairo 7100

• RFIO3, shared with DIO14 of the Ezairo 7100

• RFIO12

The debug port pads for the Ezairo 7100 SDA and SCL are

at the VBAT voltage.

Debug Ports

2

The CFX’s I C interfaces share the same I C bus within

2

the Ezairo 7100 chip with two other I C interfaces:

2

CFX Debug Port I C

The CFX debug port I C interface is a hardware debugger

for the Ezairo 7100 system that is always enabled regardless

of the configuration of the general−purpose I C interface.

The debug port implements the debug port protocol

command set and is tightly coupled with the CFX DSP and

the memory components attached to the CFX. The default

address is 0x60.

2

Frequency Response Graph

Conditions

2

Arm Cortex−M3 Processor Debug Port I C

The Arm Cortex−M3 debug port I C interface is a

2

SYS_CLK = 10.24 MHz

hardware debugger for the Ezairo 7100 system that is always

Firmware: Simple FIFO copy application

Gain normalized to 0 dB at 1 kHz

enabled regardless of the configuration of the general−

2

purpose I C interface. The debug port implements an Arm

Measurements taken electrically with a two−pole RC filter

on the output with a cutoff frequency (−3 dB point) of 8 kHz.

From 2 kHz to 8 kHz, the roll−off is due to the RC filter.

Cortex−M3 processor debug port protocol command set that

is tightly coupled with the Arm Cortex−M3 processor and

the memory components attached to this core. The default

address is 0x40.

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16

EZAIRO 7160 SL HYBRID

Figure 7. Frequency Response Graph

RSL10 ARCHITECTURE OVERVIEW

Information on the RSL10 architecture can be found on

the RSL10 datasheet available on www.onsemi.com

16 bits). Similar to the Ezairo 7100 information, the hybrid

ID can be retrieved using a programming interface.

• Hybrid ID: −0x03C0: for OPN E7160−0−102A57−AG

−0x13C0: for OPN E7160−0P−102A57−AG

Chip Identification

System identification is used to identify different system

components.

Solder Information

For the Ezairo 7100, this information can be retrieved

using the Promirat Serial Platform from TotalPhase, Inc. or

the Communications Accelerator Adaptor (CAA) with the

protocol software provided by onsemi. The key identifier

components and values are as follows:

• Chip Family: 0x06

• Chip Version: 0x01

• Chip Revision: 0x0200

The Ezairo 7160 SL hybrid is constructed with RoHS

compliant material with bump metallization of SAC305

(Sn96.5/Ag3.0/Cu0.5) solder.

This hybrid device is Moisture Sensitive Class MSL3 and

must be stored and handled accordingly. Re−flow according

to IPC/JEDEC standard J−STD−020C, Joint Industry

Standard: Moisture/Re−flow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices.

For soldering guidelines, please refer to the Soldering and

For the RSL10 chip, the key identifier components and

values are as follows:

Mounting

Techniques

Reference

Manual

(SOLDERRM/D).

• Chip Family: 0x09

Important Note: the maximum peak body temperature

reflow is 240°C vs the 260°C peak body temperature as

listed in Figure called “Typical Reflow Profile for Pb−Free

Solder (J−STD−020C)” of section “IR Reflow Profile” of

the SOLDERRM/D documentation.

• Chip Version: 0x01

• Chip Revision: 0x01

The hybrid ID can be found in the manufacturing area of

the EEPROM at address 0x00F1 to 0x00F2 (2 bytes =>

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17

EZAIRO 7160 SL HYBRID

TAPE & REEL INFORMATION

Electrostatic Discharge (ESD) Device

Company or Product Inquiries

CAUTION: ESD sensitive device. Permanent damage

may occur on devices subjected to high−energy electrostatic

discharges. Proper ESD precautions in handling, packaging

and testing are recommended to avoid performance

degradation or loss of functionality.

For more information about onsemi products or services

visit our web site at http://onsemi.com.

Technical Contact Information

dsp.support@onsemi.com

Datasheet Document Classification: Advanced

Information Datasheet

Development Tools

For more information about which development tools best

suit your application, contact your local sales representative

or authorized distributor.

The Advance Information document is for a device that is

NOT fully qualified, but is in the final stages of the release

process, and for which production is eminent. While the

commitment has been made to produce the device, final

characterization and qualification may not be complete. The

Advance Information document is replaced with the “Fully

Released Technical Data” document once the device/part

becomes fully qualified. The Advance Information

document displays the following disclaimer at the bottom of

the first page: “This document contains information on

a new product. Specifications and information herein are

subject to change without notice.”

Tape and Reel and package information

Informations about the Tape and Reel used for the Ezairo

7160 SL (SIP57) can be found in the onsemi document

BRD8011−D.PDF, available on−line.

Communication Libraries

Communication libraries are available to support

Unidirectional Stereo Audio streaming from a remote

streamer to the hearing aid using Ezairo 7160 SL. While

audio is streamed to the hearing aids, the user is able to

control the hearing device from a smartphone.

EZAIRO is a registered trademark of of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States

and/or other countries.

Bluetooth is a registered trademark of Bluetooth SIG, Inc. Arm and Cortex are registered trademarks of Arm Limited.

Promira is a trademark of Total Phase, Inc.

www.onsemi.com

18

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SIP57 6.80x3.94

CASE 127EX

ISSUE B

DATE 10 MAR 2022

GENERIC

MARKING DIAGRAM*

XXXXXXXXXXXX

ZZZZZZ

NNNNN

XXXX = Specific Device Code

ZZZ = Assembly Lot Code

NNN = Serial Number

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON80926G

SIP57 6.80x3.94

PAGE 1 OF 1

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	E7160-0-102A57-BPG
厂家：	ONSEMI
描述：	音频处理器，用于助听器的无线功能 DSP 无线
文件：	总20页 (文件大小：1104K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

E7160-0-102A57-BPG [ONSEMI]

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