EMI9404MUTAG [ONSEMI]
EMI Array, 4-Channel, with ESD Protection;
| 型号： | EMI9404MUTAG |
| 厂家： | 
ONSEMI |
| 描述： | EMI Array, 4-Channel, with ESD Protection |
| 文件： | 总6页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EMI9404
PRAETORIAN) III
4-Channel EMI Array with
ESD Protection
Description
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The EMI9404 is an inductor−based (L−C) EMI filter array with
ESD protection, which integrates four filters in a UDFN package with
0.40 mm pitch. Each EMI filter channel of the EMI9404 is
MARKING
DIAGRAMS
implemented
with
the
component
value
of
8
UDFN8
L4 MG
1.8 pF−35 nH–4.7 pF−35 nH– 6 pF. The cut−off frequency at −3 dB
attenuation is 300 MHz and can be used in applications where the data
rates are as high as 160 Mbps, while providing greater than −35 dB
attenuation over the 800 MHz to 2.7 GHz frequency range. The parts
include ESD diodes on every I/O pin and provide a high level of
protection against electrostatic discharge (ESD). The ESD protection
diodes connected to the external filter ports are designed and
characterized to safely dissipate ESD strikes of 14 kV, which is
beyond the maximum requirement of the IEC61000−4−2 international
standard.
CASE 517BC
G
1
1
L4
= Specific Device Code
= Date Code
= Pb−Free Package
M
G
(*Note: Microdot may be in either location)
PINOUTS
Internal Pins
(Lower ESD Event)
This device is particularly well suited for wireless handsets, mobile
LCD modules and PDAs because of its small package format and
easy−to−use pin assignments. In particular, the EMI9404 is ideal for
EMI filtering and protecting data and control lines for the LCD display
and camera interface in mobile handsets.
1
2
3
4
GND
8
7
6
5
The EMI9404 is housed in space saving, low profile, 0.40 mm pitch
UDFN packages in a RoHS compliant, Pb−Free format.
External Pins
(Higher ESD Event)
(Bottom View)
Features
• Four Channels of EMI Filtering with Integrated ESD Protection
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
•
14 kV ESD Protection (IEC 61000−4−2, contact discharge) at
External Pin
• Greater than −40 dB Attenuation (typical) at 1 GHz
• UDFN Pb−Free Package with 0.40 mm Lead Pitch:
4−ch. = 8−lead UDFN
• UDFN Package Size: 8−lead: 1.70 mm x 1.35 mm
• Increased Robustness Against Vertical Impacts During
Manufacturing Process
• These Devices are Pb−Free and are RoHS Compliant
Applications
• LCD and Camera Data Lines in Mobile Handsets
• I/O Port Protection for Mobile Handsets, Notebook
Computers, PDAs etc.
• EMI Filtering for Data Ports in Cell Phones, PDAs or
Notebook Computers
• Wireless Handsets
• Handheld PCs/PDAs
• LCD and Camera Modules
©
Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
January, 2013 − Rev. 1
EMI9404/D
EMI9404
Figure 1. Electrical Schematic
Table 1. PIN DESCRIPTIONS
Pin #
Name
Description
1
FILTER1
FILTER2
FILTER3
FILTER4
FILTER4
FILTER3
FILTER2
FILTER1
GND
Filter + ESD Channel 1 (Internal)
Filter + ESD Channel 2 (Internal)
Filter + ESD Channel 3 (Internal)
Filter + ESD Channel 4 (Internal)
Filter + ESD Channel 4 (External)
Filter + ESD Channel 3 (External)
Filter + ESD Channel 2 (External)
Filter + ESD Channel 1 (External)
Device Ground
2
3
4
5
6
7
8
GND PAD
SPECIFICATIONS
MAXIMUM RATINGS
Parameter
Value
–65 to +150
15
Unit
°C
Storage Temperature Range
Current per Inductor
mA
mW
DC Package Power Rating
500
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
STANDARD OPERATING CONDITIONS
Parameter
Rating
Unit
Operating Temperature Range
–40 to +85
°C
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2
EMI9404
ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Total Channel Inductance
Conditions
Min
Typ
70
Max
24
Unit
nH
W
L
TOT
R
TOT
Total Channel DC Resistance
Total Channel Capacitance, 0 V bias
Total Channel Capacitance, 2.5 V bias
Stand−off Voltage
45
C
TOT_0V
TOT_2.5V
ST
LEAK
SIG
0 V dc; 1 MHz, 30 mV
17.5
11.5
pF
pF
V
rms
C
2.5 V dc; 1 MHz, 30 mV
rms
V
I = 10 mA
5.5
I
Diode Leakage Current
VIN = +3.3 V
0.1
0.5
mA
V
V
Signal Clamp Voltage Positive Clamp
Negative Clamp
I
LOAD = 10 mA
LOAD = −10 mA
5.6
−1.5
6.8
−0.8
9.0
−0.4
I
VESD
In−system ESD Withstand Voltage
a) Contact discharge per IEC 61000−4−2
standard, Level 4 (External Pins)
b) Contact discharge per IEC 61000−4−2
standard, Level 1 (Internal Pins)
c.) Air discharge per IEC61000−4−2
standard. Level 4 (External Pins)
Notes 2 and 3
14
kV
2
16
V
C
Clamping Voltage
TLP (Note 4)
See Figures 4 through 7
I
PP
PP
= 8 A
= 16 A
= −8 A
= −16 A
13.7
20
−4.4
−7.6
V
PP
I
I
I
PP
fC
Cut−off frequency ZSOURCE = 50 W,
345
MHz
Z
LOAD = 50 W
1. T = 25°C unless otherwise specified.
A
2. ESD applied to input and output pins with respect to GND, one at a time.
3. Unused pins are left open.
4. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.
0
p
r
1
2
PERFORMANCE INFORMATION
TYPICAL FILTER PERFORMANCE
(T = 25°C, DC Bias = 0 V, 50 W Environment)
A
TYPICAL DIODE CAPACITANCE VS. INPUT
VOLTAGE
Figure 3. Filter Capacitance vs. Input Voltage
(Normalized to Capacitance at 0 VDC and 25°C)
Figure 2. Typical Filter Insertion Loss
ORDERING INFORMATION
†
Device
Pins
Marking
Package
Shipping
EMI9404MUTAG
8
L4
uDFN−8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
EMI9404
VOLTAGE (V)
VOLTAGE (V)
Figure 4. Positive TLP I−V Curve
Figure 5. Negative TLP I−V Curve
Transmission Line Pulse (TLP) Measurement
detail on TLP datasheet parameters, while application note
AND9006/D provides a more complete explanation of the
use of TLP for understanding protection product
characteristics.
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 6. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 7 where an 8 kV IEC 61000−4−2
current waveform into a short is compared with TLP current
pulses at 8 A and 16 A, also into a short. A TLP I−V curve
shows the voltage at which the device turns on, as well as
how well the device clamps voltage over a range of current
levels. Typical TLP I−V curves for the EMI9404 are shown
in Figures 4 and 5 for positive and negative stress
respectively. Application note AND9007/D gives more
50 W Coax
Cable
L
Attenuator
S
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 6. Simplified Schematic of a Typical TLP
System
Figure 7. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
PRAETORIAN s a registered trademark of Semiconductor Components Industries (SCILLC).
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8, 1.7x1.35, 0.4P
CASE 517BC
8
ISSUE A
1
DATE 11 AUG 2022
SCALE 4:1
GENERIC
MARKING DIAGRAMS*
XX MG
XXXMG
G
G
1
1
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON47060E
UDFN8, 1.7x1.35, 0.4P
PAGE 1 OF 1
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