ESD10201MUT5G [ONSEMI]
Low Capacitance ESD Protection Diodes;
| 型号： | ESD10201MUT5G |
| 厂家： | 
ONSEMI |
| 描述： | Low Capacitance ESD Protection Diodes |
| 文件： | 总6页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD10201
Low Capacitance ESD
Protection Diodes
Micro−package Diodes for ESD Protection
The ESD10201 is designed to protect voltage sensitive components
that require ultra−low capacitance from ESD and transient voltage
events. Excellent clamping capability, low capacitance, low leakage,
and fast response time make these parts ideal for ESD protection on
designs where board space is at a premium. It has industry leading
capacitance linearity over voltage making it ideal for RF applications.
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1
2
Features
MARKING
DIAGRAM
• Low Capacitance 0.3 pF (Typical)
• Low Clamping Voltage
• Small Body Outline Dimensions: (0.62 x 0.32 mm) − 0201
• Low Body Height: 0.3 mm
PIN 1
Y M
X3DFN2
CASE 152AF
• Working Voltage: 21 V
• IEC61000−4−2 Level 4 ESD Protection
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Y
M
= Specific Device Code
= Date Code
*Date Code orientation and/or position may vary de-
pending upon manufacturing location.
Typical Applications
• RF Signal ESD Protection
• Wireless Charger
ORDERING INFORMATION
• RF Switching, PA, and Antenna ESD Protection
• Near Field Communications
†
Device
Package
Shipping
ESD10201MUT5G
X3DFN2
(Pb−Free)
15000 / Tape &
Reel
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Rating
Symbol
Value
15
Unit
kV
kV
A
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
IEC 61000−4−2 (ESD) (Note 1) Air
IEC 61000−4−2 (ESD) (Note 1) Contact
IEC 61000−4−5 (ESD) (Note 2)
12
1
Total Power Dissipation (Note 3) @ T = 25°C
°P °
250
400
mW
°C/W
A
D
Thermal Resistance, Junction−to−Ambient
R
q
JA
Junction and Storage Temperature Range
T , T
−55 to
+150
°C
J
stg
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Non−repetitive current pulse at T = 25°C, per IEC61000−4−2 waveform.
A
2. Non−repetitive current pulse at T = 25°C, per IEC61000−4−5 waveform.
A
3. Mounted with recommended minimum pad size, DC board FR−4
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
May, 2015 − Rev. 0
ESD10201/D
ESD10201
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
I
PP
Symbol
Parameter
I
Maximum Reverse Peak Pulse Current
PP
I
T
I
V
R
BR RWM
V
C
V
V
Clamping Voltage @ I
C
PP
V
I
V
V
V
R
T
RWM BR C
V
RWM
Working Peak Reverse Voltage
I
I
R
Maximum Reverse Leakage Current @ V
RWM
V
Breakdown Voltage @ I
Test Current
BR
T
I
PP
I
T
Bi−Directional ESD
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, For min/max values T = 0°C to 60°C)
A
A
Parameter
Working Voltage
Symbol
Condition
Min
Typ
Max
Unit
V
RWM
21
V
V
Breakdown Voltage (Note 4)
Reverse Current
V
BR
I = 1 mA
21.2
T
I
R
V
RVM
= 21 V
200
nA
Clamping Voltage (Note 5)
V
C
IEC61000−4−2, 8 kV Contact
See Figures 1 and 2
Clamping Voltage TLP
(Note 6)
V
C
I
= 8 A
= 16 A
= −8 A
= −16 A
37.7
40.4
−38.4
−41.1
V
PP
I
PP
I
PP
I
PP
Clamping Voltage (Note 6)
Junction Capacitance
Dynamic Resistance
Insertion Loss
Vc
I
= 1 A @ 8/20 ms
35
0.3
V
pF
W
PP
C
V
= 0 V, f = 1 MHz
J
R
R
TLP Pulse
0.44
DYN
f = 1 MHz
f = 8.5 GHz
−0.045
−0.335
dB
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
5. For test procedure see Figures 3 and 4 and application note AND8307/D.
6. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.
0
p
r
1
2
TYPICAL CHARACTERISTICS
160
140
120
100
80
20
0
−20
−40
−60
60
40
20
−80
−100
−120
0
−140
−160
−20
−25
0
25
50
75
100
125
150
175
−25
0
25
50
75
100
125
150 175
TIME (ns)
TIME (ns)
Figure 1. Typical IEC61000−4−2 + 8 kV Contact
ESD Clamping Voltage
Figure 2. Typical IEC61000−4−2 − 8 kV Contact
ESD Clamping Voltage
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2
ESD10201
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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3
ESD10201
−18
−16
−14
−12
−10
−8
18
16
14
12
10
8
−6
6
4
−4
2
0
−2
0
0
5
10
15
20
25
30
35
40
45
0
−5 −10 −15 −20 −25 −30 −35 −40 −45
VOLTAGE (V)
VOLTAGE (V)
Figure 5. Typical Positive TLP IV Curve
Figure 6. Typical Negative TLP IV Curve
NOTE: TLP parameter: Z = 50 W, t = 100 ns, t = 300 ps, averaging window: t = 30 ns to t = 60 ns.
0
p
r
1
2
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 7. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 8 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 7. Simplified Schematic of a Typical TLP
System
Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD10201
TYPICAL CHARACTERISTICS
1.E−02
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
1.E−08
1.E−09
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.E−10
1.E−11
0.1
0
−30 −25 −20 −15 −10 −5
0
5
10 15 20 25 30
−25 −20 −15 −10 −5
0
5
10
15 20 25
VOLTAGE (V)
V
Bias
(V)
Figure 9. Typical IV Characteristics
Figure 10. Typical CV Characteristics
1
0
0.6
0.5
0.4
0.3
0.2
−1
−2
−3
−4
−5
−6
−7
−8
0.1
0
−9
−10
1.E+07
1.E+08
1.E+09
1.E+10
0.E+00
1.E+09
2.E+09
3.E+09
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Typical Insertion Loss
Figure 12. Typical Capacitance over
Frequency
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5
ESD10201
PACKAGE DIMENSIONS
X3DFN2, 0.62x0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
PIN 1
INDICATOR
(OPTIONAL)
MILLIMETERS
DIM MIN
MAX
0.33
0.05
0.28
0.66
0.36
A
A1
b
D
E
0.25
−−−
E
TOP VIEW
0.22
0.58
0.28
e
0.355 BSC
0.23
L2 0.17
0.05
0.05
C
C
A
RECOMMENDED
2X
A1
SIDE VIEW
MOUNTING FOOTPRINT*
SEATING
PLANE
C
2X
0.74
0.30
e
1
2X b
1
2
2X
0.31
DIMENSIONS: MILLIMETERS
M
0.05
C A B
2X L2
See Application Note AND8398/D for more mounting details
M
0.05
C A B
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
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particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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ESD10201/D
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