ESD7008MUTAG [ONSEMI]
ESD Protection Diodes;型号: | ESD7008MUTAG |
厂家: | ONSEMI |
描述: | ESD Protection Diodes 局域网 二极管 |
文件: | 总10页 (文件大小:291K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ESD7008, SZESD7008
ESD Protection Diodes
Low Capacitance ESD Protection for
High Speed Data
The ESD7008 ESD protection diode is designed specifically to
protect four high speed differential pairs. Ultra−low capacitance and
low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance for the high speed lines.
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MARKING
DIAGRAM
18
1
7008MG
UDFN18
CASE 517BV
G
Features
• Integrated 4 Pairs (8 Lines) High Speed Data
• Single Connect, Flow through Routing
• Low Capacitance (0.12 pF Typical, I/O to GND)
7008
M
= Specific Device Code
= Date Code
= Pb−Free Package
G
• Protection for the Following IEC Standards:
(Note: Microdot may be in either location)
IEC 61000−4−2 Level 4
• UL Flammability Rating of 94 V−0
ORDERING INFORMATION
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
Device
Package
Shipping
ESD7008MUTAG
UDFN18
(Pb−Free)
3000 / Tape &
Reel
• This is a Pb−Free Device
Typical Applications
• V−by−One HS
• Thunderbolt (Light Peak)
• USB 3.0
SZESD7008MUTAG UDFN18
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• HDMI
• Display Port
• LVDS
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
−55 to +125
−55 to +150
260
Unit
°C
Operating Junction Temperature Range
Storage Temperature Range
T
J
T
stg
°C
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
°C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
15
15
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
August, 2016 − Rev. 6
ESD7008/D
ESD7008, SZESD7008
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin 1
Pin 2
Pin 4
Pin 5
Pin 7
Pin 8
Pin 10 Pin 11
GND
Pin 3
GND
Pin 6
GND
Pin 9
GND
Pin 13
GND
Pin 15
GND
Pin 17
Note: Only Minimum of 1 GND connection required
=
Figure 1. Pin Schematic
I/O
I/O
1
N/C
18
17
16
2
3
N/C
GND
GND
I/O
I/O
4
5
6
7
N/C
GND
I/O
15
N/C
GND
14
13
N/C
GND
N/C
8
9
I/O
N/C
GND
10
11
I/O
I/O
12
Figure 2. Pin Configuration
Note: Only minimum of one pin needs to be connected to ground for functional-
ity of all pins. All pins labeled “N/C” should have no electrical connection.
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2
ESD7008, SZESD7008
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
I/O Pin to GND (Note 1)
I = 1 mA, I/O Pin to GND
Min
Typ
Max
Unit
V
Reverse Working Voltage
Breakdown Voltage
V
RWM
5.0
V
BR
5.5
6.7
V
T
Reverse Leakage Current
Clamping Voltage (Note 1)
Clamping Voltage (Note 2)
I
V
= 5 V, I/O Pin to GND
1.0
10
mA
V
R
RWM
V
I
PP
= 1 A, I/O Pin to GND (8 x 20 ms pulse)
C
C
C
V
V
IEC61000−4−2, 8 kV Contact
See Figures 3 and 4
V
Clamping Voltage
TLP (Note 3)
I
PP
I
PP
=
=
8 A
16 A
13.2
18.2
See Figures 8 through 11
Junction Capacitance
C
V
V
= 0 V, f = 1 MHz between I/O Pins and GND
= 0 V, f = 1 MHz between I/O Pins and GND
0.12
0.02
0.15
pF
pF
J
R
Junction Capacitance
Difference
DC
J
R
1. Surge current waveform per Figure 7.
2. For test procedure see Figures 5 and 6 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.
0
p
r
1
2
90
80
70
60
50
40
30
20
10
0
0
−10
−20
−30
−40
−50
−10
−20
0
20
40
60
TIME (ns)
80
100
120
140
−20
0
20
40
60
80
100
120
140
TIME (ns)
Figure 3. IEC61000−4−2 +8 KV Contact
Clamping Voltage
Figure 4. IEC61000−4−2 −8 KV Contact
Clamping Voltage
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3
ESD7008, SZESD7008
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 5. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 7. 8 X 20 ms Pulse Waveform
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4
ESD7008, SZESD7008
22
20
18
16
14
12
10
8
−22
−20
−18
−16
−14
−12
−10
−8
6
−6
4
−4
2
−2
0
0
0
2
4
6
8
10 12 14 16 18 20 22
VOLTAGE (V)
0
2
4
6
8
10 12 14 16 18 20 22
VOLTAGE (V)
Figure 8. Positive TLP I−V Curve
Figure 9. Negative TLP I−V Curve
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 10. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 11 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 10. Simplified Schematic of a Typical TLP
System
Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
ESD7008, SZESD7008
Without ESD
With ESD7008
Figure 12. HDMI1.4 Eye Diagram with and without ESD7008. 3.4 Gb/s, 400 mVPP
Without ESD
With ESD7008
Figure 13. USB3.0 Eye Diagram with and without ESD7008. 5.0 Gb/s, 400 mVPP
Without ESD
With ESD7008
Figure 14. Thunderbolt Eye Diagram with and without ESD7008. 10 Gb/s, 400 mVPP
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6
ESD7008, SZESD7008
4
2
ESD7008
IO−GND
0
−2
−4
−6
−8
−10
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
FREQUENCY (Hz)
Figure 15. ESD7008 Insertion Loss
USB 3.0 Type A
Connector
StdA_SSTX+
Vbus
ESD7008
N/ C
N/ C
N/ C
N/ C
StdA_SSTX−
D−
N/C
N/C
N/C
Vbus
GND_DRAIN
D+
Iden or N/C
StdA_SSRX+
GND
StdA_SSRX−
Figure 16. USB3.0 Layout Diagram
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7
ESD7008, SZESD7008
Thunderbolt
Connector
ESD9X
GND
Hot Plug Detect
D3−
CONFIG1
D3+
ESD7008
CONFIG2
GND
GND
D2−
D0−
D2+
D0+
GND
GND
D1−
AUX_CH+
D1+
AUX_CH−
GND
DP_PWR
CONFIG 1
CONFIG 2
AUX_CH+
NUP4114
Figure 17. Thunderbolt Layout Diagram
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8
ESD7008, SZESD7008
HDMI
Type A Connector
ESD7008
D2+
GND
D2−
D1+
GND
D1−
D0+
GND
D0−
CLK +
GND
CLK −
CEC
N/C (or HEC _DAT – HDMI 1.4)
SCL
SDA
GND
5V
HPD (and HEC _DAT – HDMI 1.4)
NUP4114
Figure 18. HDMI Layout Diagram
ESD7008
Figure 19. V−by−One HS Layout Diagram (for LCD Panel)
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9
ESD7008, SZESD7008
PACKAGE DIMENSIONS
UDFN18, 5.5x1.5, 0.5P
CASE 517BV
ISSUE A
NOTES:
L2
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A B
E
PIN ONE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. EXPOSED ENDS OF TERMINALS ARE
ELECTRICALLY ACTIVE.
REFERENCE
L1
2X
0.10
C
DETAIL A
OPTIONAL
CONSTRUCTIONS
2X
0.10
C
TOP VIEW
MILLIMETERS
DIM MIN
MAX
0.55
0.05
DETAIL B
(A3)
EXPOSED Cu
MOLD CMPD
A
A1
A3
b
0.45
0.00
0.13 REF
0.05
0.10
C
C
A
0.15
0.25
D
D2
E
E2
eA
eB
L
L1
L2
5.50 BSC
DETAIL B
0.45
0.55
NOTE 4
SEATING
PLANE
OPTIONAL
A1
C
SIDE VIEW
1.50 BSC
CONSTRUCTION
0.35
0.45
0.50 BSC
0.75 BSC
D2
0.20
0.00
0.40
0.05
eA
eB
DETAIL A
NOTE 5
1
0.10 REF
11
E2
RECOMMENDED
SOLDERING FOOTPRINT*
18
12
L
18X b
1.50
PITCH
END VIEW
M
0.10
C A B
0.75
PITCH
M
NOTE 3
C
0.05
18X
0.50
3X
0.60
BOTTOM VIEW
3X
0.50
1.80
18X
0.30
0.50
PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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ESD7008/D
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