ESD7351 [ONSEMI]
Transient Voltage Suppressors;
| 型号： | ESD7351 |
| 厂家： | 
ONSEMI |
| 描述： | Transient Voltage Suppressors |
| 文件： | 总8页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD7351, SZESD7351
Series
Transient Voltage
Suppressors
The ESD7351 Series is designed to protect voltage sensitive
components that require ultra−low capacitance from ESD and
transient voltage events. Excellent clamping capability, low
capacitance, low leakage, and fast response time, make these parts
ideal for ESD protection on designs where board space is at a
premium. Because of its low capacitance, it is suited for use in high
frequency designs such as USB 2.0 high speed and antenna line
applications.
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MARKING
DIAGRAMS
2
SOD−323
CASE 477
AF
M
1
1
Features
• Low Capacitance (0.6 pF Max, I/O to GND)
• Low Clamping Voltage
2
SOD−523
CASE 502
AE
1
2
• Stand−off Voltage: 3.3 V
• Low Leakage
• Response Time is < 1 ns
• Low Dynamic Resistance < 1 W
• IEC61000−4−2 Level 4 ESD Protection
SOD−923
CASE 514AB
AD M
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
X, XX = Specific Device Code
M
= Date Code
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
PIN CONFIGURATION
AND SCHEMATIC
Compliant
Typical Applications
• RF Signal ESD Protection
• RF Switching, PA, and Antenna ESD Protection
• Near Field Communications
1
2
Cathode
Anode
MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)
Symbol
Value
Unit
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Contact
Air
20
20
kV
Total Power Dissipation on FR−5 Board
°P °
D
150
mW
(Note 1) @ T = 25°C
A
Junction and Storage Temperature Range T , T
−55 to +150
260
°C
°C
J
stg
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
September, 2014 − Rev. 2
ESD7351/D
ESD7351, SZESD7351 Series
ELECTRICAL CHARACTERISTICS
I
(T = 25°C unless otherwise noted)
A
I
F
Symbol
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
I
PP
V
C
PP
V
C
V V
BR RWM
V
Working Peak Reverse Voltage
RWM
V
I
V
F
R
T
I
R
Maximum Reverse Leakage Current @ V
I
RWM
V
Breakdown Voltage @ I
Test Current
BR
T
I
T
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
I
PP
Uni−Directional TVS
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
V
Reverse Working Voltage
Breakdown Voltage (Note 2)
Reverse Leakage Current
Clamping Voltage (Note 3)
Clamping Voltage (Note 3)
Junction Capacitance
V
RWM
3.3
V
BR
I = 1 mA
5.0
V
T
I
R
V
RWM
= 3.3 V
< 1.0
50
8.0
10
nA
V
V
C
I
PP
I
PP
= 1 A
V
C
= 3 A
V
C
V
R
V
R
= 0 V, f = 1 MHz
= 0 V, f < 1 GHz
0.43
0.43
0.6
0.6
pF
J
Dynamic Resistance
R
TLP Pulse
0.35
W
DYN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
3. Non−repetitive current pulse at T = 25°C, per IEC61000−4−5 waveform.
A
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2
ESD7351, SZESD7351 Series
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
1.E−11
1.E−12
1.0
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
7
8
0
0.5
1
1.5
2
2.5
3
3.5
V (V)
VBias (V)
Figure 1. IV Characteristics
Figure 2. CV Characteristics
2.0
2
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−2
−4
−6
−8
−10
−12
−14
1.E+08
1.E+09
1.E+10
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5
FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 3. RF Insertion Loss
Figure 4. Capacitance over Frequency
16
8
6
4
2
0
−16
−14
−12
−10
−8
8
6
4
2
0
14
12
10
8
6
−6
4
−4
2
−2
0
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
V , VOLTAGE (V)
C
V , VOLTAGE (V)
C
Figure 5. Positive TLP I−V Curve
Figure 6. Negative TLP I−V Curve
NOTE: TLP parameter: Z = 50 W, t = 100 ns, t = 300 ps, averaging window: t = 30 ns to t = 60 ns. V is the equivalent voltage
IEC
0
p
r
1
2
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
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3
ESD7351, SZESD7351 Series
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 7. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 8. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
50 W Coax
Cable
L
Attenuator
S
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
Figure 9. Simplified Schematic of a Typical TLP
System
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4
ESD7351, SZESD7351 Series
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ORDERING INFORMATION
†
Device
Package
Shipping
ESD7351HT1G,
SZESD7351HT1G*
SOD−323
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
8000 / Tape & Reel
ESD7351XV2T1G,
SZESD7351XV2T1G*
SOD−523
(Pb−Free)
ESD7351P2T5G,
SZESD7351P2T5G*
SOD−923
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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5
ESD7351, SZESD7351 Series
PACKAGE DIMENSIONS
SOD−323
CASE 477−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
H
E
2. CONTROLLING DIMENSION: MILLIMETERS.
3. LEAD THICKNESS SPECIFIED PER L/F DRAWING
WITH SOLDER PLATING.
D
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
5. DIMENSION L IS MEASURED FROM END OF RADIUS.
1
E
b
2
MILLIMETERS
DIM MIN NOM MAX
0.80
INCHES
NOM MAX
1.00 0.031 0.035 0.040
0.10 0.000 0.002 0.004
0.006 REF
MIN
A
0.90
0.05
A1 0.00
A3
A
A3
0.15 REF
0.32
0.12 0.177 0.003 0.005 0.007
1.70
1.25
b
C
D
E
L
0.25
0.089
1.60
1.15
0.08
2.30
0.4 0.010 0.012 0.016
1.80 0.062 0.066 0.070
1.35 0.045 0.049 0.053
0.003
H
2.50
2.70 0.090 0.098 0.105
E
L
A1
C
NOTE 5
NOTE 3
SOLDERING FOOTPRINT*
0.63
0.025
0.83
0.033
1.60
0.063
2.85
0.112
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
ESD7351, SZESD7351 Series
PACKAGE DIMENSIONS
SOD−523
CASE 502
ISSUE E
−X−
D
NOTES:
6. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
−Y−
7. CONTROLLING DIMENSION: MILLIMETERS.
8. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
E
9. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-
TRUSIONS, OR GATE BURRS.
1
2
2X b
MILLIMETERS
M
0.08
X Y
DIM
A
b
c
D
E
HE
L
MIN
0.50
0.25
0.07
1.10
0.70
1.50
NOM
0.60
0.30
0.14
1.20
MAX
0.70
0.35
0.20
1.30
0.90
1.70
TOP VIEW
0.80
1.60
A
0.30 REF
0.20
L2
0.15
0.25
c
HE
RECOMMENDED
SOLDERING FOOTPRINT*
SIDE VIEW
1.80
2X
0.48
2X
0.40
2X
L
PACKAGE
OUTLINE
DIMENSION: MILLIMETERS
2X
L2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
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7
ESD7351, SZESD7351 Series
PACKAGE DIMENSIONS
SOD−923
CASE 514AB
ISSUE C
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
−Y−
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-
TRUSIONS, OR GATE BURRS.
E
1
2
MILLIMETERS
DIM MIN NOM MAX
INCHES
NOM MAX
2X b
MIN
0.08 X
Y
A
b
c
0.34
0.15
0.07
0.75
0.55
0.95
0.37
0.20
0.12
0.80
0.60
0.40
0.25
0.17
0.85
0.65
1.05
0.013 0.015 0.016
0.006 0.008 0.010
0.003 0.005 0.007
0.030 0.031 0.033
0.022 0.024 0.026
0.037 0.039 0.041
0.007 REF
TOP VIEW
D
E
A
H
1.00
E
L
0.19 REF
0.10
L2 0.05
0.15
0.002 0.004 0.006
c
H
SOLDERING FOOTPRINT*
E
SIDE VIEW
1.20
2X
2X
0.25
0.36
2X
L
PACKAGE
OUTLINE
DIMENSIONS: MILLIMETERS
2X
L2
See Application Note AND8455/D for more mounting details
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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ESD7351/D
相关型号：
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