ESD7383NCTBG [ONSEMI]
ESD 保护，3 线，极低电容，用于 USB;
| 型号： | ESD7383NCTBG |
| 厂家： | 
ONSEMI |
| 描述： | ESD 保护，3 线，极低电容，用于 USB 局域网 测试 二极管 |
| 文件： | 总7页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD7383
ESD Protection
3−Line, Very Low Capacitance
Product Description
The ESD7383 is a 4−bump very low capacitance ESD protection
device in 0.4 mm CSP form factor. It is fully compliant with IEC
61000−4−2. The ESD7383 is RoHS II compliant.
www.onsemi.com
ELECTRICAL SCHEMATIC
Features
• These Devices are Pb−Free and are RoHS Compliant
CH1 (A1)
CH2 (B1)
CH3 (B2)
Applications
• ESD protection for USB (including USB OTG)
♦ USB compliance
High Speed USB port
Up to 480 Mb/s according to USB 2.0 high speed specification
GND (A2)
MARKING
DIAGRAM
WLCSP4
CASE 567CB
7M
7
= Specific Device Code
M = Date Code
PINOUT
B
B1
B2
A2
2
A1
1
A
BOTTOM VIEW
PIN DESCRIPTIONS
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Pin
Description
Rating
Symbol
Value
50
Unit
W
Peak Pulse Power Dissipation, 8 x 20 ms
Maximum Peak Pulse Current, 8 x 20 ms
Operating Junction Temperature Range
Storage Temperature Range
P
pk
A1
A2
B1
B2
ESD Channel 1
Device Ground
ESD Channel 2
ESD Channel 3
I
PP
2.5
A
T
J
−40 to +85
−55 to +150
8000
°C
°C
V
T
stg
IEC 61000−4−2 Contact (ESD)
ESD
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
October, 2017 − Rev. 1
EMD7383/D
ESD7383
ELECTRICAL SPECIFICATIONS AND CONDITIONS
ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Min
Typ
Max
Unit
V
Symbol
Parameter
Input Operating Supply Voltage
Breakdown Voltage
Conditions
V
IN
3.0
5.5
V
BR
I = 8 mA
T
6
V
I
Reverse Leakage Current
Channel Input Capacitance
Channel Input Capacitance Matching
V
= 3 V
100
1.5
nA
pF
pF
V
R
RM
C
At 1 MHz, V = 0 V
IN
IN
DC
At 1 MHz, V = 0 V
0.02
IN
IN
V
CL
Channel Clamp Voltage
Positive Transients
Negative Transients
I
PP
= 1 A, t = 8/20 ms
P
+10
−1.5
R
Dynamic Resistance
Positive Transients
Negative Transients
I
= 1 A, t = 8/20 ms
P
DYN
PP
Any I/O pin to Ground
0.6
0.5
W
W
1. All parameters specified at T = 25°C unless otherwise noted.
A
ORDERING INFORMATION
†
Part Number
ESD7383
Bumps
Variation
Part Marking
Package
Shipping
4
WLCSP4
7
CSP
(Pb−Free)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Figure 1. ESD Clamping Voltage Screenshot
Figure 2. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Negative 8 kV Contact per IEC61000−4−2
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2
ESD7383
IEC61000−4−2 Waveform
IEC61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Device
Under
Test
Oscilloscope
ESD Gun
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 5. 8 x 20 ms Pulse Waveform
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3
ESD7383
Figure 6. Positive TLP I−V Curve
Figure 7. Negative TLP I−V Curve
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. A typical TLP I−V
curve for the ESD7383 is shown in Figures 6 and 7.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC61000−4−2 and 8 A and 16 A TLP Waveforms
www.onsemi.com
4
ESD7383
Figure 10. 480 Mb/s USB Source
Clears USB 2.0 Hi Speed Mask
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP4, 0.8x0.8
CASE 567CB−01
ISSUE O
SCALE 4:1
DATE 26 JUL 2010
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A
D
B
E
PIN A1
REFERENCE
MILLIMETERS
2X
0.05
0.05
C
DIM
A
A1
A2
b
MIN
0.57
0.17
0.41 REF
0.24
MAX
0.63
0.24
2X
C
TOP VIEW
0.29
D
E
e
0.80 BSC
0.80 BSC
0.40 BSC
A2
0.05
C
C
A
RECOMMENDED
SOLDERING FOOTPRINT*
0.05
SEATING
PLANE
PACKAGE
OUTLINE
A1
NOTE 3
C
A1
SIDE VIEW
e
4X0.25
4X
b
0.40
PITCH
e
0.05
0.03
C
C
A B
0.40
B
PITCH
A
DIMENSIONS: MILLIMETERS
1
2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50305E
WLCSP4, 0.8X0.8
PAGE 1 OF 1
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