ESDM3032MXT5G [ONSEMI]
3.3 V 双向微型封装 ESD 保护二极管;
| 型号： | ESDM3032MXT5G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V 双向微型封装 ESD 保护二极管 二极管 |
| 文件： | 总8页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD Protection Diode
Micro−Packaged Diodes for ESD Protection
ESDM3032
The ESDM3032 is designed to protect voltage sensitive components
that require low capacitance from ESD and transient voltage events.
Excellent clamping capability, low capacitance, low leakage, and fast
response time, make these parts ideal for ESD protection on designs
where board space is at a premium.
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Features
• Low Clamping Voltage
2
1
• Small Body Outline Dimensions: 0.62 mm x 0.32 mm
• Low Body Height: 0.3 mm
• Stand−off Voltage: 3.3 V
MARKING
DIAGRAM
• IEC61000−4−2 Level 4 ESD Protection
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
PIN 1
3 M
Compliant
X3DFN2
CASE 152AF
Typical Applications
• mSD Card Protection
• Audio Line
3
M
= Specific Device Code
= Date Code
• GPIO
MAXIMUM RATINGS
ORDERING INFORMATION
Rating
IEC 61000−4−2 (ESD)
Symbol
Value
Unit
†
Device
ESDM3032MXT5G
Package
Shipping
Contact
Air
30
30
kV
X3DFN2
(Pb−Free)
10000 / Tape &
Reel
Total Power Dissipation on FR−5 Board
°P °
D
250
mW
(Note 1) @ T = 25°C
A
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Thermal Resistance, Junction−to−Ambient
R
400
−55 to +150
260
°C/W
°C
q
JA
Junction and Storage Temperature Range
T , T
J stg
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
July, 2021 − Rev. 1
ESDM3032/D
ESDM3032
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
I
PP
Symbol
Parameter
I
Maximum Reverse Peak Pulse Current
PP
I
T
I
V
R
BR RWM
V
Clamping Voltage @ I
V
C
V
C
PP
V
I
V
V
V
R
T
RWM BR C
V
RWM
Working Peak Reverse Voltage
I
I
R
Maximum Reverse Leakage Current @ V
RWM
V
Breakdown Voltage @ I
Test Current
BR
T
I
PP
I
T
Bi−Directional
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
3.3
Unit
V
Reverse Working Voltage
Breakdown Voltage
V
RWM
I/O Pin to GND
I = 1 mA, I/O Pin to GND
V
BR
4.1
5.7
V
T
Reverse Leakage Current
I
V
= 3.3 V, I/O Pin to GND
100
nA
V
R
RWM
I
PP
= 8 A
Clamping Voltage TLP
(Note 2)
V
7.2
8.5
C
IEC 61000−4−2 Level 2 equivalent
( 4 kV Contact, 8 kV Air)
I
PP
= 16 A
V
IEC 61000−4−2 Level 4 equivalent
( 8 kV Contact, 16 kV Air)
Reverse Peak Pulse Current
I
IEC61000−4−5 (8/20 ms)
= 7.5 A
7.5
8.5
8.5
A
V
PP
Clamping Voltage (8/20 ms)
(Note 3)
V
I
PP
9.7
10
C
Dynamic Resistance
Junction Capacitance
R
100 ns TLP Pulse
= 0 V, f = 1 MHz
0.16
8.5
W
DYN
C
V
R
pF
J
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 1 ns, averaging window; t = 70 ns to t = 90 ns.
0
p
r
1
2
3. Non−repetitive current pulse at T = 25°C, per IEC61000−4−5 waveform.
A
TYPICAL CHARACTERISTICS
50
40
30
20
10
0
30
20
10
0
−10
−20
−30
−10
−40
−50
−20
−30
−20
0
20
40
60
80
100
120
140
−20
0
20
40
60
80
100
120 140
TIME (ns)
TIME (ns)
Figure 1. ESD Clamping Voltage − Pin 1 to Pin 2
8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage − Pin 2 to Pin 1
8 kV Contact per IEC61000−4−2
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2
ESDM3032
TYPICAL CHARACTERISTICS
20
18
16
14
12
10
8
20
18
16
14
12
10
8
6
6
4
2
0
4
2
0
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
V
CTLP
(V)
V
CTLP
(V)
Figure 3. 100 ns TLP I−V Curve − Pin 1 to Pin 2
Figure 4. 100 ns TLP I−V Curve − Pin 2 to Pin 1
10
9
10
9
8
7
8
7
6
5
4
3
2
6
5
4
3
2
1
0
1
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
6
8
9
10
I
PK
(A)
I
PK
(A)
Figure 5. Clamping Voltage vs. Peak Pulse
Figure 6. Clamping Voltage vs. Peak Pulse
Current − Pin 1 to Pin 2 (tp = 8/20 ms)
Current − Pin 2 to Pin 1 (tp = 8/20 ms)
1E−03
1E−04
1E−05
1E−06
1E−07
1E−08
1E−09
1E−10
1E−11
1E−12
1E−13
10
9
8
7
6
5
4
3
2
1
0
−4
1E−14
1E−15
−6
−4
−2
0
2
4
6
−3
−2
−1
0
1
2
3
4
V
R
(V)
V
BIAS
(V)
Figure 7. Reverse Leakage Current
Figure 8. Line Capacitance, f = 1 MHz
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3
ESDM3032
TYPICAL CHARACTERISTICS
12
11
10
9
0
−1
−2
−3
−4
8
7
6
−5
−6
1E+07
1E+08
1E+09
1E+07
1E+08
1E+09
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. Insertion Loss
Figure 10. Capacitance Over Frequency
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4
ESDM3032
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 11. IEC61000−4−2 Spec
Device
Under
Test
Oscilloscope
ESD Gun
50 W
Cable
50 W
Figure 12. Diagram of ESD Test Setup
ESD Voltage Clamping
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 13. 8 x 20 ms Pulse Waveform
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5
ESDM3032
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 14. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 15 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 14. Simplified Schematic of a Typical TLP
System
Figure 15. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X3DFN2, 0.62x0.32, 0.355P, (0201)
CASE 152AF
ISSUE B
DATE 13 JAN 2023
SCALE 8:1
GENERIC
MARKING DIAGRAM*
PIN 1
XM
X
= Specific Device Code
M = Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON56472E
X3DFN2, 0.62X0.32, 0.355P, (0201)
PAGE 1 OF 1
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