FAD7171MX [ONSEMI]
600V, 4A, SOIC-8,High-Side Gate Drive IC;
| 型号： | FAD7171MX |
| 厂家： | 
ONSEMI |
| 描述： | 600V, 4A, SOIC-8,High-Side Gate Drive IC 栅 |
| 文件： | 总11页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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600 V / 4 A, High-Side
Automotive Gate Driver IC
8
1
SOIC−8 NB
CASE 751−07
FAD7171MX
Description
MARKING DIAGRAM
The FAD7171MX is a monolithic high−side gate drive IC that can
drive high−speed MOSFETs and IGBTs that operate up to +600 V. It
has a buffered output stage with all NMOS transistors designed for
high pulse current driving capability and minimum cross−conduction.
onsemi’s high−voltage process and common−mode noise−canceling
techniques provide stable operation of the high−side driver under high
dv/dt noise circumstances. An advanced level−shift circuit offers
8
FAD7171MX
ALYW
1
high−side gate driver operation up to V = −11 V for VBS = 15 V.
S
The UVLO circuit prevents malfunction when VBS is lower than
the specified threshold voltage. The high−current and low−output
voltage−drop feature make this device suitable for sustaining switch
drivers and energy−recovery switch drivers in automotive motor drive
inverters, switching power supplies, and high−power DC−DC
converter applications.
FAD717MX = Device
A
= Assembly Site
L
YW
= Wafer Lot Number
= Assembly Start Week
ORDERING INFORMATION
Features
†
• Floating Channel for Bootstrap Operation to +600 V
• 4 A Sourcing and 4 A Sinking Current Driving Capability
• Common−Mode dv/dt Noise−Cancelling Circuit
• 3.3 V and 5 V Input Logic Compatible
• Output In−phase with Input Signal
Device
FAD7171MX
Package
Shipping
SOIC8
(Pb−Free /
Halogen Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1. These devices passed wave soldering test by
JESD22A−111.
• Under−Voltage Lockout for VBS
• 8−SOIC Package, Case 751−07
(JEDEC MS−012, 0.150 inch Narrow Body)
• AEC−Q100 Qualified and PPAP Capable for Ambient Operating
Temperature from −40°C to 125°C
Applications
• Common Rail Injection Systems
• DC−DC Converter
• Motor Drive (Electric Power Steering, Fans)
Related Product Resources
• FAN7171 Product Folder
• FAD7171 Product Folder
• AND9674 Design and Application Guide of Bootstrap Circuit for
High−Voltage Gate−Drive IC
• AN−8102 Recommendations to Avoid Short Pulse Width Issues in
HVIC Gate Driver Applications
• AN−9052 Design Guide for Selection of Bootstrap Components
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
April, 2022 − Rev. 0
FAD7171MX/D
FAD7171MX
TYPICAL APPLICATION
15 V
VIN
RBOOT
DBOOT
FAD7171MX
VB
1
2
VDD
8
7
R1
CBOOT
PWM
IN
HO
VS
R2
L1
NC
GND
C1
3
4
6
5
NC
VOUT
C2
Figure 1. Typical Application
VDD
8
8
VDD
VB
HO
VS
UVLO
GND
7
6
7
6
R
R
S
NOISE
CANCELLER
IN
Q
Figure 2. Block Diagram
PIN CONFIGURATION
8
7
6
5
1
2
3
4
FAD7171MX
Figure 3. Pin Assignment (Top Through View)
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2
FAD7171MX
PIN DESCRIPTION
Pin No.
Symbol
Description
1
2
3
4
5
6
7
8
V
Supply Voltage
DD
IN
NC
Logic Input for High−Side Gate Driver Output
No Connection
GND
NC
Ground
No Connection
V
High−Voltage Floating Supply Return
High−Side Driver Output
High−Side Floating Supply
S
HO
V
B
ABSOLUTE MAXIMUM RATINGS
Symbol
Characteristics
Min
− 25
Max
Unit
V
V
V
High−Side Floating Offset Voltage
V
B
V + 0.3
B
S
B
High−Side Floating Supply Voltage
High−Side Floating Output Voltage
Low−Side and Logic Supply Voltage
Logic Input Voltage
−0.3
625.0
V
V
HO
V
DD
V − 0.3
S
V + 0.3
B
V
−0.3
−0.3
−
25
V
V
IN
V
+ 0.3
50
V
DD
dV /dt
Allowable Offset Voltage Slew Rate
Power Dissipation (Notes 2, 3, 4)
Thermal Resistance
V/ns
W
S
P
D
−
0.625
200
q
−
°C/W
°C
°C
°C
V
JA
T
J
Junction Temperature
−55
−55
−40
−
150
T
STG
Storage Temperature
150
T
Operating Ambient Temperature
Human Body Model (HBM)
Charge Device Model (CDM)
125
A
ESD
2000
500
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR−4 glass epoxy material).
3. Refer to the following standards:
JESD51−2: Integral circuits thermal test method environmental conditions, natural convection, and
JESD51−3: Low effective thermal conductivity test board for leaded surface−mount packages.
4. Do not exceed power dissipation (P ) under any circumstances.
D
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
High−Side Floating Supply Voltage
Min
10
Max
20
Unit
V
V
BS
V
High−Side Floating Supply Offset Voltage (DC) @ VBS = 15 V
High−Side Output Voltage
−11
600
V
S
V
HO
V
S
V
B
V
V
Logic Input Voltage
GND
10
V
V
IN
DD
V
DD
Supply Voltage
20
V
T
Minimum Input Pulse Width
80
−
ns
PULSE
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
FAD7171MX
ELECTRICAL CHARACTERISTICS (V
(V , V ) = 15 V, −40°C ≤ T ≤ 125°C, unless otherwise specified. The V and I
IN
BIAS
DD
BS
A
IN
parameters are referenced to GND. The V and I parameters are relative to V and are applicable to the respective output HO)
O
O
S
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY SECTION
I
Quiescent V Supply Current
V = 0 V or 5 V
IN
−
−
85
200
170
mA
mA
QDD
DD
I
Operating V Supply Current
C
= 1 nF, f = 20 kHz
105
PDD
DD
LOAD
IN
BOOTSTRAPPED SUPPLY SECTION
V
V
Supply Under−Voltage Positive−Going
V
V
V
= Sweep
8.4
7.7
9.4
8.7
10.1
9.3
V
V
BSUV+
BSUV−
BSHYS
BS
BS
BS
BS
Threshold Voltage
V
V
BS
Supply Under−Voltage Negative−Going
= Sweep
Threshold Voltage
V
V
BS
Supply UVLO Hysteresis Voltage
= Sweep
−
−
−
−
0.7
−
−
50
V
I
LK
Offset Supply Leakage Current
Quiescent V Supply Current
V = V = 600 V
B
mA
mA
mA
S
I
V
IN
= 0 V or 5 V
43
620
95
QBS
BS
I
Operating V Supply Current
C
= 1 nF, f = 20 kHz
1200
PBS
BS
LOAD
IN
INPUT LOGIC SECTION (IN)
V
Logic “1” Input Voltage
1.8
−
−
−
0.8
−
V
V
IH
V
Logic “0” Input Voltage
IL
V
Logic Input Hysteresis Voltage
Logic Input High Bias Current
Logic Input Low Bias Current
Input Pull−down Resistance
−
−
0.5
45
−
V
INHYS
I
I
V
V
= 5 V
100
2
mA
mA
kW
IN+
IN
= 0 V
−
IN−
IN
R
30
105
−
IN
GATE DRIVER OUTPUT SECTION (HO)
V
High Level Output Voltage (V
− V )
No Load
No Load
−
−
−
−
35
35
−
mV
mV
A
OH
BIAS
O
V
Low Level Output Voltage
OL
I
O+
Output High, Short−Circuit Pulsed Current
(Note 5)
V
HO
= 0 V, V = 5 V, PW ≤ 10 ms
2.5
4.0
IN
I
Output Low, Short−Circuit Pulsed Current
(Note 5)
V
HO
= 15 V, V = 0 V, PW ≤ 10 ms
2.5
−
4.0
−
−
A
V
O−
IN
V
Allowable Negative V Pin Voltage for IN
11
S
S
Signal Propagation to HO
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. These parameters guaranteed by design.
DYNAMIC ELECTRICAL CHARACTERISTICS (V
(V , V ) = 15 V, V = GND = 0 V, C =1000 pF, and −40°C ≤ T ≤ 125°C,
BIAS
DD
BS
S
L
A
unless otherwise specified)
Symbol
Parameter
Turn−On Propagation Delay
Turn−Off Propagation Delay
Turn−On Rise Time
Conditions
Min
−
Typ
48
46
11
Max
100
95
Unit
ns
t
V = 0 V
S
ON
t
V = 0 V
S
−
ns
OFF
t
R
−
18
ns
t
F
Turn−Off Fall Time
−
12
19
ns
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4
FAD7171MX
TYPICAL PERFORMANCE CHARACTERISTICS
60
55
50
45
40
35
30
60
55
50
45
40
35
30
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4. Turn−On Propagation Delay vs.
Temperature
Figure 5. Turn−Off Propagation Delay vs.
Temperature
14
16
14
12
10
8
12
10
8
6
6
4
4
2
2
0
0
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. Turn−On Rise Time vs. Temperature
Figure 7. Turn−Off Fall Time vs. Temperature
150
140
130
120
110
100
90
680
660
640
620
600
580
560
80
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. Operating VDD Supply Current vs.
Temperature
Figure 9. Operating VBS Supply Current vs.
Temperature
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5
FAD7171MX
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
8.85
8.8
9.5
9.4
9.3
9.2
8.75
8.7
8.65
8.6
8.55
8.5
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. VBS UVLO+ vs. Temperature
Figure 11. VBS UVLO− vs. Temperature
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.75
1.70
1.65
1.60
1.55
1.50
1.45
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Logic High Input Voltage vs.
Temperature
Figure 13. Logic Low Input Voltage vs.
Temperature
140
120
100
80
1.0
0.8
0.6
0.4
V
OL
0.2
0.0
60
−0.2
−0.4
−0.6
−0.8
−1.0
V
OH
40
20
0
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. RIN vs. Temperature
Figure 15. Output Voltage vs. Temperature
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6
FAD7171MX
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
6
5
4
3
2
1
6
V
HO
= 0 V, V = 5 V, PW ≤ 10 ms
V = 15 V, V = 0 V, PW ≤ 10 ms
HO IN
IN
5
4
3
2
1
0
0
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Output High, Short−Circuit Pulsed
Current vs. Temperature
Figure 17. Output Low, Short−Circuit Pulsed
Current vs. Temperature
10
7
Gate resistance = 100 mW,
Gate resistance = 100 mW,
9
6
5
4
3
2
1
0
C
= 100 nF, f = 20kHz
C
= 100 nF, f = 20kHz
LOAD IN
LOAD
IN
8
7
6
5
4
3
2
1
0
10
12
14
16
18
20
10
12
14
16
18
20
V
BS
(V)
V
BS
(V)
Figure 18. Output High, Short−Circuit Pulsed
Current vs. Supply Voltage
Figure 19. Output Low, Short−Circuit Pulsed
Current vs. Supply Voltage
140
60
125°C
−40°C
120
100
80
60
40
20
0
50
25°C
40 −40°C
25°C
30
20
10
0
125°C
10
12
14
16
18
20
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage (V
)
Supply Voltage (V
)
DD
BS
Figure 21. Quiescent VDD Supply Current vs.
Supply Voltage
Figure 20. Quiescent VBS Supply Current vs.
Supply Voltage
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7
FAD7171MX
SWITCHING TIME DEFINITIONS
15 V
+
V
DD
V
B
1
8
10 mF
10 nF
0.1 mF
10 mF
15 V
−
GND
V
S
4
2
6
7
FAD7171MX
1000 pF
IN
HO
Figure 22. Switching Time Test Circuit (Referenced 8−SOIC)
50%
50%
IN
t on t r
t off
t f
90%
90%
HO − VS
10%
10%
Figure 23. Switching Time Waveform Definitions
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
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