FAM65CR51ADZ1 [ONSEMI]
Power Integrated Module (PIM) Boost Converter Stage for Multiphase and Semi-Bridgeless PFC;
| 型号： | FAM65CR51ADZ1 |
| 厂家： | 
ONSEMI |
| 描述： | Power Integrated Module (PIM) Boost Converter Stage for Multiphase and Semi-Bridgeless PFC 功率因数校正 |
| 文件： | 总14页 (文件大小：683K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Boost Converter Stage in
APM16 Series for Multiphase
and Semi-Bridgeless PFC
with SiC Diodes
FAM65CR51ADZ1,
FAM65CR51ADZ2
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Features
• Integrated SIP or DIP Boost Converter Stage Power Module for
On−board Charger (OBC) in EV or PHEV
• 5 kV/1 sec Electrically Isolated Substrate for Easy Assembly
• Creepage and Clearance per IEC60664−1, IEC 60950−1
• Compact Design for Low Total Module Resistance
• Module Serialization for Full Traceability
• Lead Free, RoHS and UL94V−0 Compliant
• Automotive Qualified per AEC Q101 and AQG324 Guidelines
• Improved Performance with SiC Diodes
APMCD−A16
12 LEAD
CASE MODGG
Applications
• PFC Stage of an On−board Charger in PHEV or EV
Benefits
• Enable Design of Small, Efficient and Reliable System for Reduced
Vehicle Fuel Consumption and CO Emission
2
APMCD−B16
12 LEAD
CASE MODGK
• Simplified Assembly, Optimized Layout, High Level of Integration,
and Improved Thermal Performance
MARKING DIAGRAM
XXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
XXXX = Specific Device Code
ZZZ = Lot ID
AT
Y
= Assembly & Test Location
= Year
W
= Work Week
NNN = Serial Number
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
May, 2021 − Rev. 5
FAM65CR51ADZ1/D
FAM65CR51ADZ1, FAM65CR51ADZ2
ORDERING INFORMATION
Pb−Free and
RoHS Compliant Temperature (T )
Operating
Packing
Method
Part Number
Package
Lead Forming
Y−Shape
DBC Material
Al2O3
A
FAM65CR51ADZ1
FAM65CR51ADZ2
APM16−CDA
APM16−CDB
Yes
Yes
−40°C ~ 125°C
−40°C ~ 125°C
Tube
Tube
L−Shape
Al2O3
Pin Configuration and Description
Figure 1. Pin Configuration
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
AC1
Pin Description
1, 2
3
Phase 1 Leg of the PFC Bridge
Not Connected
NC
4
NC
Not Connected
5, 6
7, 8
9
B+
Positive Battery Terminal
Source Terminal of Q1
Gate Terminal of Q1
Gate Terminal of Q2
Source Terminal of Q2
Not Connected
Q1 Source
Q1 Gate
Q2 Gate
Q2 Source
NC
10
11, 12
13
14
NC
Not Connected
15, 16
AC2
Phase 2 Leg of the PFC Bridge
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2
FAM65CR51ADZ1, FAM65CR51ADZ2
INTERNAL EQUIVALENT CIRCUIT
Figure 2. Internal Block Diagram
Table 2. ABSOLUTE MAXIMUM RATINGS OF MOSFET (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Max
650
Unit
V
V
V
(Q1~Q2)
(Q1~Q2)
Drain−to−Source Voltage
Gate−to−Source Voltage
DS
GS
20
V
I
D
(Q1~Q2)
Drain Current Continuous (T = 25°C, V = 10 V) (Note 1)
41
A
C
GS
Drain Current Continuous (T = 100°C, V = 10 V) (Note 1)
25
A
C
GS
E
AS
(Q1~Q2)
Single Pulse Avalanche Energy (Note 2)
623
mJ
W
°C
°C
°C
P
D
Power Dissipation (Note 1)
Maximum Junction Temperature
Maximum Case Temperature
Storage Temperature
189
T
J
−55 to +150
−40 to +125
−40 to +125
T
C
T
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum continuous current and power, without switching losses, to reach T = 150°C respectively at T = 25°C and T = 100°C; defined
J
C
C
by design based on MOSFET R
and R
and not subject to production test
q
DS(ON)
JC
2. Starting T = 25°C, I = 6.5 A, R = 25 W
J
AS
G
DBC Substrate
Compliance to RoHS Directives
0.63 mm Al2O3 alumina with 0.3 mm copper on both sides.
DBC substrate is NOT nickel plated.
The power module is 100% lead free and RoHS compliant
2000/53/C directive.
Lead Frame
Solder
OFC copper alloy, 0.50 mm thick. Plated with 8 mm to
25.4 mm thick Matte Tin
Solder used is a lead free SnAgCu alloy.
Solder presents high risk to melt at temperature beyond
210°C. Base of the leads, at the interface with the package
body, should not be exposed to more than 200°C during
mounting on the PCB or during welding to prevent the
re−melting of the solder joints.
Flammability Information
All materials present in the power module meet UL
flammability rating class 94V−0.
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3
FAM65CR51ADZ1, FAM65CR51ADZ2
Table 3. ELECTRICAL SPECIFICATIONS OF MOSFET (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Conditions
I = 1 mA, V = 0 V
D
Min
650
3.0
−
Typ
−
Max
−
Unit
V
BV
Drain−to−Source Breakdown Voltage
Gate−to−Source Threshold Voltage
Q1 Low Side MOSFET
DSS
GS
V
GS(th)
V
GS
= V , I = 3.3 mA
−
5.0
51
51
−
V
DS
D
R
R
R
R
Q1
V
GS
= 10 V, I = 20 A
44
44
79
79
30
−
mW
mW
mW
mW
S
DS(ON)
DS(ON)
DS(ON)
DS(ON)
D
Q2
Q1
Q2
Q2 Low Side MOSFET
−
Q1 Low Side MOSFET
V
GS
= 10 V, I = 20 A, T = 125°C (Note 3)
−
D
J
Q2 Low Side MOSFET
−
−
g
FS
Forward Transconductance
Gate−to−Source Leakage Current
Drain−to−Source Leakage Current
V
DS
= 20 V, I = 20 A (Note 3)
−
−
D
I
V
=
20 V, V = 0 V
−100
−
+100
10
nA
mA
GSS
GS
DS
DS
I
V
= 650 V, V = 0 V
−
DSS
GS
DYNAMIC CHARACTERISTICS (Note 3)
C
Input Capacitance
V
V
= 400 V
−
−
−
−
4864
109
16
−
−
−
−
pF
pF
pF
pF
iss
DS
= 0 V
GS
C
Output Capacitance
oss
f = 1 MHz
= 0 to 520 V
DS
C
Reverse Transfer Capacitance
Effective Output Capacitance
rss
C
V
652
oss(eff)
V
GS
= 0 V
R
Gate Resistance
f = 1 MHz
−
−
−
−
2
−
−
−
−
W
g
Q
Total Gate Charge
V
= 380 V
= 20 A
123
37.5
49
nC
nC
nC
g(tot)
DS
I
D
Q
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
gs
gd
V
= 0 to 10 V
GS
Q
SWITCHING CHARACTERISTICS (Note 3)
t
Turn−on Time
V
= 400 V
= 20 A
−
−
−
−
−
−
87
47
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
on
DS
I
D
t
Turn−on Delay Time
Turn−on Rise Time
Turn−off Time
d(on)
V
= 10 V
GS
t
r
43
R
= 4.7 Ohm
G
t
146
118
29
off
d(off)
t
Turn−off Delay Time
Turn−off Fall Time
t
f
BODY DIODE CHARACTERISTICS
V
Source−to−Drain Diode Voltage
Reverse Recovery Time
I
= 20 A, V = 0 V
−
−
−
0.95
133
669
−
−
−
V
SD
SD
GS
T
V
= 520 V, I = 20 A,
ns
nC
rr
DS
t
D
d /d = 100 A/ms (Note 3)
I
Q
Reverse Recovery Charge
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Defined by design, not subject to production test
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4
FAM65CR51ADZ1, FAM65CR51ADZ2
Table 4. ABSOLUTE MAXIMUM RATINGS OF THE BOOST DIODE (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Peak Repetitive Reverse Voltage (Note 4)
Rating
650
Unit
V
V
RRM
E
Avalanche Energy (17 A, 1 mH)
144
mJ
A
AS
I
Continuous Rectified Forward Current, T < 148_C
30
F
C
I
I
Non−Repetitive Forward Surge Current, T = 25_C, 10 ms
1100
A
F,MAX
F,MAX
C
Non−Repetitive Forward Surge Current, T = 150_C, 10 ms
1000
A
C
I
Non−Repetitive Peak Surge Current (Sine Half Wave, Tp = 8.3 ms)
110
A
FSM
P
Power Dissipation (T = 25_C)
65
W
°C
°C
°C
D
C
T
Maximum Junction Temperature
Maximum Case Temperature
Storage Temperature
−55 to +175
−40 to +125
−40 to +125
J
T
C
T
STG
4. V
and I value referenced to TO220−2L Auto Qualified Package Device FFSP3065B_F085
F
RRM
Table 5. ELECTRICAL SPECIFICATIONS OF THE BOOST DIODE (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
DC Blocking Voltage
Test Conditions
Min
650
−
Typ
−
Max
−
Unit
V
V
DC
I
= 200 mA
T
C
T
C
= 25°C
= 25°C
R
V
F
Instantaneous Forward Voltage
Instantaneous Reverse Current
I = 30 A
1.38
1.6
1.7
2.0
2.4
40
V
F
T
= 125°C
= 175°C
= 25°C
−
V
C
C
T
−
1.72
0.5
V
I
R
V
= 650 V
T
C
−
mA
mA
mA
nC
pF
R
T
C
T
C
= 125°C
= 175°C
−
1.0
80
−
2.0
160
−
Q
Total Capacitive Charge
Total Capacitance
V
= 400 V
T
C
= 25°C
−
43
C
R
C
V
= 1 V
f = 100 kHz
f = 100 kHz
f = 100 kHz
1280
139
108
R
V
= 200 V
= 400 V
R
R
V
Table 6. THERMAL RESISTANCE
Parameters
Min
−
Typ
Max
Unit
°C/W
°C/W
°C/W
°C/W
R
R
(per MOSFET chip)
(per MOSFET chip)
(per DIODE chip)
Q1,Q2 Thermal Resistance Junction−to−Case (Note 5)
Q1,Q2 Thermal Resistance Junction−to−Sink (Note 6)
D1,D2 Thermal Resistance Junction−to−Case (Note 5)
D1,D2 Thermal Resistance Junction−to−Sink (Note 6)
0.47
0.95
1.78
3.10
0.66
−
θ
JC
JS
−
θ
R
R
−
2.3
−
θ
JC
(per DIODE chip)
−
θ
JS
5. Test method compliant with MIL STD 883−1012.1, from case temperature under the chip to case temperature measured below the package
at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed
6. Defined by thermal simulation assuming the module is mounted on a 5 mm Al−360 die casting material with 30 um of 1.8 W/mK thermal
interface material
Table 7. ISOLATION (Isolation resistance at tested voltage between the base plate and to control pins or power terminals.)
Test
Test Conditions
Isolation Resistance
Unit
Leakage @ Isolation Voltage (Hi−Pot)
V
AC
= 5 kV, 50 Hz
100M <
W
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5
FAM65CR51ADZ1, FAM65CR51ADZ2
PARAMETER DEFINITIONS
Reference to Table 3: Parameter of MOSFET Electrical Specifications
BV
Q1, Q2 MOSFET Drain−to−Source Breakdown Voltage
DSS
The maximum drain−to−source voltage the MOSFET can endure without the avalanche breakdown of the body− drain
P−N junction in off state.
The measurement conditions are to be found in Table 3.
The typ. Temperature behavior is described in Figure 13
V
GS(th)
Q1, Q2 MOSFET Gate to Source Threshold Voltage
The gate−to−source voltage measurement is triggered by a threshold ID current given in conditions at Table 4.
The typ. Temperature behavior can be found in Figure 10
R
Q1, Q2 MOSFET On Resistance
DS(ON)
RDS(on) is the total resistance between the source and the drain during the on state.
The measurement conditions are to be found in Table 3.
The typ behavior can be found in Figure 11 and Figure 12 as well as Figure 17
g
FS
Q1, Q2 MOSFET Forward Transconductance
Transconductance is the gain in the MOSFET, expressed in the Equation below.
It describes the change in drain current by the change in the gate−source bias voltage: g = [DI / DV ]
fs
DS
GS VDS
I
Q1, Q2 MOSFET Gate−to−Source Leakage Current
GSS
The current flowing from Gate to Source at the maximum allowed VGS
The measurement conditions are described in the Table 3.
I
Q1, Q2 MOSFET Drain−to−Source Leakage Current
DSS
Drain – Source current is measured in off state while providing the maximum allowed drain−to-source voltage and the
gate is shorted to the source.
IDSS has a positive temperature coefficient.
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6
FAM65CR51ADZ1, FAM65CR51ADZ2
Figure 3. Timing Measurement Variable Definition
Table 8. PARAMETER OF SWITCHING CHARACTERISTICS
Turn−On Delay (t
)
This is the time needed to charge the input capacitance, Ciss, before the load current ID starts flowing.
The measurement conditions are described in the Table 3.
For signal definition please check Figure 3 above.
d(on)
Rise Time (t )
The rise time is the time to discharge output capacitance, Coss.
After that time the MOSFET conducts the given load current ID.
The measurement conditions are described in the Table 3.
For signal definition please check Figure 3 above.
r
Turn−On Time (t
)
Is the sum of turn−on−delay and rise time
on
Turn−Off Delay (t
)
td(off) is the time to discharge Ciss after the MOSFET is turned off.
During this time the load current ID is still flowing
d(off)
The measurement conditions are described in the Table 3.
For signal definition please check Figure 3 above.
Fall Time (t )
The fall time, tf, is the time to charge the output capacitance, Coss.
During this time the load current drops down and the voltage VDS rises accordingly.
The measurement conditions are described in the Table 3.
f
For signal definition please check Figure 3 above.
Turn−Off Time (t
)
Is the sum of turn−off−delay and fall time
off
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FAM65CR51ADZ1, FAM65CR51ADZ2
TYPICAL CHARACTERISTICS − MOSFETs
1.2
1.0
0.8
0.6
0.4
50
V
GS
= 10 V
40
30
20
10
0.2
0
R
= 0.66°C/W
q
JC
R
= 0.66°C/W
q
JC
0
0
3
0
25
50
75
100
125
150
25
50
75
100
125
150
T , CASE TEMPERATURE (°C)
T , CASE TEMPERATURE (°C)
C
C
Figure 4. Normalized Power Dissipation vs.
Case Temperature
Figure 5. Maximum Continuous ID vs. Case
Temperature
V = 0 V
GS
60
50
40
30
20
V
= 20 V
DS
100
10
1
T = 25°C
J
T = 150°C
T = 25°C
J
J
0.1
T = 150°C
J
10
0
T = −55°C
J
0.01
4
5
6
7
8
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
, GATE−TO−SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
GS
Figure 6. Transfer Characteristics
Figure 7. Forward Diode
100
90
80
70
60
50
40
30
20
80
70
60
50
40
30
20
V
= 15 V
10 V
GS
8.0 V
V
= 15 V
GS
10 V
7.0 V
6.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
5.5 V
5.0 V
10
0
10
0
1
2
3
4
5
6
7
8
9
10
0
10 20 30
40 50 60 70
80 90 100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 8. On Region Characteristics (255C)
Figure 9. On Region Characteristics (1505C)
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8
FAM65CR51ADZ1, FAM65CR51ADZ2
TYPICAL CHARACTERISTICS − MOSFETs
200
150
100
2.5
I
V
= 20 A
I
D
= 20 A
D
= 10 V
GS
2.0
1.5
1.0
T = 150°C
J
T = 25°C
J
50
0
0.5
0
5.5
6.5
7.5
8.5
9.5
−75 −50 −25
0
25
50 75 100 125 150 175
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
J
Figure 10. On−Resistance vs. Gate−to−Source
Figure 11. RDS(norm) vs. Junction Temperature
Voltage
1.2
1.0
1.2
1.1
1.0
I
D
= 3.3 mA
I = 10 A
D
0.8
0.6
0.9
0.8
−75 −50 −25
0
25 50 75 100 125 150 175
−75 −50 −25
0
25 50 75 100 125 150 175
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 12. Normalized Gate Threshold Voltage
vs. Temperature
Figure 13. Normalized Breakdown Voltage vs.
Temperature
30
25
20
15
10
100k
10k
1k
C
ISS
C
C
OSS
100
RSS
V
= 0 V
GS
10
1
5
0
f = 1 MHz
0
100
200
300
400
500
600
700
0.1
1
10
100
1000
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 14. Eoss vs. Drain−to−Source Voltage
Figure 15. Capacitance Variation
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FAM65CR51ADZ1, FAM65CR51ADZ2
TYPICAL CHARACTERISTICS − MOSFETs
10
8
0.060
T
C
= 25°C
V
DD
= 130 V
0.055
0.050
V
= 400 V
DD
V
GS
= 10 V
6
4
V
GS
= 20 V
0.045
0.040
2
0
0
40
80
Q , GATE CHARGE (nC)
120
160
0
20
40
60
80
I , DRAIN CURRENT (A)
g
D
Figure 16. Gate Charge Characteristics
Figure 17. ON−Resistance Variation with Drain
Current and Gage Voltage
1000
100
10
1000
T
= 25°C
T
R
= 25°C
C
C
V
= 10 V
GS
10 ms
1 ms
100 ms
1 ms
= 0.66°C/W
q
For temperatures above 25°C
Derate peak current as follows:
JC
Single Pulse
10 ms
ǒ150 * TCǓ
Ǹ
I + I
Limited I
248 A
25
DM
125
100 ms
100
10
Notes:
= 0.66°C/W
Duty Cycle: D = t /t
1
R
Limit
DS(on)
R
q
JC
Thermal Limit
1
2
Package Limit
Single Pulse
Peak T = P
x Z (t) + T
q
JC C
J
DM
0.1
0.1
1
10
100
1000
0.000001 0.00001 0.0001 0.001
0.01
0.1
1
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
t, RECTANGULAR PULSE DURATION (s)
Figure 18. Safe Operating Area
Figure 19. Peak Current Capability
100k
10k
1k
100
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 20. Peak Power
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FAM65CR51ADZ1, FAM65CR51ADZ2
TYPICAL CHARACTERISTICS − DIODES
10
70
10
1
T = 175°C
J
T = 75°C
J
0.1
T = 25°C
J
T = 125°C
J
T = 25°C
J
T = 75°C
J
T = 175°C
T = −55°C
T = −55°C
J
J
T = 125°C
J
J
1
0.01
0
0.5
1.0
1.5
2.0
2.5
3.0
100
200
300
400
500
600
700
V , FORWARD VOLTAGE (V)
F
V , REVERSE VOLTAGE (V)
R
Figure 21. Typical Forward Voltage Drop vs.
Forward Current
Figure 22. Typical Reverse Current vs.
Reverse Voltage
10k
1k
f = 100 kHz
V
GS
= 0 V
100
10
0.1
1
1
10
100
1k
V , REVERSE VOLTAGE (V)
R
Figure 23. Capacitance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
Notes:
R
= 0.66°C/W
q
JC
Peak T = P
x Z (t) + T
q
JC C
J
DM
Duty Cycle, D = t /t
1
2
Single Pulse
0.000001 0.00001
0.001
0.0001
0.001
0.01
0.1
1
t, RECTANGULAR PULSE DURATION (s)
Figure 24. Transient Thermal Impedance
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCD−A16 / 12LD, AUTOMOTIVE MODULE
CASE MODGG
ISSUE C
DATE 03 NOV 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Lot ID
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
AT
Y
= Assembly & Test Location
= Year
XXXXXXXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
WW = Work Week
NNN = Serial Number
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON94738G
APMCD−A16 / 12LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCD−B16 / 12LD, AUTOMOTIVE MODULE
CASE MODGK
ISSUE D
DATE 04 NOV 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Lot ID
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
AT
Y
W
= Assembly & Test Location
= Year
= Work Week
XXXXXXXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
NNN = Serial Number
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON97134G
APMCD−B16 / 12LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
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