FAN2108EMPX [ONSEMI]

-8A，24V 输入，集成式同步降压稳压器;


型号：	FAN2108EMPX
厂家：	ONSEMI
描述：	-8A，24V 输入，集成式同步降压稳压器信息通信管理开关稳压器
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中文：	中文翻译
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August 2014

FAN2108 — TinyBuck™ 3-24 V Input, 8 A, High-

Efficiency, Integrated Synchronous Buck Regulator

Features

Description

The FAN2108 TinyBuck™ is a highly efficient, small

footprint, 8 A, synchronous buck regulator.

Wide Input Voltage Range: 3 V-24 V

Wide Output Voltage Range: 0.8 V to 80% V_IN

8 A Output Current

The FAN2108 contains both synchronous MOSFETs

and a controller/driver with optimized interconnects in

one package, which enables designers to solve high-

current requirements in a small area with minimal

external components.

Programmable Frequency Operation: 200 KHz to

600 KHz

Over 95% Peak Efficiency

External compensation, programmable switching

frequency, and current limit features allow design

optimization and flexibility.

Integrated Schottky Diode on Low-side MOSFET

Boosts Efficiency

Internal Bootstrap diode

The summing current mode modulator uses lossless

current sensing for current feedback and over-current

protection. Voltage feedforward helps operation over a

wide input voltage range.

Power-Good Signal

Pre-Bias Startup

Accepts Ceramic Capacitors on Output

External Compensation for Flexible Design

Input Under-Voltage Lockout

Programmable Current Limit

Fairchild’s advanced BiCMOS power process, combined

with low-R_DS(ON)internal MOSFETs and a thermally

efficient MLP package, provide the ability to dissipate

high power in a small package.

Under-Voltage, Over-Voltage, and Thermal

Shutdown Protections

Output over-voltage, under-voltage, and thermal

shutdown protections help protect the device from

damage during fault conditions. FAN2108 prevents

pre-biased output discharge during startup in point-of-

load applications.

Internal Soft-Start

5 x 6 mm, 25-Pin, 3-Pad MLP Package

Applications

Related Application Notes

Servers

AN-8022 — TinyCalc™ Calculator

Point-of-Load Regulation

High-End Computing Systems

Graphics Cards

Battery-Powered Equipment

Set-Top Boxes

Ordering Information

Operating Temperature

Packing

Part Number

Range

Package

Method

FAN2108MPX

-10°C to 85°C

-40°C to 85°C

Molded Leadless Package (MLP) 5 x 6 mm

Tape and Reel

FAN2108EMPX

FAN2108 • Rev. 1.0.3

www.fairchildsemi.com

Typical Application

Boot

+5V

Diode

C_HF

C_IN

VCC

BOOT

R_RAMP

C_BOOT

RAMP

PGOOD

Power

Good

OUT

C_OUT

Enable

R_ILIM

PWM

ILIM

DRIVER

R_T

R(T)

PGND

POWER

MOSFETS

COMP

AGND

24 NC

R_BIAS

Figure 1. Typical Application Diagram

Block Diagram

Figure 2. Block Diagram

FAN2108 • Rev. 1.0.3

www.fairchildsemi.com

Pin Configuration

Figure 3. MLP 5 x 6 mm Pin Configuration (Bottom View)

Pin Definitions

Pin #

P1, 6-12

P2, 2-5

Name

Description

Switching Node.

Power Input Voltage. Connect to the main input power source.

VIN

P3, 21-23

PGND Power Ground. Power return and Q2 source.

High-Side Drive BOOT Voltage. Connect through capacitor (C_BOOT) to SW. The IC includes

BOOT

PGOOD

an internal synchronous bootstrap diode to recharge the capacitor on this pin to V_CCwhen

SW is LOW.

Power-Good Flag. An open-drain output that pulls LOW when FB is outside a ±10% range

of the reference. PGOOD does not assert HIGH until the fault latch is enabled.

ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the

regulator after a latched fault condition. This input has an internal pull-up when the IC is

functioning normally. When a latched fault occurs, EN is discharged by a current sink.

VCC

Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin.

Analog Ground. The signal ground for the IC. All internal control voltages are referred to

this pin. Tie this pin to the ground island/plane through the lowest impedance connection.

AGND

Current Limit. A resistor (R_ILIM) from this pin to AGND can be used to program the current-

limit trip threshold lower than the default setting.

ILIM

Oscillator Frequency. A resistor (R_T) from this pin to AGND sets the PWM switching

frequency.

R(T)

Output Voltage Feedback. Connect through a resistor divider to the output voltage.

Compensation. Error amplifier output. Connect the external compensation network between

this pin and FB.

COMP

No Connect. This pin is not used.

Ramp Amplitude. A resistor (R_RAMP) connected from this pin to V_INsets the ramp amplitude

and provides voltage feedforward functionality.

RAMP

FAN2108 • Rev. 1.0.3

www.fairchildsemi.com

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Parameter

VIN to PGND

VCC to AGND

BOOT to PGND

BOOT to SW

Conditions

Min.

Max.

Unit

AGND=PGND

Continuous

-0.3

-0.5

-5

6.0

24.0

SW to PGND

All other pins

ESD

Transient (t < 20 ns, f < 600 KHz)

-0.3

V_CC+0.3

Human Body Model, JEDEC JESD22-A114

Charged Device Model, JEDEC JESD22-C101

2.5

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol

V_CC

Parameter

Conditions

Min.

4.5

Typ.

Max.

5.5

Unit

Bias Voltage

VCC to AGND

5.0

V_IN

Supply Voltage

VIN to PGND

FAN2108MPX

FAN2108EMPX

-10

-40

+85

+125

600

°C

kHz

T_A

Ambient Temperature

T_J

Junction Temperature

Switching Frequency

Thermal Information

Symbol

Parameter

Min.

Typ.

Max.

+150

+300

+215

+220

Unit

°C

T_STG

T_L

Storage Temperature

-65

Lead Soldering Temperature, 10 Seconds

Vapor Phase, 60 Seconds

°C

T_VP

T_I

°C

Infrared, 15 Seconds

°C

P1 (Q2)

P2 (Q1)

°C/W

Thermal Resistance: Junction-to-Case

θ_JC

Thermal Resistance: Junction-to-Mounting Surface⁽¹⁾

Power Dissipation, T_A=25°C⁽¹⁾

θ_J-PCB

P_D

2.8

Note:

1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 25. Actual results

are dependent on mounting method and surface related to the design.

FAN2108 • Rev. 1.0.3

www.fairchildsemi.com

Electrical Specifications

Electrical specifications are the result of using the circuit shown in Figure 1 unless otherwise noted.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Power Supplies

SW=Open, FB=0.7 V, V_CC=5 V,

_SW=600 KHz

I_CC

V_CCCurrent

Shutdown: EN=0, V_CC=5 V

Rising V_CC

µA

4.1

4.3

300

4.5

V_UVLO

V_CCUVLO Threshold

Hysteresis

Oscillator

255

540

300

600

345

660

KHz

R_T=50 KΩ

R_T=24 KΩ

Frequency

t_ON

Minimum On-Time⁽²⁾

16 V_IN, 1.8 V_OUT, R_T=30 KΩ,

R_RAMP=200 KΩ

V_RAMP

Ramp Amplitude, peak-to–peak

Minimum Off-Time⁽²⁾

0.53

100

t_OFF

150

Reference

FAN2108MPX, 25°C

FAN2108EMPX, 25°C

794

795

800 806

800 805

Reference Voltage (see Figure 4 for

Temperature Coefficient)

V_FB

Error Amplifier

DC Gain⁽²⁾

Gain Bandwidth Product⁽²⁾

MHz

V_CC=5 V

V_COMP

I_SINK

Output Voltage

0.4

1.5

0.8

3.2

2.2

1.2

Output Current, Sourcing

V_CC=5 V, V_COMP=2.2 V

V_CC=5 V, V_COMP=1.2 V

V_FB=0.8 V, 25°C

I_SOURCEOutput Current, Sinking

I_BIASFB Bias Current

Protection and Shutdown

-850 -650 -450

R_ILIMOpen at 25°C (see Circuit

Description)

I_LIM

Current Limit

-9

I_ILIM

T_TSD

T_HYS

V_OVP

V_UVLO

V_FLT

I_LIMCurrent

-11

-10

+155

+30

µA

°C

Over-Temperature Shutdown

Over-Temperature Hysteresis

Over-Voltage Threshold

Under-Voltage Shutdown

Fault Discharge Threshold

Internal IC Temperature

Two Consecutive Clock Cycles

16 Consecutive Clock Cycles

Measured at FB Pin

110

115 121 %V_OUT

78 %V_OUT

250

V_{FLT_HYS}Fault Discharge Hysteresis

Measured at FB Pin (V_FB~500 mV)

Soft-Start

t_SS

t_EN

V_OUTto Regulation (T0.8)

Fault Enable/SSOK (T1.0)

5.3

6.7

Frequency=600 KHz

Note:

2. Specifications guaranteed by design and characterization; not production tested.

www.fairchildsemi.com

FAN2108 • Rev. 1.0.3

Electrical Specifications (Continued)

Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Control Functions

V_{EN_R}

EN Threshold, Rising

1.35 2.00

V_{EN_HYS}EN Hysteresis

250

800

KΩ

µA

R_EN

I_EN

EN Pull-Up Resistance

EN Discharge Current

Auto-Restart Mode

R_FB

FB OK Drive Resistance

800

FB < V_REF

FB > V_REF

I_OUT< 2 mA

-14

-11

-8

V_PG

PGOOD Threshold

PGOOD Output Low

%V_REF

+10 +13.5

0.4

V_{PG_L}

FAN2108 • Rev. 1.0.3

www.fairchildsemi.com

Typical Characteristics

1.010

1.005

1.000

0.995

0.990

1.20

1.10

1.00

0.90

0.80

-50

100

150

-50

100

150

Temperature (^oC)

Figure 4. Reference Voltage (V_FB

)

Figure 5. Reference Bias Current (I_FB

)

vs. Temperature, Normalized

1500

1200

900

600

300

1.02

1.01

1.00

0.99

0.98

600KHz

300KHz

-50

100

150

100

120

140

Temperature (^oC)

R_T(K )

Figure 6. Frequency vs. R_T

Figure 7. Frequency vs. Temperature, Normalized

1.4

1.2

1.04

1.02

1.00

0.98

0.96

Q1 ~0.32%/°C

Q2 ~0.35%/°C

0.8

0.6

-50

100

150

100

150

Temperature (^oC)

Temperature (°C)

Figure 9. I_LIMCurrent (I_ILIM) vs. Temperature,

Normalized

Figure 8. R_DSvs. Temperature, Normalized

(V_CC=V_GS=5V)

FAN2108 • Rev. 1.0.3

www.fairchildsemi.com

Application Circuit

VIN

VCC

+5V

8-20 V_IN

1.0u

X5R

10K

200K

PGOOD

3.3n

3 x 4.7u

X7R

V_OUT

RAMP

2.49K

COMP

2.49K

4.7n

56p

Inter-Technical

SC7232-2R2M

BOOT

ILIM

4.7n

0.1u

V_OUT

200K

3.3n

2.2u *

R(T)

1.5

30.1K

2.00K

4 x 22u

X5R

AGND

PGND

390p

Figure 10. Application Circuit: 1.8 V_OUT, 500 KHz

Typical Performance Characteristics

Typical operating characteristics using the circuit shown in Figure 10. V_IN=12 V, V_CC=5 V, unless otherwise specified.

Efficiency @ Vo=1.8V, fsw=500KHz, Ta=25⁰C

Efficiency @ Vo=3.3V, fsw=300KHz, Ta=25⁰C

100

Vin=5V

Vin=8V

Vin=10V

Vin=12V

Vin=14V

Vin=20V

Vin=12V

Vin=16V

Vin=20V

Vin=24V

Load Current (A)

Figure 11. 1.8 V_OUTEfficiency Over V_INvs. Load

Figure 12. 3.3 V_OUTEfficiency Over V_INvs. Load

Efficiency@ Vin=12V, Vo=1.8V

Load Regulation @ Vo=0.8V, 500kHz, 25°C

0.8012

Vin=8V

0.801

Vin=12V

0.8008

Vin=16V

0.8006

0.8004

0.8002

0.8

Vin=20V

Vin=24V

300KHz

500KHz

600KHz

0.7998

0.7996

0.7994

0.7992

Load Current (A)

Figure 13. 1.8 V_OUTEfficiency Over Frequency

vs. Load

Figure 14. 0.8 V_OUTLoad Regulation Over V_IN

vs. Load

FAN2108 • Rev. 1.0.3

www.fairchildsemi.com

Typical Performance Characteristics (Continued)

Typical operating characteristics using the circuit shown in Figure 10. V_IN=12 V, V_CC=5 V, unless otherwise specified.

V_OUT

PGOOD

Figure 15. Startup, 3 A Load

Figure 16. Startup with 1 V Pre-Bias on V_OUT

V_OUT

PGOOD

Figure 17. Shutdown, 1 A Load

Figure 18. Restart on Fault

HS and LS MOSFET Temperature

V_OUT

LSFET@ 20Vin

LSFET@ 12Vin

HSFET@ 20Vin

HSFET@ 12Vin

I_OUT

Load Current (A)

Figure 20. MOSFET Temperature – Still Air at Room

Temperature

Figure 19. Transient Response, 2-8 A Load

FAN2108 • Rev. 1.0.3

www.fairchildsemi.com

Circuit Description

Initialization

Soft-Start

Once V_CCexceeds the UVLO threshold and EN is HIGH,

the IC checks for an open or shorted FB pin before

releasing the internal soft-start ramp (SS).

Once internal SS ramp has charged to 0.8 V (T0.8), the

output voltage is in regulation. Until SS ramp reaches

1.0 V (T1.0), the fault latch is inhibited.

If R1 is open (Figure 1), the error amplifier output

(COMP) is forced LOW and no pulses are generated.

After the SS ramp times out (T1.0), an under-voltage

latched fault occurs.

To avoid skipping the soft-start cycle, it is necessary to

apply V_INbefore V_CCreaches its UVLO threshold.

Soft-start time is a function of oscillator frequency.

If the parallel combination of R1 and R_BIASis ≤ 1 KΩ, the

internal SS ramp is not released and the regulator does

not start.

1.35V

2400 CLKs

0.8V

Bias Supply

The FAN2108 requires a 5 V supply rail to bias the IC

and provide gate-drive energy. Connect a ≥ 1.0 µf X5R

or X7R decoupling capacitor between VCC and PGND.

Fault

Latch

Enable

1.0V

0.8V

Since V_CCis used to drive the internal MOSFET gates,

supply current is frequency and voltage dependent.

Approximate V_CCcurrent (I_CC) is calculated by:

V_CC− 5

227

3200 CLKs

4000 CLKs

I_CC

= 4.58 + [(

+ 0.013)•(f −128)]

(1)

(mA)

T0.8

where frequency (f) is expressed in KHz.

Enable

T1.0

Figure 21. Soft-Start Timing Diagram

FAN2108 has an internal pull-up to enable pin so that

the IC is enabled once V_CCis applied. Connecting a

small capacitor across EN and AGND delays the rate of

voltage rise on the EN pin. EN pin also serves for the

restart whenever a fault occurs (refer to the Auto-Restart

section). For applications where sequencing is required,

FAN2108 can be enabled (after the V_CCcomes up) with

external control, as shown in Figure 20.

The regulator does not allow the low-side MOSFET to

operate in full synchronous rectification mode until

internal SS ramp reaches 95% of V_REF(~0.76 V). This

helps the regulator to start on a pre-biased output and

ensures that inductor current does not "ratchet" up

during the soft-start cycle.

V_CCUVLO or toggling the EN pin discharges the SS and

resets the IC.

Setting the Output Voltage

The output voltage of the regulator can be set from

0.8 V to 80% of V_INby an external resistor divider (R1

and R_BIASin Figure 1).

The internal reference is 0.8 V with 650 nA, sourced

from the FB pin to ensure that, if the pin is open, the

regulator does not start.

Figure 20. Enabling with External Control

Setting the Frequency

The external resistor divider is calculated using:

Oscillator frequency is determined by an external resistor,

R_T, connected between the R(T) pin and AGND.

Resistance is calculated by:

V_OUT− 0.8V

0.8V

+ 650nA

(3)

R_BIAS

Connect R_BIASbetween FB and AGND.

(10⁶/ f ) −135

(2)

R_T

(KΩ)

where R_Tis in KΩ and frequency (f) is in KHz.

The regulator cannot start if R_Tis left open.

FAN2108 • Rev. 1.0.3

www.fairchildsemi.com

R_ILIM= V_RILIM/ 10µA

(7)

Calculating the Inductor Value

The voltage V_RILIMis made up of two components, V_BOT

(which relates to the current through the low-side

MOSFET) and V_RMPEAK(which relates to the peak

current through the inductor). Combining those two

voltage terms results in:

Typically the inductor is set for a ripple current (ΔI_L) of

10% to 35% of the maximum DC load. Regulators

requiring fast transient response use a value on the high

side of this range; while regulators that require very low

output ripple and/or use high-ESR capacitors restrict

allowable ripple current.

R_ILIM= (V_BOT+ V_RMPEAK)/ 10µA

(8)

V_OUT

V_OUT• (1-

ΔIL • f

)

(4)

V_IN

R_ILIM= {0.96 + (I_LOAD* R_DSON*K_T*8)} +

{D*(V_IN– 1.8)/(f_SW*0.03*10^-3 R_RAMP)}/10µA

(9)

L =

where:

where f is the oscillator frequency.

_BOT= 0.96 + (I_LOAD* R_DSON*K_T*8);

V_RMPEAK= D*(V_IN– 1.8)/(f_SW*0.03*10^-3*R_RAMP);

_LOAD= the desired maximum load current;

Setting the Ramp Resistor Value

The internal ramp voltage excursion (∆V_RAMP) during t_ON

should be set to 0.6 V at nominal operating point. R_RAMP

is approximately:

R_DSON= the nominal R_DSONof the low-side MOSFET;

(V_IN−1.8)•V_OUT

18x10⁻⁶•V_IN• f

R_RAMP(KΩ)

− 2

(5)

K_T= the normalized temperature coefficient for the

low-side MOSFET (on datasheet graph);

where frequency (f) is expressed in KHz.

D = V_OUT/V_INduty cycle;

f_SW= Clock frequency in kHz; and

Setting the Current Limit

_RAMP= chosen ramp resistor value in kΩ.

The current limit system involves two comparators. The

MAX I_LIMITcomparator is used with a V_ILIMfixed-voltage

reference and represents the maximum current limit

allowable. This reference voltage is temperature

compensated to reflect the R_DSONvariation of the low-

side MOSFET. The ADJUST I_LIMITcomparator is used

where the current limit needs to be set lower than the

After 16 consecutive, pulse-by-pulse, current-limit

cycles, the fault latch is set and the regulator shuts

down. Cycling V_CCor EN restores operation after a

normal soft-start cycle (refer to the Auto-Restart

section).

V_ILIMfixed reference. The 10 µA current source does not

The over-current protection fault latch is active during

track the R_DSONchanges over temperature, so change is

added into the equations for calculating the ADJUST

I_LIMITcomparator reference voltage, as is shown below.

Figure 22 shows a simplified schematic of the over-

current system.

the soft-start cycle. Use 1% resistor for R_ILIM

Loop Compensation

The loop is compensated using a feedback network

around the error amplifier. Figure 23 shows a complete

type-3 compensation network. For type-2 compensation,

eliminate R3 and C3.

PWM

COMP

RAMP

VERR

PWM

MAX

ILIMIT

V_CC

VILIM

10µA

ADJUST

ILIMIT

ILIMTRIP

ILIM

RILIM

Figure 23. Compensation Network

Figure 22. Current-Limit System Schematic

Since the FAN2108 employs summing current-mode

architecture, type-2 compensation can be used for many

applications. For applications that require wide loop

bandwidth and/or use very low-ESR output capacitors,

type-3 compensation may be required.

Since the I_LIMvoltage is set by a 10 µA current source

into the R_ILIMresistor, the basic equation for setting the

reference voltage is:

V_RILIM= 10µA*R_ILIM

(6)

To calculate R_ILIM

FAN2108 • Rev. 1.0.3

www.fairchildsemi.com

If auto-restart is not desired, tie the EN pin to the VCC

pin or pull it HIGH after V_CCcomes up with a logic gate

to keep the 1 µA current sink from discharging EN to

1.1 V. Figure 24 shows one method to pull up EN to V_CC

for a latch configuration.

Protection

The converter output is monitored and protected against

extreme overload, short-circuit, over-voltage, under-

voltage, and over-temperature conditions.

An internal fault latch is set for any fault intended to shut

down the IC. When the fault latch is set, the IC

discharges V_OUTby enhancing the low-side MOSFET

until FB<0.25 V. The MOSFET is not turned on again

unless FB>0.5 V. This behavior discharges the output

without causing undershoot (negative output voltage).

VCC

100K

FAN2108

Under-Voltage Shutdown

If voltage on the FB pin remains below the under-voltage

threshold for 16 consecutive clock cycles, the fault latch

is set and the converter shuts down. This protection is

not active until the internal SS ramp reaches 1.0 V

during soft-start.

3.3n

Figure 24. Enable Control with Latch Option

Over-Voltage Protection / Shutdown

If voltage on the FB pin exceeds the over-voltage

threshold for two consecutive clock cycles, the fault latch

is set and shutdown occurs.

Over-Temperature Protection (OTP)

The chip incorporates an over-temperature protection

circuit that sets the fault latch when a die temperature of

about 150°C is reached. The IC restarts when the die

temperature falls below 125°C.

A shorted high-side MOSFET condition is detected

when SW voltage exceeds ~0.7 V while the low-side

MOSFET is fully enhanced. The fault latch is set

immediately upon detection.

Power-Good (PGOOD) Signal

The two fault protection circuits above are active all the

time, including during soft-start.

PGOOD is an open-drain output that asserts LOW when

V_OUTis out of regulation, as measured at the FB pin.

Thresholds are specified in the Electrical Specifications

section. PGOOD does not assert HIGH until the fault

latch is enabled (T1.0).

Auto-Restart

After a fault, EN pin is discharged by a 1 µA current sink

to a 1.1 V threshold before the internal 800 KΩ pull-up is

restored. A new soft-start cycle begins when EN

charges above 1.35 V.

PCB Layout

Depending on the external circuit, the FAN2108 can be

configured to remain latched-off or to automatically

restart after a fault.

Table 1. Fault / Restart Configurations

EN Pin

Controller / Restart State

Pull to GND

OFF (Disabled)

Pull-up to V_CCwith No Restart – Latched OFF(After

100K

V_CCComes Up)

Open

Immediate Restart After Fault

New Soft-Start Cycle After:

t_DELAY(ms)=3.9 • C(nf)

Cap. to GND

With EN is left open, restart is immediate.

Figure 25. Recommended PCB Layout

FAN2108 • Rev. 1.0.3

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