FAN21SV04EMPX_技术文档

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August 2014

FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input

Integrated Synchronous Buck Regulator

Features

Description

.

Single-Supply Operation with 4 A Output Current

The FAN21SV04 TinyBuck™ is a highly efficient,

small-footprint,

programmable-frequency,

4 A,

Wide Input Range with Dual Supply: 3.0 V to 24 V

Wide Output Voltage Range: 0.8 V to 80% V_IN

Over 94% Peak Efficiency

integrated synchronous buck regulator.

FAN21SV04 contains both synchronous MOSFETs

and a controller/driver with optimized interconnects in

one package, which enables designers to solve high-

current requirements in a small area with minimal

external components, thereby reducing cost. On-

board internal 5 V regulator enables single-supply

operation for input voltages >6.5 V.

1% Reference Accuracy Over Temperature

Fully Synchronous Operation with Integrated

Schottky Diode on Low-Side MOSFET Boosts

Efficiency

.

Single Supply Device for V_IN> 6.5 V – 24 V

The FAN21SV04 can be configured to drive multiple

slave devices OR synchronize to an external system

clock. In slave mode, FAN21SV04 may be set up to be

free-running in the absence of a master clock signal.

Programmable Frequency Operation (200-

600 KHz)

.

Synchronizable to External Clock with

Master/Slave Provisions

External compensation, programmable switching

frequency, and current-limit features allow for design

optimization and flexibility. High-frequency operation

allows for all-ceramic solutions.

.

Power-Good Signal

Accepts Ceramic Capacitors on Output

External Compensation for Flexible Design

Starts on Pre-Bias Outputs

Fairchild’s advanced BiCMOS power process,

combined with low-R_DS(ON)internal MOSFETs and a

thermally efficient MLP package, provide the ability

Integrated Bootstrap Diode

to dissipate high power in

a small package.

Programmable Over-Current Protection

Integration helps minimize critical inductances,

making layout simpler and more efficient compared

to discrete solutions.

Under-Voltage, Over-Voltage, and Thermal-

Shutdown Protections

.

5 x 6 mm, 25-Pin, 3-Pad MLP Package

Output over-voltage, under-voltage, over-current, and

thermal-shutdown protections help protect the device

from damage during fault conditions. FAN21SV04

prevents pre-biased output discharge during startup in

point-of-load applications.

Applications

.

Servers & Telecom

Graphics Cards & Displays

Computing Systems

Related Resources

.

TinyCalc™ Calculator Design Tool

Set-Top Boxes & Game Consoles

Point-of-Load Regulation

.

AN-8022 — TinyCalc™ Calculator User Guide

Ordering Information

Operating

Packing

Part Number

Temperature Range

Package

Method

FAN21SV04MPX

FAN21SV04EMPX

-10°C to 85°C

-40°C to 85°C

Molded Leadless Package (MLP) 5 x 6 mm

Tape and Reel

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

Typical Application Diagram

IN

VIN

Boot

Diode

C_HF

C_IN

5V_Reg

BOOT

SW

C4

R5

Q1

Q2

C_BOOT

VIN_Reg

OUT

C5

L

C_OUT

RAMP

PWM

+

DRIVER

Power

Good

R_RAMP

PGND

CLK

FB

POWER

MOSFETS

EN

ILIM

R_T

Enable

R_ILIM

R1

R_T

R3

C3

AGND

COMP

C1

R_BIAS

C2

R2

Figure 1. Typical Application as Master at V_IN=6.5 V to 24 V

Block Diagram

VIN_Reg

Reg

5V

BOOT

V^IN

Boot

Diode

5V_Reg

ILIM

Current Limit

Comparator

IILIM

Int ref

COMP

FB

CBOOT

Error

Amplifier

R

S

Q

PWM

Comparator

Gate

Drive

Circuit

VOUT

SW

L

SS

VREF

C^OUT

CLK

Summing

Amplifier

AGND

PGND

OSC

RAMP

GEN

Current

Sense

EN

RAMP

Figure 2. Block Diagram

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

2

Pin Configuration

Figure 3. MLP 5 x 6 mm Pin Configuration (Bottom View)

Pad / Pin Definitions

Pad / Pin

P1, 6-12

P2, 3-5

Name Description

SW

VIN

Switching Node. Junction of high-side and low-side MOSFETs.

Power Conversion Input Voltage. Connect to the main input power source.

Power Ground. Power return and Q2 source.

P3, 21-23

PGND

High-Side Drive BOOT Voltage. Connect through capacitor (C_BOOT) to SW. The IC has an

internal synchronous bootstrap diode to recharge the capacitor on this pin to 5 V_Reg when

SW is LOW.

1

2

BOOT

VIN_Reg

PGOOD

Regulator Input Voltage. Input voltage to the internal regulator. Connect to input voltage

>6.5 V with 10 Ω resistor and a 1 µF bypass capacitor at the pin (see Figure 10).

Power-Good. An open-drain output that pulls LOW when the voltage on the FB pin is

outside the specified limits. PGOOD does not assert HIGH until the fault latch is enabled

(see Figure 31).

13

ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the

regulator after a latched-fault condition. This input has an internal pull-up. When a latched

fault occurs, EN is discharged by a current sink.

14

15

EN

5V Regulator Output. Internal regulator output that provides power for the IC’s logic and

analog circuitry. This pin should be connected to AGND through a >2.2 µf X5R/X7R

capacitor.

5V_Reg

Analog Ground. The signal ground for the IC. All internal control voltages are referred to

this pin. Tie this pin to the ground island/plane through the lowest impedance connection.

16

17

AGND

ILIM

Current Limit. A resistor (R_ILIM) from this pin to AGND can be used to program the current-

limit trip threshold lower than the internal default setting.

Switching Frequency and Master/Slave Set. Connecting a resistor (R_T) to AGND sets the

switching frequency and configures the CLK pin as an output (master). Tying this pin to

5 V_Reg through a resistor configures the CLK signal as an input (slave) and establishes

the free-running switching frequency.

18

R_T

19

20

FB

Output Voltage Feedback. Connect through a resistor divider to the output voltage.

Compensation. Error amplifier output. Connect the external compensation network

between this pin and FB.

COMP

Clock. Bi-directional signal pin, depending on master/slave configuration. When configured

as a master, this pin represents the clock output that connects directly to the slave(s) for

synchronizing with 180° phase shift.

24

25

CLK

Ramp Amplitude. A resistor (R_RAMP) connected from this pin to VIN sets the internal ramp

amplitude and also provides voltage feedforward functionality.

RAMP

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Parameter

Conditions

Min.

Max.

28

Units

VIN, VIN_Reg to AGND AGND=PGND

V

5V_Reg to AGND

BOOT to PGND

BOOT to SW

AGND=PGND

6

35

-0.5

-5

6.0

24.0

30

Continuous

SW to PGND

All other pins

V

Transient (t < 20 ns, f < 600 KHz)

-0.3

6.0

Human Body Model,

JESD22-A114

1.5

2.5

Electrostatic Discharge

Protection Level

ESD

kV

Charged Device Model,

JESD22-C101

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Conditions

Min.

200

3.0

Typ.

Max Units

f_SW

Switching Frequency

500

600

24.0

+85

KHz

VIN to PGND

V_IN,

VIN_Reg

Supply Voltage for Power and Bias

V

VIN_Reg to AGND

FAN21SV04MPX

FAN21SV04EMPX

6.5

-10

T_A

T_J

Ambient Temperature

Junction Temperature

°C

-40

+85

+125

Thermal Information

Symbol

Parameter

Min.

Typ.

Max.

+150

+300

Units

°C

T_STG

T_L

Storage Temperature

-65

Lead Soldering Temperature, 30 Seconds

Thermal Resistance: Junction-to-Case

°C

P1 (Q2)

P2 (Q1)

P3

4

7

°C/W

θ_JC

4

Thermal Resistance: Junction-to-Mounting Surface⁽¹⁾

Total Power Dissipation in the package, T_A=25°C⁽¹⁾

35

°C/W

W

θ_J-PCB

P_D

2.8

Note:

1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 38. Actual results

are dependent upon mounting method and surface related to the design.

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

4

Electrical Characteristics

Recommended operating conditions and using the circuit shown in Figure 1, with V_IN, VIN_Reg=12 V, unless

otherwise noted.

Parameter

Conditions

Min.

Typ.

Max. Units

Power Supplies

Operating Current

(VIN+VIN_Reg)

V_IN=12 V, 5V_Reg Open, CLK Open,

22

30

mA

f

_SW=500 KHz, No Load

EN=High, 5 V_Reg Open, CLK Open,

_SW=500 KHz

VIN_Reg Operating Current

11

4

f

VIN_Reg Quiescent Current

VIN_Reg Standby Current

EN=High, FB=0.9 V

EN=0, V_IN=12 V

5

1

mA

Internal V_CCRegulator, No Load,

6.5 V<VIN_Reg<24 V

5V_Reg Output Voltage

5V_Reg Max. Current Load

VIN_Reg UVLO Threshold

Reference

4.7

5.0

5.6

5.3

V

VIN_Reg=12 V

5

6.3

5

mA

V

Rising V_IN, V_IN=VIN_Reg

Falling V_IN, V_IN=VIN_Reg

V

Reference Voltage measured

at FB (See Figure 4 for

Temperature Coefficient)

FAN21SV04MPX, T_A=25°C

FAN21SV04EMPX, T_A=25°C

794

795

800

806

805

mV

Oscillator

255

540

300

600

345

660

R_T=50 kΩ to GND (Master Mode)

R_T=24 kΩ to GND (Master Mode)

R_T=24 kΩ to 50 kΩ to 5 V_Reg

(Slave Mode)

Frequency

KHz

%

Frequency in Slave Mode

Compared to Master Mode

Minimum On Time ⁽²⁾

-15

+15

40

80

65

85

ns

%

Duty Cycle

V_IN=6.5 V, f_SW=600 KHz

Ramp Amplitude,

Peak–to-Peak⁽²⁾

Minimum Off Time ⁽²⁾

V_IN=16 V, 1.8 V_OUT, R_T=30 kΩ,

R_RAMP=200 kΩ

0.5

V

100

150

ns

Synchronization

CLK Output Pulse Width

CLK Output Sink Current

CLK Output Source Current

CLK Input Pulse Width

CLK Input Source Current

CLK Input Threshold, Rising

Soft-Start

Master (R_Tto GND)

Master, V_CLK=0.4 V

Master, V_CLK=2 V

Slave: V_CLK> 2 V

Slave: V_CLK=1 V

Slave

70

85

100

0.35

-2.0

ns

mA

ns

0.25

-2.5

50

-230

1.73

-200

1.83

-170

1.93

µA

V

V_OUTto Regulation (T_0.8

)

2.5

3.1

ms

Frequency=500 KHz

Fault Enable/SSOK (T_1.0

Error Amplifier

DC Gain ⁽²⁾

Gain Bandwidth Product⁽²⁾

Output Voltage Swing (V_COMP

Output Current, Sourcing

Output Current, Sinking

FB Bias Current

)

80

12

85

15

dB

MHz

V

VIN_Reg > 6.5 V

)

0.4

1.5

0.8

-850

4.0

2.5

5V_Reg=5 V, V_COMP=2.2 V

5V_Reg=5 V, V_COMP=1.2 V

V_FB=0.8 V, T_A=25°C

2.2

1.2

mA

nA

1.5

-650

-450

Note:

2. Specifications guaranteed by design and characterization; not production tested.

www.fairchildsemi.com

FAN21SV04 • Rev. 1.0.4

5

Electrical Characteristics (Continued)

Recommended operating conditions using the circuit shown in Figure 1 with V_IN, V_{IN_Reg}=12 V, unless otherwise

noted.

Parameter

Conditions

Min.

Typ.

Max. Units

Control Functions

EN Threshold, Rising

EN Hysteresis

1.35

250

800

1

2.00

V

mV

KΩ

µA

KΩ

EN Pull-Up Resistance

EN Discharge Current

FB OK Drive Resistance

VIN_Reg >6.5 V

Auto-Restart Mode, VIN_Reg>6.5 V

800

-11.0

+10.0

1000

-8.0

+13.5

0.4

FB < V_REF, 2 Consecutive Clock Cycles⁽³⁾

FB > V_REF, 2 Consecutive Clock Cycles⁽³⁾

I_OUT< 2 mA

-14.0

+7.0

PGOOD Low Threshold

%V_REF

PGOOD Low Voltage

V

PGOOD Leakage Current

Protection and Shutdown

V_PGOOD=5 V

0.2

6.5

1.0

µA

R_ILIMopen, f_SW=500 KHz, V_OUT=1.8 V,

Current Limit

5.5

-11

7.5

-9

A

R_RAMP=200 kΩ, 16 Consecutive Clock

Cycles⁽³⁾

I_LIMCurrent

VIN_Reg > 6.5 V, T_A=25°C

-10

+155

+30

115

73

µA

°C

Over-Temperature Shutdown

Over-Temperature Hysteresis

Over-Voltage Threshold

Under-Voltage Shutdown

Fault-Discharge Threshold

Fault-Discharge Hysteresis

Note:

Internal Temperature

°C

2 Consecutive Clock Cycles⁽³⁾

16 Consecutive Clock Cycles⁽³⁾

Measured at FB pin

110

68

120

78

%V_OUT

mV

250

Measured at FB pin (V_FB~500 mV)

mV

3. Delay times are not tested in production. Guaranteed by design.

www.fairchildsemi.com

FAN21SV04 • Rev. 1.0.4

6

Typical Characteristics

V_IN=12V, V_CC=5V, T_A=25°C, unless otherwise specified.

1.010

1.005

1.000

0.995

0.990

1.20

1.10

1.00

0.90

0.80

-50

0

50

100

150

-50

0

50

100

150

Temperature (^oC)

Figure 4. Reference Voltage (V_FB) vs. Temperature, Figure 5. Reference Bias Current (I_FB) vs. Temperature,

Normalized

1500

1200

900

600

300

0

1.02

1.01

1.00

0.99

0.98

600KHz

300KHz

-50

0

50

100

150

0

20

40

60

80

100

120

140

Temperature (^oC)

R_T(K )

Ω

Figure 6. Frequency vs. R_T(Master)

Figure 7. Frequency vs. Temperature, Normalized

1.04

1.02

1.00

0.98

0.96

1.60

1.40

1.20

1.00

0.80

0.60

Q1 ~0.32 %/^oC

Q2 ~0.35 %/^oC

-50

0

50

100

150

-50

0

50

100

150

Temperature (^oC)

Figure 8. R_DSvs. Temperature, Normalized

(5 V_Reg=V_GS=5 V)

Figure 9. ILIM Current (I_ILIM) vs. Temperature,

Normalized

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

7

Application Circuit

FAN21SV04

Figure 10. Single-Supply Application Circuit: 1.8 V_OUT, 500 KHz, Master, 8 V – 20 V Input

FAN21SV04

Figure 11. Single -Supply Application Circuit: 1.2 V_OUT, 500 KHz, Master 8 V – 20 V Input

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

8

Typical Performance Characteristics

Typical operating characteristics using the Figure 10 circuit; V_IN=12 V, V_CC=5 V, T_A=25°C, unless otherwise specified.

95

3.3V Eff 8-20V 500kHz

95

1.8V_Eff 8-20V_500kHz

90

85

8Vin

12Vin

80

8V

16Vin

12V

20Vin

75

70

75

70

16V

20V

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

Load(A)

Figure 12. 1.8 V_OUTEfficiency Over V_INvs. Load

Figure 13. 3.3 V_OUTEfficiency, 500 KHz⁽⁴⁾

95

3.3V_Eff 8-20V_300kHz

1.8V_Eff 8-20V_300kHz

95

90

85

80

75

70

90

85

8V

80

75

70

12V

16V

20V

12V

16V

20V

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

Load(A)

Figure 14. 1.8 V_OUTEfficiency, 300 KHz⁽⁴⁾

Figure 15. 3.3 V_OUTEfficiency, 300 KHz⁽⁴⁾

95

1.2V_Eff 8-20V_500kHz

95

90

85

80

75

70

90

85

80

75

70

5V_Eff 8-20V_300kHz

8Vin

12Vin

16Vin

20Vin

8V

12V

16V

20V

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

Load(A)

Load (A)

Figure 16. 1.2 V_OUTEfficiency, 500 KHz (Figure 11)

Note:

Figure 17. 5 V_OUTEfficiency, 300 KHz⁽⁴⁾

4. Circuit values for this configuration change in Figure 10.

www.fairchildsemi.com

FAN21SV04 • Rev. 1.0.4

9

Typical Performance Characteristics (Continued)

Typical operating characteristics using the Figure 10 circuit; V_IN=12 V, V_CC=5 V, T_A=25°C, unless otherwise specified.

0.10

0.15

Line Regulation

Load Regulation

0.08

0.05

No load

0.1

0.05

0

0.5A Load

12V

16V

0.03

0.00

-0.03

-0.05

-0.08

-0.10

-0.05

-0.1

-0.15

0

0.5

1

1.5

2

2.5

3

3.5

4

0

5

10

15

20

25

Load(A)

Input Voltage (V)

Figure 18. 1.8 V_OUTLine Regulation

Figure 19. 1.8 V_OUTLoad Regulation

70

60

50

40

30

20

10

0

70

Peak Case Tempr over Mosfet Location

@Room Tempr - 3.3V Output, 500kHz

60

50

40

30

20

10

0

Peak Case Tempr over Mosfet Location

@Room Tempr - 5V Output, 300kHz

12V_HS

12V_LS

24V_HS

24V_LS

12V_HS

12V_LS

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

Load(A)

Figure 20. Peak MOSFET Temperatures 3.3 V Output, Figure 21. Peak Case Temperature Over MOSFET

12 V and 24 V Input (500KHz)⁽⁵⁾

Locations 5 V Output (300 KHz)

95

90

85

80

75

70

Recommended FAN21SV04 Safe Operating Area curves for 70 Deg

Temperature rise VIN = 20V, Natural Convection.

1.8V_Eff 12V Input

6

5

4

3

2

1

0

300kHz

400kHz

500kHz

600kHz

300KHz

500KHz

600Khz

0

2

4

6

8

10

12

14

0

0.5

1

1.5

2

2.5

3

3.5

4

Output Voltage (Volts)

Load(A)

Figure 23. Typical Output Operating Area Based on

Thermal Limitations

Figure 22. 1.8 V_OUTEfficiency Over f_SW

Note:

5. Circuit values for this configuration change in Figure 10.

www.fairchildsemi.com

FAN21SV04 • Rev. 1.0.4

10

Typical Performance Characteristics (Continued)

Typical operating characteristics using the Figure 10 circuit. V_IN=12 V unless otherwise specified.

V_OUT, 1V/div

V_OUT, 100mv/div

EN, 1V/div

CLK, 5V/div

I

_OUT, 2A/div

PGOOD, 5V/div

Figure 24. CLK and V_OUTat Startup

Figure 25. Transient Response, 2-4 A Load

V_OUT, 1V/div

EN, 2V/div

SW, 10V/div

Figure 26. Startup on Pre-Bias

Figure 27. Restart on Fault

CLK, 5V/div

V_OUT, 1V/div

SW, 5V/div

CLK, 5V/div

EN, 5V/div

PGOOD, 5V/div

Figure 29.

Slave (500 KHz Free-Run to 600 KHz

Synchronization)

Figure 28. Shutdown, 1 A Load

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

11

Circuit Operation

PWM Generation

Internal Regulator

Refer to Figure 2 for the PWM control mechanism.

FAN21SV04 uses the summing-mode method of control

to generate the PWM pulses. An amplified current-

sense signal is summed with an internally generated

ramp and the combined signal is compared with the

output of the error amplifier to generate the pulse width

to drive the high-side MOSFET. Sensed current from the

previous cycle is used to modulate the output of the

summing block. The output of the summing block is also

compared against a voltage threshold set by the R_LIM

resistor to limit the inductor current on a cycle-by-cycle

basis. R_RAMPresistor helps set the charging current for

the internal ramp and provides input voltage feed-

forward function. The controller facilitates external

compensation for enhanced flexibility.

FAN21SV04 facilitates single-supply operation for input

voltages >6.5 V. At startup, the output of the internal

regulator tracks the input voltage and comes into

regulation (5 V) when VIN_Reg exceeds the UVLO

threshold. The EN pin is released at the same time. The

output voltage of the internal regulator (5 V_Reg) is set

to 5 V. The internal regulator supplies power to all the

control circuits including the drivers.

For applications with V_IN<6.5 V, FAN21SV04 can be used

if VIN_Reg is provided with a separate low-power source

>6.5 V. VIN_Reg supply should come up after V_INduring

dual-supply operation. The VIN_Reg pin should always be

decoupled with at least a 10 Ω resistor and a 1 µF

ceramic capacitor (see Figure 10, Figure 11).

Since 5 V_Reg is used to drive the internal MOSFET

gates, high peak currents are present on the 5 V_Reg

pin. Connect a >2.2 µf X5R or X7R decoupling capacitor

between the 5 V_Reg pin and AGND. For V_IN>20 V

operation, use a 3.3 Ω resistor in series with the boot

capacitor to reduce noise into the regulator.

Initialization

Once VIN_Reg voltage exceeds the UVLO threshold

and EN is HIGH, the IC checks for a shorted FB pin

before releasing the internal soft-start ramp (SS).

If the parallel combination of R1 and R_BIASis ≤ 1 kΩ, the

internal SS ramp is not released and the regulator does

not start.

In addition to supplying power for the control circuits

internally, 5 V_Reg output can be used as a reference

voltage for other applications requiring low noise

reference voltage. 5 V_Reg is capable of sourcing up to

5 mA of output current.

Enable

FAN21SV04 has an internal pull-up to the enable (EN)

pin so that the IC is enabled once VIN_Reg exceeds the

UVLO threshold. Connecting a small capacitor across

EN and AGND delays the rate of voltage rise on the EN

pin. The EN pin also serves for the restart whenever a

fault occurs (refer to the Auto-Restart section). If the

regulator is enabled externally, the external EN signal

should go HIGH only after 5 V_Reg is established. For

applications where such sequencing is required,

FAN21SV04 can be enabled (after the V_CCcomes up)

with external control, as shown in Figure 30.

When EN is pulled LOW externally, 5 V_Reg output is

still present, but the IC is in standby mode with no

switching.

Soft-Start

FAN21SV04 uses an internal digital soft-start circuit to

slowly ramp up the output voltage and limit inrush

current during startup. When 5 V_Reg is in regulation

and EN is HIGH, the circuit releases SS and enables the

PWM regulator. Soft-start time is a function of the

switching frequency (number of clock cycles).

If auto-restart is not desired, tie the EN pin HIGH with a

logic gate to keep the 1 µA current sink from discharging

EN to 1.1 V. Figure 32 shows one method to pull up EN

to V_CCfor a latch configuration.

Once internal SS ramp has charged to 0.8 V (T0.8), the

output voltage is in regulation. Until SS ramp reaches

1.0 V (T1.0), only the over-current-protection circuit is

active during soft-start and all other output protections

are inhibited.

In dual-supply operation mode, it is necessary to apply

VIN before VIN_Reg reaches its UVLO threshold to

avoid skipping the soft-start cycle.

VIN_Reg UVLO or toggling the EN pin discharges the

SS and resets the IC.

Figure 30. Enabling with External Control

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

12

Over-Temperature Protection

The chip incorporates an over-temperature protection

circuit that sets the fault latch when a die temperature of

about 155°C is reached. The IC is allowed to restart

when the die temperature falls below 125°C.

Auto-Restart

After a fault, the EN pin is discharged with 1 µA current

pull-down to a 1.1 V threshold before the internal 800 kΩ

pull-up is restored. A new soft-start cycle begins when

EN charges above 1.35 V.

Depending on the external circuit, the FAN21SV04 can

be configured to remain latched off or automatically

restart after a fault, as listed in Table 1.

Table 1. Fault / Restart Configurations

EN Pin

Controller / Restart State

Pull to GND

OFF (Disabled)

Connected to

5V_Reg with

100KΩ

No Restart – Latched OFF

Open

Immediate Restart After Fault

New Soft-Start Cycle After EN is

HIGH (Auto Restart Mode)

Cap to GND

Figure 31. Typical Soft-Start Timing Diagram

With EN left open, restart is immediate.

If auto-restart is not desired, tie the EN pin HIGH with a

logic gate to keep the 1 µA current sink from discharging

EN to 1.1 V. Figure 32 shows one method to pull up EN

to V_CCfor a latch configuration.

Startup on Pre-Bias

The regulator does not allow the low-side MOSFET to

operate in full synchronous mode until SS reaches 95%

of V_REF(~0.76 V). This enables the regulator to startup

on a pre-biased output and ensures that output is not

discharged during the soft-start cycle.

Protections

The converter output is monitored and protected against

extreme overload, short-circuit, over-voltage, and under-

voltage conditions.

Under-Voltage Protection

If FB remains below the under-voltage threshold for 16

consecutive clock cycles, the fault latch is set and the

converter shuts down. This protection is not active until

the internal SS ramp reaches 1.0 V during soft-start.

Figure 32. Enable Control with Latch Option

Power Good (PGOOD) Signal

PGOOD is an open-drain output that asserts LOW when

V_OUTis out of regulation, as measured at the FB pin.

The thresholds are specified in the Electrical

Specifications section. PGOOD does not assert HIGH

until soft start is complete (T1.0) (see Figure 31).

Over-Voltage Protection

If FB exceeds 115% • V_REFfor two consecutive clock

cycles, the fault latch is set and shutdown occurs.

A shorted high-side MOSFET condition is detected

when SW voltage exceeds ~0.7 V while the low-side

MOSFET is fully enhanced. The fault latch is set

immediately upon detection.

The OV/UV fault conditions are not allowed to set the

fault latch during soft-start. They are active only after

T1.0 (see Figure 31).

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

13

Application Information

5 V_Reg Output

The 5 V_Reg pin is the output of the internal regulator

that supplies all power to the control circuit. It is

important to keep this pin decoupled to AGND with a

>2.2 µf X5R or X7R decoupling capacitor. In addition,

for operation with V_IN>20 V, add a 3.3 Ω resistor in

series with the boot capacitor to reduce the switching

noise into the regulator.

transient response use a higher ripple-current setting

while regulator designs that require higher efficiency

keep ripple current on the low side and operate at a

lower switching frequency. The inductor value is

calculated by the following formula:

V_OUT

V_OUT• (1-

ΔIL • f

)

V

(3)

IN

L =

where f is the switching frequency.

Setting the Output Voltage

The output voltage of the regulator can be set from

0.8 V to ~80% of V_INby an external resistor divider (R1

and R_BIASin Figure 1). For output voltages >3.3 V,

output current rating may need to be de-rated depending

on the ambient temperature, power dissipated in the

package, and the PCB layout (refer to Thermal

Information table on page 4, Figure 20, Figure 21, and

Figure 23).

Setting the Ramp Resistor Value

R_RAMPresistor plays a critical role by providing charging

current to the internal ramp capacitor and also serving

as a means to provide input voltage feedforward.

R_RAMPis calculated by the following formula:

(V − 1.8) • V_OUT

IN

R_RAMP(KΩ)

=

− 2

(4)

(30.5 − 4.5 • I_OUT) • V • f •10⁻⁶

The internal reference is set to 0.8 V with 650 nA

sourced from the FB pin to ensure that the regulator

does not start if the pin is left open.

IN

where frequency (f) is expressed in KHz.

For wide input operation, first calculate R_RAMPfor the

minimum and maximum input voltage conditions and

use larger of the two values calculated.

The external resistor divider is calculated using:

V_OUT− 0.8V

0.8V

=

+ 650nA

(1)

R_BIAS

R1

In all applications, current through the R_RAMPpin must

be greater than 10 µA from the equation below for

proper operation:

Connect R_BIASbetween FB and AGND.

If R1 is open (see Figure 1), the output voltage is not

regulated and a latched fault occurs after the SS is

complete (T1.0).

V_IN−1.8

R_RAMP+ 2

≥ 10μA

(5)

If the parallel combination of R1 and R_BIASis ≤ 1 KΩ, the

internal SS ramp is not released and the regulator does

not start.

If the calculated R_RAMPvalues in Equation (4) result in a

current less than 10 µA, use the R_RAMPvalue that

satisfies Equation (5). In applications with large Input

ripple voltage, the R_RAMPresistor should be adequately

decoupled from the input voltage to minimize ripple on

the ramp pin.

Setting the Switching Frequency

Switching frequency is determined by a resistor, R_T,

connected between the R_Tpin and AGND (Master

Mode) or 5 V_Reg (Slave Mode):

Setting the Current Limit

The current limit system involves two comparators. The

MAX I_LIMITcomparator is used with a V_ILIMfixed-voltage

reference and represents the maximum current limit

allowable. This reference voltage is temperature

compensated to reflect the R_DSONvariation of the low-

side MOSFET. The ADJUST I_LIMITcomparator is used

where the current limit needs to be set lower than the

where R_Tis expressed in kΩ:

(10⁶/ f )−135

(2)

R_T

=

(KΩ)

65

where frequency (f) is expressed in KHz.

V

_ILIMfixed reference. The 10 µA current source does not

In Slave Mode, the switching frequency is about 10%

slower for the same R_T. The regulator does not start if

R_Tis open in Master Mode.

track the R_DSONchanges over temperature, so change is

added into the equations for calculating the ADJUST

I_LIMITcomparator reference voltage, as is shown below.

Figure 33 shows a simplified schematic of the over-

current system.

Calculating the Inductor Value

Typically the inductor value is chosen based on ripple

current (ΔI_L), which is chosen between 10 to 35% of the

maximum DC load. Regulator designs that require fast

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

14

PWM

COMP

complete Type-3 compensation network. Type-2

compensation eliminates R3 and C3.

RAMP

+

_

VERR

PWM

MAX

ILIMIT

+

_

V_CC

VILIM

10µA

ADJUST

ILIMIT

ILIMTRIP

+

_

ILIM

RILIM

Figure 34. Compensation Network

Figure 33. Current-Limit System Schematic

Since the FAN21SV04 employs summing current-mode

architecture, Type-2 compensation can be used for

many applications. For applications that require wide

loop bandwidth and/or use very low-ESR output

capacitors, Type-3 compensation may be required.

Since the I_LIMvoltage is set by a 10 µA current source

into the R_ILIMresistor, the basic equation for setting the

reference voltage is:

V

_RILIM= 10µA*R_ILIM

To calculate R_ILIM

R_ILIM= V_RILIM/ 10µA

(6)

R_RAMPprovides feedforward compensation for changes

in V_IN. With a fixed R_RAMPvalue, the modulator gain

increases as V_INis reduced, which can make it difficult

to compensate the loop. For low-input-voltage-range

designs (3 V to 8 V), R_RAMPand the compensation

component values are different as compared to designs

with V_INbetween 8 V and 24 V.

:

(7)

The voltage V_RILIMis made up of two components, V_BOT

(which relates to the current through the low-side

MOSFET) and V_RMPEAK(which relates to the peak

current through the inductor). Combining those two

voltage terms results in:

Master / Slave Configuration

R_ILIM= (V_BOT+ V_RMPEAK)/ 10µA

(8)

When first enabled, the IC determines if it is configured

as a master or slave for synchronization, depending on

how R_Tis connected.

R_ILIM= {0.96 + (I_LOAD* R_DSON*K_T*8)} +

{D*(V_IN– 1.8)/(f_SW*0.03*10^-3*R_RAMP)}/10µA

(9)

Table 2. Master / Slave Configuration

where:

V

_BOT= 0.96 + (I_LOAD* R_DSON*K_T*8);

V_RMPEAK= D*(V_IN– 1.8)/(f_SW*0.03*10^-3*R_RAMP);

_LOAD= the desired maximum load current;

_DSON= the nominal R_DSONof the low-side MOSFET;

R_Tto:

GND

Master / Slave

Master

CLK Pin

Output

Input

5V_Reg

Slave, free-running

I

R

Slaves free-run in the absence of an external clock

signal input when R_Tis connected to 5 V_Reg, allowing

regulation to be maintained. It is not recommended to

leave R_Topen when running in Slave Mode to avoid

noise pick up on the clock pin.

K_T= the normalized temperature coefficient for the

low-side MOSFET (on datasheet graph);

D = V_OUT/V_INduty cycle;

f

_SW= Clock frequency in kHz; and

Slave free-running frequency should be set at least 25%

lower than the incoming synchronizing pulse frequency.

R_RAMP= chosen ramp resistor value in kΩ.

Maximum

synchronizing

clock

frequency

is

recommended to be below 600 KHz.

After 16 consecutive, pulse-by-pulse, current-limit

cycles, the fault latch is set and the regulator shuts

down. Cycling V_CCor EN restores operation after a

normal soft-start cycle (refer to the Auto-Restart

section).

Synchronization

The synchronization method employed by the

FAN21SV04 also provides the following features for

maximum flexibility.

The over-current protection fault latch is active during

the soft-start cycle. Use 1% resistor for R_ILIM

.

Synchronization to an external system clock

Loop Compensation

The control loop is compensated using a feedback

network around the error amplifier. Figure 34 shows a

Multiple FAN21SV04s can be synchronized to a

single master or system clock

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

15

Since the synchronizing circuit utilizes a narrow reset

pulse, the actual phase delay is slightly more than 180^o.

.

Independently programmable phase adjustment for

one or multiple slaves

Free-running capability in the absence of system

clock or, if the master is disabled/faulted, the slaves

can continue to regulate at a lower frequency

The FAN21SV04 is not intended for use in single-output,

multi-phase regulator applications.

The FAN21SV04 master outputs an 85 ns-wide clock

(CLK) signal, delayed 180^ofrom its leading PWM edge.

This feature allows out-of-phase operation for the slaves,

thereby reducing the input capacitance requirements

when more than one converter is operating on the same

input supply. The leading SW-node edge is delayed

~40 ns from the rising PWM signal.

PCB Layout

Good PCB layout and careful attention to temperature

rise is essential for reliable operation of the regulator.

Four-layer PCB with two-ounce copper on the top and

bottom side and thermal vias connecting the layers is

recommended. Keep power traces wide and short to

minimize losses and ringing. Do not connect AGND to

PGND below the IC. Connect AGND pin to PGND at the

output OR to the PGND plane.

On a slave, synchronization is rising-edge triggered. The

CLK input pin has a 1.8 V threshold and a 200 µA

current source pull-up.

In Master Mode, the clock signals go out after power-

good signal asserts HIGH. Likewise, in Slave Mode,

synchronization to an external clock signal occurs after

the power-good signal goes HIGH. Until then, the

converter operates in free-run mode.

V_IN

SW

PGND

V_OUT

Figure 35. Synchronization Timing Diagram

Figure 38. Recommended PCB Layout

Figure 36. Slave-CLK-Input Block Diagram

One or more slaves can be connected directly to a

master or system clock to achieve a 180^°phase shift.

Figure 37. Slaves with 180^°Phase Shift

FAN21SV04 • Rev. 1.0.4

www.fairchildsemi.com

16

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1


型号：	FAN21SV04EMPX
厂家：	ONSEMI
描述：	- 4 A、24 V 单输入集成同步降压调节器调节器
文件：	总19页 (文件大小：767K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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