FAN23SV04TAMPX [ONSEMI]
4 A 同步降压调节器，实现 DDR 终止;
| 型号： | FAN23SV04TAMPX |
| 厂家： | 
ONSEMI |
| 描述： | 4 A 同步降压调节器，实现 DDR 终止 双倍数据速率 调节器 |
| 文件： | 总20页 (文件大小：1625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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September 2015
FAN23SV04TAMPX
4 A Synchronous Buck Regulator for DDR Termination
Description
Features
The FAN23SV04TA is a highly efficient, synchronous
buck regulator for use in tracking applications, such as
DDR termination rails. The VDDQ input includes an
internal 2:1 resistive voltage divider to reduce total
circuit size and component count. The regulator
operates with an input range from 7 V to 18 V and
supports up to 4 A load currents. The device can
operate from a 5 V rail (±10%) if VIN, PVIN, and PVCC
are connected together to bypass the internal linear
regulator.
.
VIN Range: 7 V to 18 V Using Internal Linear
Regulator for Bias
.
VIN Range: 4.5 V to 5.5 V with VIN/PVIN/PVCC
Connected to Bypass Internal Regulator
.
.
.
.
.
.
.
.
.
.
.
.
.
High Efficiency
Continuous Output Current: 4 A
Internal Linear Bias Regulator
Internal VDDQ Resistor Divider
Excellent Line and Load Transient Response
Output Voltage Range: 0.5 to 1.5 V
Programmable Frequency: 200 kHz to 1.5 MHz
Programmable Soft-Start
This device utilizes Fairchild’s constant on-time control
architecture to provide excellent transient response and
to maintain a relatively constant switching frequency.
Switching frequency and sourcing over-current
protection can be programmed to provide a flexible
solution for various applications.
Low Shutdown Current
Output over-current, and thermal shutdown protections
help prevent damage during fault conditions.
A
Adjustable Sourcing Current Limit
Internal Boot Diode
hysteresis feature restarts the device when normal
operating temperature is reached.
Thermal Shutdown
Halogen and Lead Free, RoHS Compliant
Applications
.
.
.
.
Bus Termination
Servers and Desktop Computers
NVDC Notebooks, Netbooks
Game Consoles
Ordering Information
Operating
Temperature Range Current
Output
Part Number
Configuration
Package
PWM Mode with
VDDQ Tracking Input
FAN23SV04TAMPX
-40 to 125°C
4 A
34-Lead, PQFN, 5.5 mm x 5.0 mm
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
Typical Application Diagrams
VIN=12V
C3
0.1µF
R7
61.9k
9
8
7
6
5
4
3
2
1
C2
10µF
R8
10k
VOUT=0.6V
10
11
12
13
NC
NC
PVIN
PVIN
SW
34
L1
1µH
33
32
31
30
FREQ
VDDQ
SS
SW
VDDQ
FAN23SV04TA
14
15
16
17
SW
C10d C10d C10b C10a
C4
R9
27.4k
R2
1k
SW
EN
NC
47µF 47µF 47µF 47µF
0.1µF
29
28
27
SW
SW
FB
C5
470pF
C7
15nF
R3
10k
18 19 20 21 22 23 24 25 26
R11
10
C9
2.2µF
C10
0.1µF
R6
4.99k
R5
1.02k
Figure 1. Typical Application with VIN = 12 V
VIN=5V
C3
0.1µF
9
8
7
6
5
4
3
2
1
C2
10µF
VOUT=0.6V
10
11
12
13
NC
NC
PVIN
PVIN
SW
34
L1
0.72µH
33
32
31
30
FREQ
VDDQ
SS
SW
VDDQ
EN
FAN23SV04TA
14
15
16
17
SW
C10d C10d C10b C10a
47µF 47µF 47µF 47µF
C4
0.1µF
R2
1k
SW
EN
NC
29
28
27
SW
SW
FB
C5
100pF
R9
26.1k
C7
15nF
R3
10k
18 19 20 21 22 23 24 25 26
R11
10
R5 1.1k
C10
0.1µF
R6
4.99k
C9
2.2µF
Figure 2. Typical Application with VIN = 5 V
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
2
Functional Block Diagram
VIN
BOOT PVIN
PVCC
Linear
Regulator
PVCC
VCC
EN
VCC
VCC UVLO
PVCC
ENABLE
VCC
Modulator
FB
SS
HS Gate
Driver
FB
Comparator
VDDQ
SW
FREQ
Control
Logic
Thermal
Shutdown
VCC
PVCC
20µA
LS Gate
Driver
ILIM
Current Limit
Comparator
AGND
PGND
Figure 3. Block Diagram
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
3
Pin Configuration
5
7
6
4
2
9
8
3
1
5
1
3
4
6
8
2
7
9
PVIN 10
PVIN 11
34 NC
33 NC
NC
34
33
10 PVIN
PVIN
(P2)
11
12
13
NC
PVIN
FREQ
32
31
SW 12
SW 13
FREQ
32
31
SW
SW
VDDQ
VDDQ
AGND
(P1)
SW
(P3)
SW 14
SW 15
SW 16
SW 17
30
29
SS
EN
SS
EN
30
29
28
27
SW
SW
SW
SW
14
15
28
27
NC
FB
16
17
NC
FB
21
20
19
18
19
20
21
22
23
24
25
26
18
25
24
23
22
26
Figure 4. Bottom View
Figure 5. Top View
Pin Definitions
Name
Pad / Pin
Description
PVIN
VIN
P2; 5-11
1
Power input for the power stage.
Power input to the linear regulator; used in the modulator for input voltage feed-forward.
Power output of the linear regulator; directly supplies power for the low-side gate driver
and boot diode. Can be connected to VIN and PVIN for operation from 5 V rail.
PVCC
25
VCC
PGND
AGND
SW
26
Power supply input for the controller.
18-21
Power ground for the low-side power MOSFET and for the low-side gate driver.
Analog ground for the analog portions of the IC and for substrate.
P1; 4, 23
P3; 2, 12-17, 22 Switching node; junction between high-and low-side MOSFETs.
Supply for high-side MOSFET gate driver. A capacitor from BOOT to SW supplies the
charge to turn on the N-channel high-side MOSFET. During the freewheeling interval
(low-side MOSFET on), the high-side capacitor is recharged by an internal diode
BOOT
3
connected to PVCC.
ILIM
FB
24
27
29
30
Current limit. A resistor between ILIM and SW sets the current-limit threshold.
Output voltage feedback to the modulator.
EN
SS
Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable.
Soft-Start input to the modulator.
External reference input to the modulator. The modulator regulates to half of the voltage
at the VDDQ pin.
VDDQ
31
On-time and frequency programming pin. Connect a resistor between FREQ and AGND
to program on-time and switching frequency.
FREQ
NC
32
28, 33-34
Leave pin open or connect to AGND.
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VPVIN
Parameter
Power Input
Condition
Referenced to PGND
Min.
Max. Unit
-0.3
-0.3
-0.3
-0.3
-1
25.0
25.0
26.0
30.0
25
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
VIN
Modulator Input
Referenced to AGND
Referenced to PVCC
VBOOT
Boot Voltage
Referenced to PVCC, <20 ns
Referenced to PGND, AGND
Referenced to PGND, AGND < 20 ns
Referenced to SW
VSW
SW Voltage to GND
-5
25
Boot to SW Voltage
Boot to PGND
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
6.0
VBOOT
Referenced to PGND
30
VPVCC
VVCC
VILIM
VFB
Gate Drive Supply Input
Controller Supply Input
Current Limit Input
Output Voltage Feedback
Enable Input
Referenced to PGND, AGND
Referenced to PGND, AGND
Referenced to AGND
6.0
6.0
6.0
Referenced to AGND
6.0
VEN
Referenced to AGND
6.0
VSS
Soft Start Input
Referenced to AGND
6.0
VFREQ
VDDQ
Frequency Input
Referenced to AGND
6.0
VDDQ Input
Referenced to AGND
6.0
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
1000
2500
+150
+150
ESD
Electrostatic Discharge
TJ
Junction Temperature
Storage Temperature
TSTG
-55
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VPVIN
VIN
Parameter
Power Input
Condition
Referenced to PGND
Min.
7
Max. Unit
18
18
V
V
Modulator Input
Junction Temperature
Load Current
Referenced to AGND
7
TJ
-40
+125
6
°C
A
ILOAD
TA=25°C, No Airflow
VPVIN, VIN, VPVCC Connected for 5 V Rail
Operation and Referenced to PGND,
AGND
VPVIN, VIN, PVIN, VIN, and Gate Drive
VPVCC Supply Input
4.5
5.5
V
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
5
Thermal Characteristics
The thermal characteristics were evaluated on a 4-layer pcb structure (1 oz/1 oz/1 oz/1 oz) measuring 7 cm x 7 cm).
Symbol
Parameter
Thermal Resistance, Junction-to-Ambient
Typ.
Unit
35
2.7
2.3
°C/W
°C/W
°C/W
JA
ψJC
Thermal Characterization Parameter, Junction-to-Top of Case
Thermal Characterization Parameter, Junction-to-PCB
ψJPCB
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
6
Electrical Characteristics
Unless otherwise noted; VIN=12 V, VOUT=0.6 V, TA=TJ=-40 to +125°C.(1)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Supply Current
IVIN,SD
IVIN,Q
Shutdown Current
Quiescent Current
EN=0 V
16
µA
mA
mA
EN=5 V, Not Switching
EN=5 V, fSW=500 kHz
1.8
IVIN,GateCharge Gate Charge Current
10
Linear Regulator
VREG
IREG
Regulator Output Voltage
Regulator Current Limit
4.75
60
5.00
5.25
V
mA
Reference, Feedback Comparator
VFB
VDDQ
FB Voltage Threshold
VDDQ Pin Voltage Range
FB Pin Bias Current
590
0
596
0
602
3
mV
V
IFB
-100
100
nA
Modulator
RFREQ=56 k, VIN=10 V,
tON=250 ns, No Load
tON
On-Time Accuracy
-20
20
%
tOFF,MIN
DMIN
Minimum SW Off-Time
Minimum Duty Cycle
320
0
374
ns
%
FB=1 V
Soft-Start
ISS
Soft-Start Current
SS=0 V
7
10
13
10
µA
%
Current Limit
ILIM Valley Current Limit Accuracy
KILIM
TA=TJ=25°C, IVALLEY=4 A
-10
ILIM Set-Point Scale Factor
Temperature Coefficient
233
ILIMTC
Enable
VTH+
4000
ppm/°C
Rising Threshold
Hysteresis
1.11
1.26
122
1.14
4.5
1.43
1.28
V
mV
V
VHYST
VTH-
Falling Threshold
1.00
4.3
24
VENCLAMP Enable Voltage Clamp
IEN=20 µA
EN=5 V
V
IENCLAMP
IENLK
Clamp Current
µA
nA
µA
Enable Pin Leakage
Enable Pin Leakage
EN=1.2 V
VEN=5 V
100
76
IENLK
UVLO
VON
VCC Good Threshold Rising
Hysteresis Voltage
4.4
V
VHYS
160
mV
Thermal Shutdown
TOFF
THYS
Thermal Shutdown Trip Point(2)
Hysteresis(2)
155
15
°C
°C
Internal Bootstrap Diode
VFBOOT
IR
Notes:
Forward Voltage
Reverse Leakage
IF=10 mA
VR=24 V
0.6
V
1000
µA
1. Device is 100% production tested at TA=25°C. Limits over that temperature are guaranteed by design.
2. Guaranteed by design; not production tested.
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
7
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, VOUT=0.6 V, fSW=500 kHz, TA=25°C, and no
airflow; unless otherwise specified.
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
Vo=1.05V, L=1.2µH
Vo=0.9V, L=1.2µH
Vo=0.75V, L=0.72µH
Vo=0.6V, L=0.72µH
Vo=5V, L=3.3µH
Vo=3.3V, L=2.4µH
Vo=1.2V, L=1.2µH
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Load Current (A)
Load Current (A)
Figure 6.
Efficiency vs. Load Current VIN=12 V
and fSW=500 kHz
Figure 7.
Efficiency vs. Load Current VIN=12 V
and fSW=500 kHz
25
20
15
10
5
90
85
80
75
70
65
60
55
50
45
40
12Vi/0.6Vo/1.5MHz
12Vi/0.6Vo/1MHz
12Vi/0.6Vo/500kHz
Fsw=500kHz, L=0.72µH
Fsw=1MHz, L=0.4µH
Fsw=1.5MHz, L=0.4µH
0
0
2
4
6
0
2
4
6
Load Current (A)
Load Current (A)
Figure 8.
Efficiency vs. Load Current with VIN=12 V
and VOUT=0.6 V
Figure 9. Case Temperature Rise vs. Load Current
0.625
0.620
0.615
0.610
0.605
0.600
0.595
0.590
0.585
EN (5V/div)
RLOAD=0.25Ω
VIN=12V
VSS (0.5V/div)
VOUT (0.5V/div)
VDDQ (1V/div)
0
1
2
3
4
5
6
Load Current (A)
Figure 10. Load Regulation
Figure 11. Startup Waveforms Using Soft-Start with
2.4 A Resistive Load
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
8
Typical Performance Characteristics (Continued)
EN (5V/div)
EN (5V/div)
VSS (0.5V/div)
VSS (0.5V/div)
RLOAD=0.25Ω
VIN=12V
RLOAD=0.25O
VIN=12V
VOUT (0.5V/div)
VDDQ (1V/div)
VOUT (0.5V/div)
VDDQ (1V/div)
Figure 12. Startup Waveforms Tracking VDDQ with Figure 13. Shutdown Waveforms Tracking VDDQ with
2.4 A Resistive Load
2.4 A Resistive Load
VOUT (20mV/div)
EN (5V/div)
RLOAD=0.25Ω
VIN=12V
VIN=12V
VOUT=1.2V
VOUT (0.5V/div)
VDDQ (0.5V/div)
VSW (5V/div)
Figure 14. Tracking Operation with Variable VDDQ
Reference Input
Figure 15. Static Output Ripple with No Load
VOUT (20mV/div)
VOUT (20mV/div)
VIN=12V
VOUT=1.2V
VSW (5V/div)
VIN=12V
IOUT (1A/div)
VOUT=1.2V
Figure 16. Static Output Ripple with 4 A Load Current
Figure 17. Operation as Load Changes from
0 A to 4 A
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
9
Typical Performance Characteristics (Continued)
VOUT (20mV/div)
VOUT (20mV/div)
IL (1A/div)
VIN=12V
VOUT=1.2V
IOUT (1A/div)
VIN=12V, VOUT=1.2V
IOUT from 0A to 2A, 2.5A/µs
Figure 18. Operation as Load Changes from
4 A to 0 A
Figure 19. Load Transient from 0% to 50% Load
Current
VOUT (1V/div)
VSS (1V/div)
VOUT (20mV/div)
IL (1A/div)
IO (5A/div)
VIN=12V, VOUT=1.2V
IOUT from 2A to 4A, 2.5A/µs
IOUT=0A then short output
Figure 20. Load Transient from 50% to 100% Load
Current
Figure 21. Over-Current Protection with Heavy Load
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
10
Circuit Operation
The FAN23SV04TA uses a constant-on-time modulation
voltage and the frequency-setting resistor. This on-time
is proportional to the desired output voltage, divided by
the input voltage. With this proportionality, the frequency
is essentially constant over the load range where
inductor current is continuous.
architecture with
a
VIN feed-forward input to
accommodate a wide VIN range. This method provides
fixed switching frequency (fSW) operation when the
inductor operates in Continuous Conduction Mode
(CCM). Additional benefits include excellent line and
load transient response, cycle-by-cycle current limiting,
and elimination of loop compensation requirements.
For a buck converter in Continuous-Conduction Mode
(CCM), the switching frequency fSW is expressed as:
ꢄꢜꢝꢞ
At the beginning of each cycle, FAN23SV04TA turns on
the high-side MOSFET (HS) for a fixed duration (tON). At
ꢙ
ꢚꢛ
ꢁ
ꢡꢡꢡꢡꢡꢡ
(3)
ꢄ
ꢅꢆ ꢟ ꢠꢜꢆ
the end of tON, HS turns off for a duration (tOFF
)
The on-time generator sets the on-time (tON) for the
high-side MOSFET, which results in the switching
frequency of the regulator during steady-state operation.
To maintain a relatively constant switching frequency
over a wide range of input conditions, the input voltage
information is fed into the on-time generator.
determined by the operating conditions. Once the FB
voltage (VFB) falls below the reference voltage (VREF), a
new switching cycle begins.
The modulator provides a minimum off-time (tOFF-MIN) of
250 ns to provide a guaranteed interval for low-side
MOSFET (LS) current sensing and PFM operation. tOFF-
tON is determined by:
provides stability against multiple pulsing and limits
MIN
ꢢꢣꢜꢆ
maximum switching frequency during transient events.
ꢠꢜꢆ
ꢁ
ꢟ ꢖꢄꢡꢡꢡꢡꢡ
(4)
ꢤꢣꢜꢆ
Enable
where ItON is:
The enable pin can be driven with an external logic
signal, connected to a resistive divider from PVIN/Vin to
ground to create an Under-Voltage Lockout (UVLO)
based on the PVIN/VIN supply, or connected to
PVIN/VIN through a single resistor to auto-enable while
operating within the EN pin internal clamp current sink
capability.
ꢌ
ꢄ
ꢅꢆ
ꢤꢣꢜꢆ
ꢁ
ꢟ
ꢡꢡꢡꢡꢡ
(5)
ꢌꢥ
ꢦꢧꢊꢨ
where RFREQ is the frequency-setting resistor
described in the Setting Switching Frequency section;
CtON is the internal 2.2 pF capacitor; and ItON is the VIN
feed-forward current that generates the on-time.
The EN pin can be directly driven by logic voltages of
5 V, 3.3 V, 2.5 V, etc. If the EN pin is driven by 5 V logic,
a small current flows into the pin when the EN pin
voltage exceeds the internal clamp voltage of 4.3 V. To
eliminate clamp current flowing into the EN pin use a
voltage divider to limit the EN pin voltage to < 4 V.
The FAN23SV04TA implements open-circuit detection
on the FREQ pin to protect the output from an infinitely
long on-time. In the event the FREQ pin is left floating,
switching of the regulator is disabled. The
FAN23SV04TA is designed for a VIN input range 7 to
18 V and fSW from 200 kHz to 1.5 MHz, resulting in an
ItON ratio of 1 to 16.
To implement the UVLO function based on PVIN/VIN
voltage level, select values for R7 and R8 in Figure 1
such that the tap point reaches 1.26 V when VIN reaches
the desired startup level using the following equation:
As the ratio of VOUT to VIN increases, tOFF,min introduces a
limit on the maximum switching frequency as calculated
in the following equation, where the factor 1.2 is
included in the denominator to provide some headroom
for transient operation:
ꢄ
ꢅꢆꢇꢈꢉ
ꢀ ꢁ ꢂ ꢃ
ꢋ ꢌꢍ
(1)
ꢄꢊꢆꢇꢈꢉ
where VIN,on is the input voltage for startup and VEN,on
is the EN pin rising threshold of 1.26 V. With R8
selected as 10 kΩ, and VIN,on=9 V the value of R7 is
61.9 kΩ.
ꢄꢜꢝꢞ
ꢅꢆꢇꢏꢕꢉ
ꢪꢌ ꢋ
ꢫ
ꢄ
(6)
ꢙ
ꢚꢛ
ꢩ
ꢌꢬꢖ ꢟ ꢠꢜꢦꢦꢇꢏꢕꢉ
VDDQ
The EN pin can be pulled high with a single resistor
connected from VIN to the EN pin. With VIN > 5.5V a
series resistor is required to limit the current flow into
the EN pin clamp to less than 24 µA to keep the internal
clamp within normal operating range. The resistor value
can be calculated from the following equation:
This pin is connected to the VDDQ supply, which the
FAN23SV04TA must track during startup and produce
an output (VTT) equal to half of VDDQ in steady-state
conditions. To accomplish this, the VDDQ pin has an
internal resistor divider to AGND that provides a
reference voltage equal to VDDQ/2 at the positive input of
the FB comparator.
ꢄꢅꢆꢇꢏꢐꢑ ꢋ ꢄꢊꢆꢇꢒꢓꢐꢏꢔꢇꢏꢕꢉ
ꢊꢆ
ꢎ
(2)
ꢖꢖꢗꢘ
Soft-Start (SS)
A conventional soft-start ramp is implemented to provide
a controlled startup sequence of the output voltage. A
current is generated on the SS pin to charge an external
Constant On-Time Modulation
The FAN23SV04TA uses a constant on-time modulation
technique, in which the HS MOSFET is turned on for a
fixed time, set by the modulator, in response to the input
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
11
capacitor. The lesser of the voltage on the SS pin and
the reference voltage is used for output regulation.
During normal operation, the SS voltage is clamped to
400 mV above the FB voltage. The clamp voltage drops
to 40 mV during an overload condition (when VFB is ≤
400 mV) to allow the converter to recover using the soft-
start ramp once the overload condition is removed. There
is no on-time modulation during normal soft-start or when
recovering from an overload condition.
Application Information
Stability
Constant on-time stability consists of two parameters:
stability criterion and sufficient signal at VFB.
Stability criterion is given by:
The nominal startup time is programmable through an
internal current source charging the external soft-start
ꢠꢜꢆ
(8)
(9)
ꢊꢚꢧ ꢟ ꢢꢜꢝꢞ
ꢭ
ꢡꢡꢡ
ꢖ
capacitor CSS
:
Sufficient signal requirement is given by:
ꢤꢚꢚ ꢟ ꢠꢚꢚ
ꢄꢧꢊꢦ
ꢢꢚꢚ
ꢁ
ꢡꢡꢡꢡꢡ
(7)
ꢮꢤꢅꢆꢯ ꢟ ꢎ ꢮꢄꢦꢰꢡꢡꢡꢡ
ꢊꢚꢧ
where:
where IIND is the inductor current ripple and VFB is
the ripple voltage on VFB, which should be ≥12 mV.
CSS = External soft-start programming capacitor;
In certain applications, especially designs utilizing only
ceramic output capacitors, there may not be sufficient
ripple magnitude available on the feedback pin for
stable operation. In this case, an external circuit
consisting of 2 resistors (R2 and R6) and 2 capacitors
(C4 and C5) can be added to inject ripple voltage into
the FB pin (see Figure 1).
ISS = Internal soft-start charging current source,
10 A;
tSS = Soft-start time; and
VREF = VDDQ/2.
For example; for 1 ms startup time, CSS=15 nF.
The soft-start option can be used for ratiometric tracking.
When EN is LOW, the soft-start capacitor is discharged.
There are some specific considerations when selecting
the RCC ripple injector circuit. For typical applications,
use 4.99 kΩ for R6; the value of C4 can be selected as
0.1 µF and approximate values for R2 and C5 can be
determined using the following equations.
Internal Linear Regulator
The FAN23SV04TA includes a linear regulator to
facilitate single-supply operation for self-biased
applications. PVCC is the linear regulator output and
supplies power to the internal gate drivers. The PVCC
pin should be bypassed with a 2.2 µF ceramic capacitor.
The device can operate from a 5 V rail if the VIN, PVIN
and PVCC pins are connected together to bypass the
internal linear regulator.
R2 must be small enough to develop 12 mV of ripple:
ꢱ
ꢲ
ꢄ
ꢅꢆ ꢋ ꢄꢜꢝꢞ ꢟ ꢄꢜꢝꢞ
ꢖ ꢩ
(10)
,
ꢄꢅꢆ ꢟ ꢥꢬꢥꢌꢖꢄ ꢟ ꢢꢳ ꢟ ꢙ
ꢚꢛ
R2 must also be selected such that the R2C4 time
constant enables stable operation:
VCC Bias Supply and UVLO
ꢥꢬꢴꢴ ꢟ ꢖꢵ ꢟ ꢙꢚꢛ ꢟ ꢶꢜꢝꢞ ꢟ ꢢꢜꢝꢞ
The VCC rail supplies power to the controller. It is
generally connected to the PVCC rail through a low-
pass filter of a 10 resistor and 0.1 µF capacitor to
minimize any noise sources from the driver supply.
(11)
ꢖ ꢩ
ꢢꢳ
The minimum value of C5 can be selected to minimize
the capacitive component of ripple appearing on the
feedback pin:
An Under-Voltage Lockout (UVLO) circuit monitors the
VCC voltage to ensure proper operation. Once the VCC
voltage is above the UVLO threshold, the part begins
operation after an initialization routine of 50 µs. There is
no UVLO circuitry on either the PVCC or VIN rails.
ꢼꢽꢾꢿ ꢟ ꢷꢽꢾꢿ
(12)
ꢷꢸꢹꢺꢻ
ꢁ
ꣀꢖ ꢟ ꣀꢴ ꢟ ꢷꢳ
Using the minimum value of C5 generally offers the best
transient response, and 100 pF is a good initial value in
many applications. However, under some operating
conditions excessive pulse jitter may be observed. To
reduce jitter and improve stability, the value of C5 can
be increased:
Over-Current Protection (OCP)
The FAN23SV04TA uses current information through
the LS to implement valley-current limiting. While an OC
event is detected, the HS is prevented from turning on
and the LS is kept on until the current falls below the
user-defined set point. Once the current is below the set
point, the HS is allowed to turn on.
(13)
ꢢꢸ ꣁ ꢖ ꢟ ꢷꢸꢹꢺꢻ
5 V PVCC
The ILIM pin has an open detection circuit to provide
protection against operation without a current limit.
The PVCC is the output of the internal regulator that
supplies power to the drivers and VCC. It is crucial to keep
this pin decoupled to PGND with a ≥1 µF X5R or X7R
ceramic capacitor. Because VCC powers the internal
analog circuit, it is filtered from PVCC with a 10 Ω resistor
and 0.1 µF X7R decoupling ceramic capacitor to AGND.
Over-Temperature Protection (OTP)
FAN23SV04TA incorporates an over-temperature
protection circuit that disables the converter when the
die temperature reaches 155°C. The IC restarts when
the die temperature falls below 140°C.
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
12
Setting the Output Voltage (VOUT
)
ꢤꢒꢅꢆꢱꢧꢚꢲ ꢁ ꢤꢜꢯ ꢟ ꢟ ꢱꢌ ꢋ ꢲꢡꢡꢡꢡꢡꢡꢡ
(18)
The output voltage, VOUT, is regulated by initiating a high-
side MOSFET on-time interval when the valley of the
divided output voltage appearing at the FB pin reaches
VREF. Since this method regulates at the valley of the
output ripple voltage, the actual DC output voltage on
VOUT is offset from the programmed output voltage by the
average value of the output ripple voltage. The output
VOUT setting of the regulator can be determined using the
following equation:
where ILOAD-MAX is the maximum load current and D is
the duty cycle VOUT/VIN. The maximum ICIN(RMS) occurs
at 50% duty cycle.
The capacitance is given by:
ꢤꢜꢯ ꢟ ꢟ ꢱꢌ ꢋ ꢲ
ꢢꢅꢆ
ꢁ
ꢡꢡꢡꢡꢡꢡ
(19)
ꢙ
ꢚꢛ ꢟ ꢮꢄ
ꢅꢆ
where VIN is input voltage ripple, normally 1% of VIN.
ꢄꢯꢯꢨ
(14)
ꢄꢜꢝꢞ
ꢁ
ꢖ
For example: for VIN=12 V, VIN=120 mV, VOUT=0.6 V,
4 A load, and fSW=950 kHz; then CIN is calculated as
1.7 µF, select a single 10 µF, 25 V-rated ceramic
capacitor with X7R or similar dielectric, recognizing that
the capacitor DC bias characteristic indicates that the
capacitance value falls approximately 40% at VIN=12 V.
where VDDQ is the voltage applied to pin 31.
For example; if VDDQ=1.2 V then VOUT=600mV. VFB is
trimmed to value of 596 mV when
a
VDDQ=VREF=600 mV. The final output voltage, including
the effect of the output ripple voltage, can be
approximated by:
Output Capacitor Selection
Output capacitor COUT is also selected based on voltage
rating, RMS current ICIN (RMS) rating, and capacitance.
For capacitors with DC voltage bias derating, such as
ceramic capacitors, higher rating is recommended.
ꢄ
ꢄꢜꢝꢞꢡ ꢁ ꢄꢦꢰꢡ ꣂ ꣃ ꣄ꢕꢔꣅ
(15)
ꢖ
When calculating COUT
,
usually the dominant
Setting the Switching Frequency (fSW)
fSW is programmed through external RFREQ as follows:
requirement is the current load step transient. If the
unloading transient requirement (IOUT transitioning from
HIGH to LOW), is satisfied, the load transient (IOUT
transitioning LOW to HIGH), is also usually satisfied.
The unloading COUT calculation, assuming COUT has
negligible parasitic resistance and inductance in the
circuit path, is given by:
ꢄꢜꢝꢞ
ꢦꢧꢊꢨ
ꢁ
ꢡ
(16)
ꢖꢥ ꢢꢣꢜꢆ ꢙ
ꢚꢛ
where CtON=2.2 pF). For example; for fSW=500 kHz
and VOUT=0.6 V, then select a standard resistor value
for RFREQ=27.4 k.
ꢤ꣐ꢊ꣎ꢊ꣏ ꢋ ꢤ꣐ꢊ꣎ꢊ꣐
ꢱꢄꢜꢝꢞ ꣂ ꢮꢄꢜꢝꢞꢲ꣐ ꢋ ꢄꢜ꣐ꢝꢞ
ꢢꢜꢝꢞ ꢁ ꢶ ꢟ
ꢡꢡꢡꢡꢡꢡꢡꢡ
(20)
Inductor Selection
where Ilevel1 and Ilevel2 are current levels before and
after load steps, and VOUT is the voltage overshoot,
usually specified at 3 to 5%.
The inductor is typically selected based on the ripple
current (IL), which is approximately 25% to 45% of the
maximum DC load. The inductor current rating should
be selected such that the saturation and heating current
ratings exceed the intended currents encountered in the
application over the expected temperature range of
operation. Regulators that require fast transient
response use smaller inductance and higher current
ripple; while regulators that require higher efficiency
keep ripple current on the low side.
For example: for VI=12 V, VOUT=0.6 V, ILEVEL1=3 A,
ILEVEL2=2 A, fSW=500 kHz, LOUT=1 µH, and 4.0% VOUT
overshoot of 24 mV; the COUT value is calculated to be
170 µF, and four 47 µF, 6.3 V-rated X5R ceramic
capacitors may be used. This equation assumes that
the load current rises instantaneously: with reduced
current slew rate, the value for COUT can be reduced.
The inductor value is given by:
Setting the Current Limit
Current limit is implemented by sensing the inductor
valley current across the LS MOSFET VDS during the LS
on-time. The current-limit comparator prevents a new
on-time from starting until the valley current is less than
the current limit.
ꢱꢄꢅꢆ ꢋ ꢄꢜꢝꢞꢲ ꢄꢜꢝꢞ
ꢶ ꢁ
ꢟ
ꢡ
(17)
ꢮꢤ ꢟ ꢙ
ꢄ
ꢅꢆ
ꢚꢛ
For example: for 12 V VIN, 0.6 V VOUT, 4 A load, 25% IL,
and 500 kHz fSW; L is calculated to be 1.1 µH and a
standard value of 1 µH is selected.
The set point is configured by connecting a resistor from
the ILIM pin to the SW pin. A trimmed current is output
onto the ILIM pin, which creates a voltage across the
resistor. When the voltage on ILIM goes negative, an
over-current condition is detected.
Input Capacitor Selection
Input capacitor CIN is selected based on voltage rating,
RMS current ICIN(RMS) rating, and capacitance. For
capacitors with DC voltage bias derating, such as
ceramic capacitors, higher rating is strongly
recommended. RMS current rating is given by:
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
13
RILIM is calculated by:
ꢁ ꢌꢬꢥꢖ ꣑ꢅꢅ ꢡꢤ꣎ꢊ꣒
should be on a common side of the PCB in close
proximity to each other and connected using surface
copper.
(21)
ꢅꢅ
where KILIM is the current source scale factor, and
IVALLEY is the inductor valley current when the current
limit threshold is reached. The factor 1.02 accounts
for the temperature offset of the LS MOSFET
compared to the control circuit.
Sensitive analog components; including SS, FB, ILIM,
FREQ, and EN; should be placed away from the high-
voltage switching circuits, such as SW and BOOT, and
connected to their respective pins with short traces.
The inner PCB layer closest to the FAN23SV04TA
device should have Power Ground (PGND) under the
power-processing portion of the device (PVIN, SW, and
PGND). This inner PCB layer should have a separate
Analog Ground (AGND) under the P1 pad and the
associated analog components. AGND and PGND
should be connected together near the IC between
PGND pins 18-21 and AGND pin 23, which connects to
P1 thermal pad.
With the constant on-time architecture, HS is always
turned on for a fixed on-time. This determines the peak-
to-peak inductor current.
Current ripple I is given by:
ꢱꢄꢅꢆ ꢋ ꢄꢜꢝꢞꢲ ꢡꢠꢜꢆ
ꢮꢤ ꢁ
ꢡꢡꢡꢡꢡꢡ
(22)
ꢶ
From the equation above, the worst-case ripple occurs
during an output short circuit (where VOUT is 0 V). This
should be taken into account when selecting the current
limit set point.
The AGND thermal pad (P1) should be connected to
AGND plane on the inner layer using four 0.25 mm vias
spread under the pad. No vias are included under PVIN
(P2) and SW (P3) to maintain the PGND plane under
the power circuitry intact.
The FAN23SV04TA uses valley-current sensing. The
current limit (IILIM) set point is the valley (IVALLEY).
Power circuit loops that carry high currents should be
arranged to minimize the loop area. Primary focus
should be directed to minimize the loop for current flow
from the input capacitor to PVIN, through the internal
MOSFETs, and returning to the input capacitor. The
input capacitor should be placed as close to the PVIN
terminals as possible.
The valley current level for calculating RILIM is given by:
ꢮꢤ
(23)
ꢤ꣎ꢊ꣒ ꢁ ꢤꢜꢯꢡꢱꢒꢲ
ꢋ
ꢡꢡ
ꢖ
where ILOAD
is the DC load current when the
(CL)
current limit threshold is reached.
The current return path from PGND at the low-side
MOSFET source to the negative terminal of the input
capacitor can be routed under the inductor and also
through vias that connect the input capacitor and low-
side MOSFET source to the PGND region under the
power portion of the IC.
For example: in a converter designed for 4 A steady-
state operation and 1 A current ripple, the current-limit
threshold could be selected at 120% of ILOAD,(SS) to
accommodate transient operation and inductor value
decrease under loading. As a result; ILOAD,(SS) is 4.8 A,
IVALLEY=4.3 A, and RILIM is selected as the standard
value of1.02 k
The SW node trace that connects the source of the
high-side MOSFET and the drain of the low-side
MOSFET to the inductor should be short and wide.
Boot Resistor
To control the voltage across the output capacitor, the
output voltage divider should be located close to the FB
pin, with the upper FB voltage divider resistor connected
to the positive side of the output capacitor, and the
bottom resistor should be connected to the AGND
portion of the FAN23SV04TA device.
In some applications, especially with higher input voltage,
the VSW ring voltage may exceed the derating guidelines
of 80% to 90% of absolute rating for VSW. In this situation,
a resistor can be connected in series with the boot
capacitor (C3 in Figure 1) to reduce the turn-on speed of
the high-side MOSFET to reduce the amplitude of the
VSW ring voltage.
When using ceramic capacitor solutions with external
ramp injection circuitry (R2, C4, C5 in Figure 1), R2 and
C4 should be connected near the inductor and coupling
capacitor C5 should be placed near the FB pin to
minimize FB pin trace length.
PCB (Printed Circuit Board) Layout
Guidelines
The following should be considered before beginning a
PCB layout using the FAN23SV04TA. A sample PCB
layout from the evaluation board following the layout
guidelines is shown in Figure 22 - Figure 25.
Decoupling capacitors for PVCC and VCC should be
located close to their respective device pins.
SW node connections to BOOT, ILIM, and ripple
injection resistor R2 should be through separate traces.
Power components consisting of the input capacitors,
output capacitors, inductor, and FAN23SV04TA device
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
14
Figure 22.Evaluation Board Top Layer Copper
Figure 23.Evaluation Board Inner Layer 1 Copper
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
15
Figure 24.Evaluation Board Inner Layer 2 Copper
Figure 25.Evaluation Board Bottom Layer Copper
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN23SV04TA • Rev. 1.0
16
5.50±0.10
26
18
1.05±0.10
17
10
27
34
(30X)
0.25±0.05
5.00±0.10
0.25±0.05
0.025±0.025
1
9
SEATING
PLANE
PIN#1
INDICATOR
SEE
DETAIL 'A'
SCALE: 2:1
1.58±0.01
(0.43)
2.18±0.01
(0.35)
0.50±0.01
9
1
(0.25)
0.40±0.01 (30X)
(0.35) 34
10
0.68±0.01
(0.35)
3.50±0.01
2.58±0.01
(1.75)
17
(0.33)
(0.35)
(0.75)
27
0.43±0.01
18
26
(0.35)
(0.25)
(3X)
(0.28)
(0.24)
NOTES: UNLESS OTHERWISE SPECIFIED
A) NO INDUSTRY REGISTRATION APPLIES.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
1.75±0.01
E) DRAWING FILE NAME: MKT-PQFN34AREV2
F) FAIRCHILD SEMICONDUCTOR
5.70
2.18
2.10
1.58
(0.35)
0.55 (30X)
1.80
26
18
0.55
17
27
(1.75)
2.58
0.68
4.10 3.50
5.20
3.60
0.75
(1.85)
34
10
1
9
(0.30)
(0.35)
0.20
0.30 (30X)
0.50±0.05
0.43
(0.08)
4.10
LAND PATTERN
RECOMMENDATION
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