FAN23SV60MPX_技术文档

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September 2015

FAN23SV60

10 A Synchronous Buck Regulator

Description

Features

The FAN23SV60 is a highly efficient synchronous buck

regulator. The regulator is capable of operating with an

input range from 7 V to 24 V and supporting up to 10 A

continuous load currents.

.

V_INRange: 7 V to 24 V Using Internal Linear

Regulator for Bias

V_INRange: 4.5 V to 5.5 V with V_IN/P_VIN/P_VCC

Connected to Bypass Internal Regulator

The FAN23SV60 utilizes Fairchild’s constant on-time

control architecture to provide excellent transient

response and to maintain a relatively constant switching

frequency. This device utilizes Pulse Frequency

Modulation (PFM) mode to maximize light-load

efficiency by reducing switching frequency when the

inductor is operating in discontinuous conduction mode

at light loads, while clamping the minimum frequency

above the audible range with ultrasonic mode.

.

High Efficiency: Over to 96% Peak

Continuous Output Current: 10 A

Internal Linear Bias Regulator

Accurate Enable facilitates V_INUVLO Functionality

PFM Mode for Light-Load Efficiency

Excellent Line and Load Transient Response

Precision Reference: ±1% Over Temperature

Output Voltage Range: 0.6 to 5.5 V

Programmable Frequency: 200 kHz to 1.5 MHz

Programmable Soft-Start

Switching frequency and over-current protection can

be programmed to provide a flexible solution for

various applications. Output over-voltage, under-

voltage, over-current, and thermal shutdown protections

help prevent damage to the device during fault

conditions. After thermal shutdown is activated, a

hysteresis feature restarts the device when normal

operating temperature is reached.

Low Shutdown Current

Adjustable Sourcing Current Limit

Internal Boot Diode

Thermal Shutdown

Halogen and Lead Free, RoHS Compliant

Applications

.

Mainstream Notebooks

Servers and Desktop Computers

Game Consoles

Telecommunications

Storage

Base Stations

Ordering Information

Operating

Temperature Range

Output

Current (A)

Part Number

Configuration

PFM with Ultrasonic Mode

Package

34-Lead, PQFN,

5.5 mm x 5.0 mm

FAN23SV60MPX

-40 to 125°C

10

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

Typical Application Diagrams

V_IN= 19V

R11

10Ω

C10

2.2µF

C9

0.1µF

CIN

0.1µF

CIN

3x10µF

R7

64.9kΩ

PVCC

VIN

PVIN

VCC

EN

Ext

EN

C3

0.1µF

R8

10kΩ

V_OUT= 1.2V

I_OUT=0-10A

BOOT

SW

FAN23SV60

R7, R8 used for Accurate EN

R7, R8 open for Ext EN

L1

0.72µH

PGOOD

ILIM

SOFT START

FREQ

R2

1.5kΩ

C4

0.1µF

COUT

6x47µF

R5 1.62kΩ

R3

10kΩ

C5

100pF

C7

15nF

FB

R9

54.9kΩ

R4

10kΩ

AGND

PGND

Figure 1. Typical Application with V_IN= 19 V

V_IN= 5V

R11

10Ω

C10

2.2µF

C9

0.1µF

CIN

0.1µF

3x10µF

PVCC

VIN

PVIN

VCC

EN

Ext

EN

C3

0.1µF

V_OUT= 1.2V

I_OUT=0-10A

BOOT

SW

FAN23SV60

L1

0.72µH

PGOOD

ILIM

SOFT START

R2

1.5kΩ

C4

0.1µF

COUT

6x47µF

R5 1.62kΩ

R3

10kΩ

C5

100pF

C7

15nF

FREQ

FB

R9

54.9kΩ

R4

10kΩ

AGND

PGND

Figure 2. Typical Application with V_IN= 5 V

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

2

Functional Block Diagram

VIN

BOOT PVIN

PVCC

Linear

Regulator

PVCC

VCC

VCC UVLO

ENABLE

1.26V/1.14V

PVCC

EN

VCC

10µA

Modulator

HS Gate

Driver

SS

FB

Comparator

VREF

SW

PFM

Comparator

FREQ

Control

Logic

2^ndLevel OVP

Comparator

x1.2

PVCC

1^stLevel OVP

Comparator

x1.1

x0.9

LS Gate

Driver

Under-Voltage

Comparator

VCC

PGOOD

Thermal

Shutdown

10µA

Current Limit

Comparator

AGND

ILIM

PGND

Figure 3. Block Diagram

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

3

Pin Configuration

5

7

6

4

2

1

3

4

6

8

9

8

3

2

7

1

9

PVIN 10

PVIN 11

34 NC

33 NC

NC

34

33

10 PVIN

PVIN

(P2)

11

12

13

NC

PVIN

FREQ

SS

FREQ

32

31

SW 12

SW 13

32

31

SW

SS

AGND

(P1)

SW

(P3)

SW 14

SW 15

SW 16

SW 17

PGOOD 30

SW

30 PGOOD

14

15

EN

29

28

27

EN

29

28

27

16

17

NC

FB

NC

FB

21

20

19

18

19

20

21

22

23

24

25

26

25

24

23

22

26

Figure 4. Pin Assignments (Bottom View)

Figure 5. Pin Assignments (Top View)

Pin Definitions

Name

PVIN

VIN

Pad / Pin

Description

P2, 5-11

1

Power input for the power stage

Power input to the linear regulator; used in the modulator for input voltage feed-forward

Power output of the linear regulator; directly supplies power for the low-side gate driver

and boot diode. Can be connected to VIN and PVIN for operation from 5 V rail.

PVCC

25

VCC

PGND

AGND

SW

26

Power supply input for the controller

18-21

Power ground for the low-side power MOSFET and for the low-side gate driver

Analog ground for the analog portions of the IC and for substrate

P1, 4, 23

P3, 2, 12-17, 22 Switching node; junction between high-and low-side MOSFETs

Supply for high-side MOSFET gate driver. A capacitor from BOOT to SW supplies the

charge to turn on the N-channel high-side MOSFET. During the freewheeling interval

(low-side MOSFET on), the high-side capacitor is recharged by an internal diode

BOOT

3

connected to PVCC.

ILIM

FB

24

27

29

31

Current limit. A resistor between ILIM and SW sets the current limit threshold.

Output voltage feedback to the modulator

EN

SS

Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable.

Soft-start input to the modulator

On-time and frequency programming pin. Connect a resistor between FREQ and

AGND to program on-time and switching frequency.

FREQ

32

PGOOD

NC

30

Power good; open-drain output indicating V_OUTis within set limits.

Leave pin open or connect to AGND.

28, 33-34

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_PVIN

Parameter

Power Input

Conditions

Referenced to PGND

Min.

Max.

Unit

-0.3

-1

30.0

33.0

30.0

6.0

V

°C

V_IN

Modulator Input

Referenced to AGND

Referenced to PVCC

V_BOOT

Boot Voltage

Referenced to PVCC, <20 ns

Referenced to PGND, AGND

Referenced to PGND, AGND < 20 ns

Referenced to SW

V_SW

SW Voltage to GND

-5

Boot to SW Voltage

Boot to PGND

-0.3

V_BOOT

Referenced to PGND

30

V_PVCC

V_VCC

V_ILIM

V_FB

Gate Drive Supply Input

Controller Supply Input

Current Limit Input

Output Voltage Feedback

Enable Input

Referenced to PGND, AGND

Referenced to AGND

6.0

Referenced to AGND

6.0

V_EN

Referenced to AGND

6.0

V_SS

Soft Start Input

Referenced to AGND

6.0

V_FREQ

Frequency Input

Referenced to AGND

6.0

V_PGOODPower Good Output

Referenced to AGND

6.0

Human Body Model, JESD22-A114⁽¹⁾

Charged Device Model, JESD22-C101⁽²⁾

2000

2500

+150

ESD

Electrostatic Discharge

T_J

Junction Temperature

Storage Temperature

T_STG

-55

Note:

1. Exception for FB pin up to 350V

2. Exception for FB pin up to 500V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_PVIN

V_IN

Parameter

Power Input

Conditions

Referenced to PGND

Referenced to AGND

Min.

7

Max.

24

Unit

V

Modulator Input

Junction Temperature

Load Current

7

24

V

T_J

-40

+125

15

°C

A

I_LOAD

T_A=25°C, No Airflow

V_PVIN,V_IN, V_PVCCConnected for 5 V

Rail Operation and Referenced to

PGND, AGND

PV_IN, V_IN, and Gate Drive

Supply Input

V_PVIN,V_IN, V_PVCC

4.5

5.5

V

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

5

Thermal Characteristics

The thermal characteristics were evaluated on a 4-layer pcb structure (1 oz/1 oz/1 oz/1 oz) measuring 7 cm x 7 cm).

Symbol

Parameter

Typical

Unit

Thermal Resistance, Junction-to-Ambient

35

2.7

2.3

°C/W

_JA

ψ_JC

Thermal Characterization Parameter, Junction-to-Top of Case

Thermal Characterization Parameter, Junction-to-PCB

ψ_JPCB

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

6

Electrical Characteristics

Unless otherwise noted; V_IN=12 V, V_OUT=1.2 V, and T_A=T_J= -40 to +125°C. ⁽⁴⁾

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

Supply Current

I_VIN,SD

I_VIN,Q

Shutdown Current

Quiescent Current

EN=0 V

16

µA

mA

EN=5 V, Not Switching

EN=5 V, f_SW=500 kHz

1.8

I_{VIN,GateCharge}Gate Charge Current

14

Linear Regulator

V_REG

I_REG

Regulator Output Voltage

Regulator Current Limit

4.75

60

5.00

5.25

V

mA

Reference, Feedback Comparator

V_FB

I_FB

FB Voltage Trip Point

FB Pin Bias Current

590

596

0

602

100

mV

nA

-100

Modulator

R_FREQ=56.2 k, V_IN=10 V,

t_ON=250 ns, No Load

t_ON

On-Time Accuracy

-20

20

%

t_OFF,MIN

t_ON,MIN

D_MIN

Minimum SW Off-Time

Minimum SW On-Time

Minimum Duty Cycle

320

45

374

ns

FB=1 V

0

%

f_MINF

Minimum Frequency Clamp

18.2

25.4

32.7

kHz

Soft-Start

I_SS

Soft-Start Current

SS=0 V

7

10

13

µA

%

t_ON,SSMOD

Soft-Start On-Time Modulation

SS<0.6 V

V_FB=0.6 V

25

100

V_SSCLAMP,NOMNominal Soft-Start Voltage Clamp

400

40

mV

Soft-Start Voltage Clamp in Overload

V_SSCLAMP,OVL

Condition

V_FB=0.3 V, OC Condition

mV

PFM Zero-Crossing Detection Comparator

V_OFF

Current Limit

I_LIM

ZCD Offset Voltage

T_A=T_J=25°C

-6

0

mV

%

Valley Current Limit Accuracy

I_LIMSet-Point Scale Factor

Temperature Coefficient

T_A=T_J=25°C, I_VALLEY=7 A

-10

10

K_ILIM

149

I_LIMTC

4000

ppm/°C

Enable

V_TH+

Rising Threshold

Hysteresis

1.11

1.26

122

1.14

4.5

1.43

1.28

V

mV

V

V_HYST

V_TH-

Falling Threshold

Enable Voltage Clamp

Clamp Current

1.00

4.3

V_ENCLAMP

I_ENCLAMP

I_ENLK

I_EN=20 µA

V

24

100

76

µA

nA

µA

Enable Pin Leakage

EN=1.2 V

V_EN=5 V

I_ENLK

UVLO

V_ON

V_CCGood Threshold Rising

Hysteresis Voltage

4.4

V

V_HYS

160

mV

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

7

Electrical Characteristics

Unless otherwise noted; V_IN=12 V, V_OUT=1.2 V, and T_A=T_J= -40 to +125°C. ⁽⁴⁾

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

Fault Protection

V_UVP

V_VOP1

V_OVP2

R_PGOOD

PGOOD UV Trip Point

PGOOD OV Trip Point

On FB Falling

86

89

92

115

125

2.03

1

%

On FB Rising

108

118

111

122

Second OV Trip Point

On FB Rising; LS=On

I_PGOOD=2 mA

%

PGOOD Pull-Down Resistance

Ω

t_PG,SSDELAYPGOOD Soft-Start Delay

I_PG,LEAKPGOOD Leakage Current

Thermal Shutdown

0.82

1.42

ms

µA

T_OFF

T_HYS

Thermal Shutdown Trip Point⁽³⁾

Hysteresis⁽³⁾

155

15

°C

Internal Bootstrap Diode

V_FBOOTForward Voltage

I_RReverse Leakage

Notes:

3. Guaranteed by design; not production tested.

I_F=10 mA

V_R=5 V

0.6

V

1000

µA

4. Device is 100% production tested at T_A=25°C. Limits over that temperature are guaranteed by design.

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

8

Typical Performance Characteristics

Tested using evaluation board circuit shown in Figure 1 with V_IN=19 V, V_OUT=1.2 V, f_SW=500 kHz, T_A=25°C, and no

airflow; unless otherwise specified.

100

90

80

70

60

50

40

30

20

10

100

90

80

70

60

50

40

30

20

10

12VIN_1.05VOUT_500KHZ_0.72UH

12VIN_1.2VOUT_500KHZ_0.72UH

12VIN_3.3VOUT_500KHZ_1.2UH

12VIN_5VOUT_500KHZ_1.8UH

19VIN_1.05VOUT_500KHZ_0.72UH

19VIN_1.2VOUT_500KHZ_0.72UH

19VIN_3.3VOUT_500KHZ_1.8UH

19VIN_5VOUT_500KHZ_1.8UH

0.01

0.1

1

10

0.01

0.1

1

10

Load Current(A)

Figure 6. Efficiency vs. Load Current with V_IN=19 V

and f_SW=500 kHz

Figure 7. Efficiency vs. Load Current with V_IN=12 V

and f_SW=500kHz

100

90

80

70

60

50

100

90

80

70

60

50

40

30

20

10

12VIN_1.2VOUT_300KHZ_1.2UH

12VIN_1.2VOUT_500KHZ_0.72UH

12VIN_1.2VOUT_1MHZ_0.4UH

12VIN_1.2VOUT_1.5MHZ_0.23UH

40

19VIN_1.2VOUT_300KHZ_1.2UH

30

20

10

19VIN_1.2VOUT_500KHZ_0.72UH

19VIN_1.2VOUT_1MHZ_0.4UH

19VIN_1.2VOUT_1.5MHZ_0.23UH

0.01

0.1

1

10

0.01

0.1

1

10

Load Current(A)

Figure 8. Efficiency vs. Load Current with V_IN=19 V

and V_OUT=1.2 V

Figure 9. Efficiency vs. Load Current with V_IN=12 V

and V_OUT=1.2 V

90

80

19VIN_1.2VOUT_1.5MHz_0.23uH

19VIN_1.2VOUT_1MHz_0.4uH

19VIN_1.2VOUT_1.5MHz_0.23uH

80

70

19VIN_1.2VOUT_1MHz_0.4uH

19VIN_1.2VOUT_500kHz_0.72uH

70

19VIN_1.2VOUT_500kHz_0.72uH

60

50

40

30

20

10

0

50

40

30

20

10

0

5

10

15

0

5

10

15

Load Current (A)

Figure 10. Case Temperature Rise vs. Load Current Figure 11. Case Temperature Rise vs. Load Current

on 4 Layer PCB, 1 oz Copper, 7 cm x 7 cm on 4 Layer PCB, 1 oz Copper, 7 cm x 7 cm

FAN23SV60 • Rev. 1.10

www.fairchildsemi.com

9

Typical Performance Characteristics

Tested using evaluation board circuit shown in Figure 1 with V_IN=19 V, V_OUT=1.2 V, f_SW=500 kHz, T_A=25°C, and no

airflow; unless otherwise specified.

1.212

1.208

1.204

1.2

1.212

1.208

1.204

1.2

0A_1.2VOUT[V]

10A_1.2VOUT[V]

12VIN_1.2VOUT

19VIN_1.2VOUT

1.196

1.192

1.188

1.196

1.192

1.188

7

9

11 13 15 17 19 21 23 25

0

2

4

6

8

10

Load Current(A)

Figure 12. Load Regulation

InputVoltage (V)

Figure 13. Line Regulation

EN (5V/div)

V_IN=19V

I_OUT=0A

V_IN=19V

I_OUT=10A

Soft Start (0.5V/div)

V_OUT(0.5V/div)

Soft Start (0.5V/div)

V_OUT(0.5V/div)

PGOOD (5V/div)

Time (500µs/div)

Figure 14. Startup Waveforms with 0 A Load Current Figure 15. Startup Waveforms with 10 A Load Current

EN (5V/div)

V_IN=19V

I_OUT=0A

Soft Start (0.5V/div)

VOUT (0.5V/div)

PGOOD (5V/div)

V_IN=19V

I_OUT=10A

Vout Prebias

V_OUT(0.5V/div)

PGOOD (5V/div)

Time (500µs/div)

Time (200µs/div)

Figure 16. Shutdown Waveforms with 10 A

Load Current

Figure 17. Startup Waveforms with Pre-Bias

Voltage on Output

FAN23SV60 • Rev. 1.10

www.fairchildsemi.com

10

Typical Performance Characteristics

Tested using evaluation board circuit shown in Figure 1 with V_IN=19 V, V_OUT=1.2 V, f_SW=500 kHz, T_A=25°C, and no

airflow; unless otherwise specified.

V_OUT(20mV/div)

V_IN=19V

I_OUT=0A

I_OUT=10A

V_SW(10V/div)

Time (10µs/div)

Figure 18. Static Load Ripple at No Load

Figure 19. Static Load Ripple at Full Load

V_OUT(20mV/div)

V_IN=19V

V_OUT=1.2V

V_IN=19V

V_OUT=1.2V

I_OUT(1A/div)

Time (50µs/div)

Figure 20. Operation as Load Changes from 0 A to 2 A Figure 21. Operation as Load Changes from 2 A to 0 A

V_OUT(20mV/div)

V_IN=19V, V_OUT=1.2V

I_OUTfrom 5A to 10A, 2.5A/us

V_IN=19V, V_OUT=1.2V

I_OUTfrom 0A to 5A, 2.5A/us

I_OUT(5A/div)

Time (100µs/div)

Figure 22. Load Transient from 0% to 50%

Load Current

Figure 23. Load Transient from 50% to 100%

Load Current

FAN23SV60 • Rev. 1.10

www.fairchildsemi.com

11

Typical Performance Characteristics

Tested using evaluation board circuit shown in Figure 1 with V_IN=19 V, V_OUT=1.2 V, f_SW=500 kHz, T_A=25°C, and no

airflow; unless otherwise specified.

PGOOD indicates UVP

V_OUT(1V/div)

With V_OUTfalling in OCP

PGOOD (5V/div)

Pull V_OUTto 2.8V

through 3Ω resistor

V_FB(0.5V/div)

V_OUT(1V/div)

Soft Start (1V/div)

Level 1

PGOOD (5V/div)

V_SW(10V/div)

I_L(10A/div)

Level 2

I_OUT=0A then short output

Time (200µs/div)

Time (50µs/div)

Figure 24. Over-Current Protection with Heavy Load Figure 25. Over-Voltage Protection Level 1 and Level 2

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

12

Circuit Operation

The FAN23SV60 uses a constant on-time modulation

Constant On-time Modulation

architecture with

a

V_INfeed-forward input to

The FAN23SV60 uses a constant on-time modulation

technique, in which the HS MOSFET is turned on for a

fixed time, set by the modulator, in response to the input

voltage and the frequency setting resistor. This on-time

is proportional to the desired output voltage, divided by

the input voltage. With this proportionality, the frequency

is essentially constant over the load range where

inductor current is continuous.

accommodate a wide V_INrange. This method provides

fixed switching frequency (f_SW) operation when the

inductor operates in Continuous Conduction Mode

(CCM) and variable frequency when operating in Pulse

Frequency Mode (PFM) at light loads. Additional

benefits include excellent line and load transient

response,

cycle-by-cycle

current

limiting,

and

elimination of the need for loop compensation.

For buck converter in Continuous-Conduction Mode

(CCM), the switching frequency f_SWis expressed as:

At the beginning of each cycle, FAN23SV60 turns on

the high-side MOSFET (HS) for a fixed duration (t_ON). At

ꢄ_ꢜꢝꢞ

the end of t_ON, HS turns off for a duration (t_OFF

)

ꢙ

ꢚꢛ

ꢁ

ꢡꢡꢡꢡꢡꢡ

(3)

determined by the operating conditions. Once the FB

voltage (V_FB) falls below the reference voltage (V_REF), a

new switching cycle begins.

ꢄ

_ꢅꢆꢟ ꢠ_ꢜꢆ

The on-time generator sets the on-time (t_ON) for the

high-side MOSFET, which results in the switching

frequency of the regulator during steady-state operation.

To maintain a relatively constant switching frequency

over a wide range of input conditions, the input voltage

information is fed into the on-time generator.

The modulator provides a minimum off-time (t_OFF-MIN) of

320 ns to provide a guaranteed interval for low-side

MOSFET (LS) current sensing and PFM operation. t_OFF-

is also used to provide stability against multiple

MIN

pulsing and limits maximum switching frequency during

transient events.

t_ONis determined by:

ꢢ_ꢣꢜꢆ

Enable

ꢠ_ꢜꢆ

ꢁ

ꢟ ꢖꢄꢡꢡꢡꢡꢡ

(4)

ꢤ_ꢣꢜꢆ

The enable pin can be driven with an external logic

signal, connected to a resistive divider from PVIN/Vin to

ground to create an Under-Voltage Lockout (UVLO)

based on the PVIN/VIN supply, or connected to

PVIN/VIN through a single resistor to auto-enable while

operating within the EN pin internal clamp current sink

capability.

where I_tONis:

ꢌ

ꢄ

ꢅꢆ

ꢤ_ꢣꢜꢆ

ꢁ

ꢟ

ꢡꢡꢡꢡꢡ

(5)

ꢌꢥ

ꢦꢧꢊꢨ

where R_FREQis the frequency-setting resistor

described in the Setting Switching Frequency section;

C_tONis the internal 2.2 pF capacitor; and I_tONis the V_IN

feed-forward current that generates the on-time.

The EN pin can be directly driven by logic voltages of

5 V, 3.3 V, 2.5 V, etc. If the EN pin is driven by 5 V logic,

a small current flows into the pin when the EN pin

voltage exceeds the internal clamp voltage of 4.3 V. To

eliminate clamp current flowing into the EN pin use a

voltage divider to limit the EN pin voltage to < 4 V.

The FAN23SV60 implements open-circuit detection on

the FREQ pin to protect the output from an infinitely long

on-time. In the event the FREQ pin is left floating,

switching of the regulator is disabled. The FAN23SV60

is designed for V_INinput range 7 to 24 V, f_SW200 kHz to

1.5 MHz, resulting in an I_tONratio exceeding 1 to 25.

To implement the UVLO function based on PVIN/VIN

voltage level, select values for R7 and R8 in Figure 1

the tap point reaches 1.26 V when V_INreaches the

desired startup level using the following equation:

As the ratio of V_OUTto V_INincreases, t_OFF,minintroduces a

limit on the maximum switching frequency as calculated

in the following equation, where the factor 1.2 is

included in the denominator to provide some headroom

for transient operation:

ꢄ

ꢅꢆꢇꢈꢉ

ꢀ ꢁ ꢂ ꢃ

ꢋ ꢌꢍ

(1)

ꢄ_{ꢊꢆꢇꢈꢉ}

where V_IN,onis the input voltage for startup and V_EN,on

is the EN pin rising threshold of 1.26 V. With R8

selected as 10 kΩ, and V_IN,on=9 V the value of R7 is

61.9 kΩ.

ꢄ_ꢜꢝꢞ

ꢪꢌ ꢋ

ꢫ

ꢄ

ꢅꢆꢇꢏꢕꢉ

(6)

ꢙ

ꢚꢛ

ꢩ

ꢌꢬꢖ ꢟ ꢠ_{ꢜꢦꢦꢇꢏꢕꢉ}

The EN pin can be pulled high with a single resistor

connected from VIN to the EN pin. With VIN > 5.5V a

series resistor is required to limit the current flow into

the EN pin clamp to less than 24 µA to keep the internal

clamp within normal operating range. The resistor value

can be calculated from the following equation:

Soft-Start (SS)

A conventional soft-start ramp is implemented to provide

a controlled startup sequence of the output voltage. A

current is generated on the SS pin to charge an external

capacitor. The lesser of the voltage on the SS pin and

the reference voltage is used for output regulation. To

reduce V_OUTripple and achieve a smoother ramp of the

output voltage, t_ONis modulated during soft-start. t_ON

starts at 50% of the steady-state on-time (PWM Mode)

and ramps up to 100% gradually.

ꢄ_{ꢅꢆꢇꢏꢐꢑ}ꢋ ꢄ_{ꢊꢆꢇꢒꢓꢐꢏꢔꢇꢏꢕꢉ}

ꢊꢆ

ꢎ

(2)

ꢖꢖꢗꢘ

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

13

During normal operation, the SS voltage is clamped to

400 mV above the FB voltage. The clamp voltage drops

to 40 mV during an overload condition to allow the

converter to recover using the soft-start ramp once the

overload condition is removed. On-time modulation

during SS is disabled when an overload condition exists.

To maintain a monotonic soft-start ramp, the regulator is

forced into PFM Mode during soft-start. The minimum

frequency clamp is disabled during soft-start.

Pulse Frequency Modulation (PFM)

One of the key benefits of using a constant on-time

modulation scheme is the seamless transitions in and

out of Pulse Frequency Modulation (PFM) Mode. The

PWM signal is not slave to a fixed oscillator and,

therefore, can operate at any frequency below the target

steady-state frequency. By reducing the frequency

during light-load conditions, the efficiency can be

significantly improved.

The nominal startup time is programmable through an

internal current source charging the external soft-start

The FAN23SV60 provides a Zero-Crossing Detector

(ZCD) circuit to identify when the current in the inductor

reverses direction. To improve efficiency at light load,

the LS MOSFET is turned off around the zero crossing

to eliminate negative current in the inductor. For

predictable operation entering PFM mode the controller

waits for nine consecutive zero crossings before

allowing the LS MOSFET to turn off.

capacitor C_SS

:

ꢤ_ꢚꢚꢟ ꢠ_ꢚꢚ

ꢄ_ꢧꢊꢦ

ꢢ_ꢚꢚ

ꢁ

ꢡꢡꢡꢡꢡ

(7)

where:

C_SS= External soft-start programming capacitor;

In PFM Mode, f_SWvaries or modulates proportionally to

the load; as load decreases, f_SWalso decreases. The

switching frequency, while the regulator is operating in

PFM, can be expressed as:

I_SS= Internal soft-start charging current source,

10 µA;

t_SS= Soft-start time; and

V_REF= 600 mV

ꢖ ꢟ ꢭ ꢟ ꢤ_ꢜꢝꢞ

ꢠ_ꢜ^ꢮ_ꢆꢟ ꢯꢄ_ꢅꢆꢋ ꢄ_ꢜꢝꢞ

ꢄ_ꢜꢝꢞ

ꢙ

ꢚꢛ

ꢁ

ꢟ

ꢡꢡꢡꢡ

(8)

For example; for 1 ms startup time, C_SS=15 nF.

ꢄ

ꢅꢆ

ꢰ

The soft-start option can be used for ratiometric tracking.

When EN is LOW, the soft-start capacitor is discharged.

where L is inductance and I_OUTis output load current.

Minimum Frequency Clamp

To maintain a switching frequency above the audible

range, the FAN23SV60 clamps the switching frequency

to a minimum value of 18 kHz. The LS MOSFET is

turned on to discharge the output and trigger a new

PWM cycle. The minimum frequency clamp is disabled

during soft-start.

Startup on Pre-Bias

FAN23SV60 allows the regulator to start on a pre-bias

output, V_OUT, and ensures V_OUTis not discharged during

the soft-start operation.

To guarantee no glitches on V_OUTat the beginning of the

soft-start ramp, the LS is disabled until the first positive-

going edge of the PWM signal. The regulator is also

forced into PFM Mode during soft-start to ensure the

inductor current remains positive, reducing the

possibility of discharging the output voltage.

Protection Features

The converter output is monitored and protected against

over-current, over-voltage, under-voltage, and high-

temperature conditions.

Over-Current Protection (OCP)

Internal Linear Regulator

The FAN23SV60 uses current information through the

LS to implement valley-current limiting. While an OC

event is detected, the HS is prevented from turning on

and the LS is kept on until the current falls below the

user-defined set point. Once the current is below the set

point, the HS is allowed to turn on.

The FAN23SV60 includes a linear regulator to facilitate

single-supply operation for self-biased applications.

PVCC is the linear regulator output and supplies power

to the internal gate drivers. The PVCC pin should be

bypassed with a 2.2 µF ceramic capacitor. The device

can operate from a 5 V rail if the V_IN, P_VIN, and P_VCC

pins are connected together to bypass the internal

linear regulator.

During an OC event, the output voltage may droop if the

load current is greater than the current the converter is

providing. If the output voltage drops below the UV

threshold, an overload condition is triggered. During an

overload condition, the SS clamp voltage is reduced to

40 mV and the on-time is fixed at the steady-state

duration. By nature of the control method; as V_OUTdrops,

the switching frequency is lower due to the reduced rate

of inductor current decay during the off-time.

V_CCBias Supply and UVLO

The V_CCrail supplies power to the controller. It is

generally connected to the PVCC rail through a low-

pass filter of a 10  resistor and 0.1 µF capacitor to

minimize any noise sources from the driver supply.

An Under-Voltage Lockout (UVLO) circuit monitors the

V_CCvoltage to ensure proper operation. Once the V_CC

voltage is above the UVLO threshold, the part begins

operation after an initialization routine of 50 µs. There is

no UVLO circuitry on either the PVCC or V_INrails.

The ILIM pin has an open-detection circuit to provide

protection against operation without a current limit.

Under-Voltage Protection (UVP)

If V_FBis below the under-voltage threshold of -11% V_REF

(534 mV), the part enters UVP and PGOOD pulls LOW.

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

14

Over-Voltage Protection (OVP)

There are two levels of OV protection: +11% and +22%.

During an over-voltage event, PGOOD pulls LOW.

ꢥꢬꢶꢶ ꢟ ꢖꢷ ꢟ ꢙ_ꢚꢛꢟ ꢭ_ꢜꢝꢞꢟ ꢢ_ꢜꢝꢞ

ꢢꢵ

(12)

ꢖ ꢩ

The minimum value of C5 can be selected to minimize

the capacitive component of ripple appearing on the

feedback pin:

When V_FBis > +11% of V_REF(666 mV), both HS and LS

turn off. By turning off the LS during an OV event, V_OUT

overshoot can be reduced when there is positive

inductor current by increasing the rate of discharge.

Once the V_FBvoltage falls below V_REF, the latched OV

signal is cleared and operation returns to normal.

ꢽ_ꢾꢿꣀꢟ ꢸ_ꢾꢿꣀꢟ ꢯꣁꢶ ꣂ ꣁꢵꢰ

(13)

ꢸꢹ_ꢺꢻꢼ

ꢁ

ꣁꢖ ꢟ ꣁꢶ ꢟ ꣁꢵ ꢟ ꢸꢵ

Using the minimum value of C5 generally offers the best

transient response, and 100 pF is a good initial value in

many applications. However, under some operating

conditions excessive pulse jitter may be observed. To

reduce jitter and improve stability, the value of C5 can

be increased:

A second over-voltage detection is implemented to

protect the load from more serious failure. When V_FB

rises +22% above the V_REF(732 mV), the HS turns off,

but the LS is forced on until a power cycle on VCC.

Over-Temperature Protection (OTP)

The FAN23SV60 incorporates an over-temperature

protection circuit that disables the converter when the

die temperature reaches 155°C. The IC restarts when

the die temperature falls below 140°C.

(14)

ꢢꢹ ꣃ ꢖ ꢟ ꢸꢹ_ꢺꢻꢼ

5 V PV_CC

Power Good (PGOOD)

The PV_CCis the output of the internal regulator that

supplies power to the drivers and V_CC. It is crucial to keep

this pin decoupled to PGND with a ≥1 µF X5R or X7R

ceramic capacitor. Because V_CCpowers internal analog

circuit, it is filtered from PV_CCwith a 10 Ω resistor and

0.1 µF X7R decoupling ceramic capacitor to AGND.

The PGOOD pin serves as an indication to the system

that the output voltage of the regulator is stable and

within regulation. Whenever V_OUTis outside the

regulation window or the regulator is at over-

temperature (UV, OV, and OT), the PGOOD pin is

pulled LOW.

Setting the Output Voltage (V_OUT

)

PGOOD is an open-drain output that asserts LOW when

V_OUTis out of regulation or when OT is detected.

The output voltage V_OUTis regulated by initiating a high-

side MOSFET on-time interval when the valley of the

divided output voltage appearing at the FB pin reaches

V_REF. Since this method regulates at the valley of the

output ripple voltage, the actual DC output voltage on

V_OUTis offset from the programmed output voltage by the

average value of the output ripple voltage. The initial V_OUT

setting of the regulator can be programmed from 0.6 V to

5.5 V by an external resistor divider (R3 and R4):

Application Information

Stability

Constant on-time stability consists of two parameters:

stability criterion and sufficient signal at V_FB.

Stability criterion is given by:

ꢶ

ꢵ ꢁ

ꢠ_ꢜꢆ

(15)

ꢄ

꣄

^ꢜꢝꢞꣅ ꢋ ꢌ

(9)

_ꢊꢚꢧꢟ ꢢ_ꢜꢝꢞ

ꢱ

ꢡꢡꢡ

ꢄ_ꢧꢊꢦ

ꢖ

Sufficient signal requirement is given by:

where V_REFis 600 mV.

For example; for 1.2 V V_OUTand 10 k R3, then R4 is

10 k. For 600 mV V_OUT, R4 is left open. VFB is

trimmed to a value of 596 mV when V_REF=600 mV, so

the final output voltage, including the effect of the output

ripple voltage, can be approximated by the equation:

ꢲꢤ_ꢅꢆꢳꢟ ꢎ ꢲꢄ_ꢦꢴꢡꢡꢡꢡ

(10)

ꢊꢚꢧ

where I_INDis the inductor current ripple and V_FBis

the ripple voltage on V_FB,which should be ≥12 mV.

In certain applications, especially designs utilizing only

ceramic output capacitors, there may not be sufficient

ripple magnitude available on the feedback pin for

stable operation. In this case, an external circuit can be

added to inject ripple voltage into the FB pin.

ꢄ

ꢶ

ꢄ_ꢜꢝꢞꢡꢁ ꢄ_ꢦꢴꢡ꣆ ꣇ꢌ ꣂ ꣈ ꣂ ꣇ ^꣉ꢕꢔ꣈

ꢵ

(16)

ꢖ

Setting the Switching Frequency (f_SW)

There are some specific considerations when selecting

the RCC ripple injector circuit. For typical applications,

the value of C4 can be selected as 0.1 µF and

approximate values for R2 and C5 can be determined

using the following equations.

f_SWis programmed through external R_FREQas follows:

ꢄ_ꢜꢝꢞ

ꢦꢧꢊꢨ

ꢁ

ꢡ

(17)

ꢖꢥ ꣆ ꢢ_ꢣꢜꢆ꣆ ꢙ

ꢚꢛ

where C_tON=2.2 pF internal capacitor that generates

t_ON. For example; for f_SW=500 kHz and V_OUT=1.2 V,

select a standard resistor value for R_FREQ=54.9 k.

R2 must be small enough to develop 12 mV of ripple:

ꢯ

ꢰ

ꢄ

_ꢅꢆꢋ ꢄ_ꢜꢝꢞꢟ ꢄ_ꢜꢝꢞ

(11)

ꢖ ꢩ

ꢄ_ꢅꢆꢟ ꢥꢬꢥꢌꢖꢄ ꢟ ꢢꢵ ꢟ ꢙ

ꢚꢛ

R2 must be selected such that the R2C4 time constant

enables stable operation:

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

15

When calculating C_OUT

,

usually the dominant

Inductor Selection

requirement is the current load step transient. If the

unloading transient requirement (I_OUTtransitioning from

HIGH to LOW), is satisfied, then the load transient (I_OUT

transitioning LOW to HIGH), is also usually satisfied.

The unloading C_OUTcalculation, assuming C_OUThas

negligible parasitic resistance and inductance in the

circuit path, is given by:

The inductor is typically selected based on the ripple

current (I_L), which is approximately 25% to 45% of the

maximum DC load. The inductor current rating should

be selected such that the saturation and heating current

ratings exceed the intended currents encountered in the

application over the expected temperature range of

operation. Regulators that require fast transient

response use smaller inductance and higher current

ripple; while regulators that require higher efficiency

keep ripple current on the low side.

ꢤ_꣋^ꢮ_꣌꣎ꢋ ꢤ_꣋^ꢮ_ꢅꢆ

ꢢ_ꢜꢝꢞꢁ ꢭ ꢟ

ꢡꢡꢡꢡꢡꢡꢡꢡ

(21)

ꢯꢄ_ꢜꢝꢞꣂ ꢲꢄ_ꢜꢝꢞꢰ^ꢮꢋ ꢄ_ꢜ^ꢮ_ꢝꢞ

where I_MAXand I_MINare maximum and minimum load

steps, respectively and V_OUTis the voltage

overshoot, usually specified at 3 to 5%.

The inductor value is given by:

ꢯꢄ_ꢅꢆꢋ ꢄ_ꢜꢝꢞꢰ ꢄ_ꢜꢝꢞ

ꢭ ꢁ

ꢟ

ꢡ

(18)

ꢲꢤ_꣊ꢟ ꢙ

ꢄ

ꢅꢆ

ꢚꢛ

For example: for V_I=19 V, V_OUT=1.2 V, 6A I_MAX, 2 A I_MIN

,

f_SW=500 kHz, L_OUT=720 nH, and 3% V_OUTdeviation of

36 mV; the C_OUTvalue is calculated to be 263µF. This

capacitor requirement can be satisfied using six 47 µF,

6.3 V-rated X5R ceramic capacitors. This calculation

applies for load current slew rates that are faster than

the inductor current slew rate, which can be defined as

V_OUT/L during the load current removal. For reduced-

load-current slew rates and/or reduced transient

requirements, the output capacitor value may be

reduced and comprised of low-cost 22 µF capacitors.

For example: for 19 V V_IN, 1.2 V V_OUT, 10 A load, 30%

I_L, and 500 kHz f_SW; L is 720 nH.

Input Capacitor Selection

Input capacitor C_INis selected based on voltage rating,

RMS current I_CIN(RMS)rating, and capacitance. For

capacitors having DC voltage bias derating, such as

ceramic capacitors, higher rating is strongly

recommended. RMS current rating is given by:

(19)

ꢤ_{ꢒꢅꢆꢯꢧ꣋ꢚꢰ}ꢁ ꢤ_{꣊ꢜ꣌ꢳ꣍꣋꣌꣎}ꢟ ꣏꣐ ꢟ ꢯꢌ ꢋ ꣐ꢰꢡꢡꢡꢡꢡꢡꢡ

Setting the Current Limit

where I_LOAD-MAXis the maximum load current and D is

the duty cycle V_OUT/V_IN. The maximum I_CIN(RMS)occurs

at 50% duty cycle.

Current limit is implemented by sensing the inductor

valley current across the LS MOSFET V_DSduring the LS

on-time. The current limit comparator prevents a new

on-time from being started until the valley current is less

than the current limit.

The capacitance is given by:

The set point is configured by connecting a resistor from

the ILIM pin to the SW pin. A trimmed current is output

onto the ILIM pin, which creates a voltage across the

resistor. When the voltage on ILIM goes negative, an

over-current condition is detected.

ꢤ_{꣊ꢜ꣌ꢳ꣍꣋꣌꣎}ꢟ ꣐ ꢟ ꢯꢌ ꢋ ꣐ꢰ

ꢢ_ꢅꢆ

ꢁ

ꢡꢡꢡꢡꢡꢡ

(20)

ꢙ

_ꢚꢛꢟ ꢲꢄ

ꢅꢆ

where V_INis the input voltage ripple, normally 1% of

V_IN.

For example; for V_IN=19 V, V_IN=120 mV, V_OUT=1.2 V,

10 A load, and f_SW=500 kHz; C_INis 9.8 F and I_CIN(RMS)is

2.4 A_RMS. Select a minimum of two 10 F 25 V-rated

ceramic capacitors with X7R or similar dielectric,

recognizing that the capacitor DC bias characteristic

indicates that the capacitance value falls approximately

60% at V_IN=19 V. Also, each 10 µF can carry over

3 A_RMSin the frequency range from 100 kHz to 1 MHz,

exceeding the input capacitor current rating

requirements. An additional 1 µF capacitor may be

needed to suppress noise generated by high frequency

switching transitions

R_ILIMis calculated by:

ꢅ꣊ꢅ꣋

ꢁ ꢌꢬꢥꢵ ꢟ ꣑_ꢅ꣊ꢅ꣋꣆ ꢡꢤ_{ꢅ꣊ꢅ꣋ꢇ꣒꣌꣊꣊ꢊ꣓}

(22)

where K_ILIMis the current source scale factor, and

I_VALLEYis the inductor valley current when the current

limit threshold is reached. The factor 1.04 accounts

for the temperature offset of the LS MOSFET

compared to the control circuit.

With the constant on-time architecture, HS is always

turned on for a fixed on-time; this determines the peak-

to-peak inductor current.

Current ripple I is given by:

Output Capacitor Selection

ꢯꢄ_ꢅꢆꢋ ꢄ_ꢜꢝꢞꢰ ꣆ꢡꢠ_ꢜꢆ

Output capacitor C_OUTis also selected based on voltage

rating, RMS current ICIN (RMS) rating, and

capacitance. For capacitors having DC voltage bias

derating, such as ceramic capacitors, higher rating is

highly recommended.

ꢲꢤ_꣊ꢁ

ꢡꢡꢡꢡꢡꢡ

(23)

ꢭ

From the equation above, the worst-case ripple occurs

during an output short circuit (where V_OUTis 0 V). This

should be taken into account when selecting the current

limit set point.

The FAN23SV60 uses valley-current sensing, the

current limit (I_ILIM) set point is the valley (I_VALLEY).

ꢲꢤ_꣊

(24)

ꢤ_{꣒꣌꣊꣊ꢊ꣓}ꢁ ꢤ_{꣊ꢜ꣌ꢳꢡꢯꢒ꣊ꢰ}

ꢋ

ꢡꢡ

ꢖ

The valley current level for calculating R_ILIMis given by:

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

16

PGND). This inner PCB layer should have a separate

analog ground (AGND) under the P1 pad and the

associated analog components. AGND and PGND

should be connected together near the IC between

PGND pins 18-21 and AGND pin 23, which connects to

P1 thermal pad.

where I_LOAD

current limit threshold is reached.

is the DC load current when the

(CL)

For example: In a converter designed for 10 A steady-

state operation and 3 A current ripple, the current-limit

threshold could be selected at 120% of I_LOAD,(MAX)to

accommodate transient operation and inductor value

decrease under loading. As a result, I_LOAD,(MAX)is 12 A,

I_VALLEY=10.5 A, and R_ILIMis 1.62 k

The AGND thermal pad (P1) should be connected to

AGND plane on inner layer using four 0.25 mm vias

spread under the pad. No vias are included under PVIN

(P2) and SW (P3) to maintain the PGND plane under

the power circuitry intact.

Boot Resistor

In some applications, especially with higher input

voltage, the V_SWring voltage may exceed derating

Power circuit loops that carry high currents should be

arranged to minimize the loop area. Primary focus

should be to minimize the loop for current flow from the

input capacitor to PVIN, through the internal MOSFETs,

and returning to the input capacitor. The input capacitor

should be as close to the PVIN terminals as possible.

guidelines of 80% to 90% of the absolute rating for V_SW

.

In this situation, a resistor can be connected in series

with a boot capacitor (C3 in Figure 1) to reduce the turn-

on speed of the high-side MOSFET to reduce the

amplitude of the V_SWring voltage. If necessary, a

resistor and capacitor snubber can be added from VSW

to PGND to reduce the magnitude of the ringing voltage.

Please contact Fairchild Customer Support for

assistance selecting a boot resistor or snubber circuit in

applications that operate above a 21 V typical input

voltage.

The current return path from PGND at the low-side

MOSFET source to the negative terminal of the input

capacitor can be routed under the inductor and also

through vias that connect the input capacitor and low-

side MOSFET source to the PGND region under the

power portion of the IC.

The SW node trace that connects the source of the

high-side MOSFET and the drain of the low-side

MOSFET to the inductor should be short and wide.

Printed Circuit Board (PCB) Layout

Guidelines

To control the voltage across the output capacitor, the

output voltage divider should be located close to the FB

pin, with the upper FB voltage divider resistor connected

to the positive side of the output capacitor and the

bottom resistor connected to the AGND portion of the

FAN23SV60 device.

The following points should be considered before

beginning a PCB layout using the FAN23SV60. A

sample PCB layout from the evaluation board is shown

in Figure 26 - Figure 29 following these layout

guidelines.

Power components (input capacitors, output capacitors,

inductor, and FAN23SV60 device) should be placed on

a common side of the PCB in close proximity to each

other and connected using surface copper.

When using ceramic capacitors with external ramp

injection circuitry (R2, C4, C5 in Figure 1), R2 and C4

should be connected near the inductor and coupling

capacitor C5 should be placed near FB pin to minimize

FB pin trace length.

Sensitive analog components including SS, FB, ILIM,

FREQ, and EN should be placed away from the high-

voltage switching circuits such as SW and BOOT and

connected to their respective pins with short traces.

Decoupling capacitors for PVCC and VCC should be

located close to their respective device pins.

SW node connections to BOOT, ILIM, and ripple

injection resistor R2 should be through separate traces.

The inner PCB layer closest to the FAN23SV60 device

should have power ground (PGND) under the power

processing portion of the device (PVIN, SW, and

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

17

Figure 26. Evaluation Board Top Layer Copper

Figure 27. Evaluation Board Inner Layer 1 Copper

www.fairchildsemi.com

FAN23SV60 • Rev. 1.10

18

Figure 28. Evaluation Board Inner Layer 2 Copper

Figure 29. Evaluation Board Bottom Layer Copper

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FAN23SV60 • Rev. 1.10

19

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1


型号：	FAN23SV60MPX
厂家：	ONSEMI
描述：	10A，24V 高能效 PoL 稳压器稳压器
文件：	总23页 (文件大小：1682K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN23SV60MPX [ONSEMI]

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