FAN3217TMX_技术文档

Dual 2-A High-Speed,

Low-Side Gate Drivers

FAN3216 / FAN3217

The FAN3216 and FAN3217 dual 2 A gate drivers are designed to

drive N−channel enhancement−mode MOSFETs in low−side

switching applications by providing high peak current pulses during

the short sw itching intervals. They are both available with TTL input

thresholds. Internal circuitry provides an under−voltage lockout

function by holding the output LOW until the supply voltage is within

the operating range. In addition, the drivers feature matched internal

propagation delays between A and B channels for applications

requiring dual gate drives with critical timing, such as synchronous

rectifiers. This also enables connecting two drivers in parallel to

effectively double the current capability driving a single MOSFET.

The FAN3216/17 drivers incorporate MillerDrivet architecture for

the final output stage. This bipolar−MOSFET combination provides

high current during the Miller plateau stage of the MOSFET turn−on /

turn−off process to minimize switching loss, while providing

rail−to−rail voltage swing and reverse current capability.

www.onsemi.com

8

1

SOIC8

CASE 751EB

PACKAGE OUTLINE

1

2

3

4

8

7

6

5

The FAN3216 offers two inverting drivers and the FAN3217 offers

two non−inverting drivers. Both are offered in a standard 8−pin SOIC

package.

Features

• Industry−Standard Pinouts

• 4.5 V to 18 V Operating Range

Figure 1. SOIC−8 (Top View)

• 3 A Peak Sink/Source at V = 12 V

DD

• 2.4 A Sink / 1.6 A Source at V

= 6 V

OUT

MARKING DIAGRAM

• Inverting Configuration (FAN3216) and Non−Inverting

Configuration (FAN3217)

8

XXXXX

AYWWG

G

• Internal Resistors Turn Driver Off If No Inputs

• 12 ns / 9 ns Typical Rise/Fall Times (1 nF Load)

• 20 ns Typical Propagation Delay Matched within 1 ns to the Other

Channel

1

SOIC8

• TTL Input Thresholds

A

L

Y

W

G

= Assembly Lot Code

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• MillerDrivet Technology

• Double Current Capability by Paralleling Channels

• Standard SOIC−8 Package

• Rated from –40°C to +125°C Ambient

(Note: Microdot may be in either location)

• These are Pb−Free Devices

*This information is generic. Please refer to device

data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

Applications

• Switch−Mode Power Supplies

• High-Efficiency MOSFET Switching

• Synchronous Rectifier Circuits

• DC-to-DC Converters

• Motor Control

ORDERING INFORMATION

See detailed ordering and shipping information on page 14 of

this data sheet.

1

Publication Order Number:

September, 2020 − Rev. 4

FAN3217/D

FAN3216 / FAN3217

PIN CONFIGURATIONS

1

8

NC

1

8

NC

2

3

4

7

6

5

OUTA

VDD

INA

GND

INB

A

B

2

3

4

7

6

5

OUTA

VDD

OUTB

INA

GND

INB

A

B

OUTB

Figure 2. FAN3216 Pin Configuration

Figure 3. FAN3217 Pin Configuration

THERMAL CHARACTERISTICS (Note 1)

Q

JL

Q

JT

Q

JA

Y

JB

Y

JT

(Note 2)

40

(Note 3)

31

(Note 4)

89

(Note 5)

43

(Note 6)

Package

Unit

8−Pin Small Outline Integrated Circuit (SOIC)

3.0

°C/W

1. Estimates derived from thermal simulation; actual values depend on the application.

2. Theta_JL (Q ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad)

JL

that are typically soldered to a PCB.

3. Theta_JT (Q ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform

JT

temperature by a top−side heatsink.

4. Theta_JA (Q ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given

JA

is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51−2, JESD51−5, and JESD51−7,

as appropriate.

5. Psi_JB (Y ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application

JB

circuit board reference point for the thermal environment defined in Note 4. For the SOIC−8 package, the board reference is defined as the

PCB copper adjacent to pin 6.

6. Psi_JT (Y ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of

JT

the top of the package for the thermal environment defined in Note 4.

PIN DEFINITIONS

Name

NC

Pin Description

No Connect. This pin can be grounded or left floating.

1

2

INA

Input to Channel A.

3

GND

INB

Ground. Common ground reference for input and output circuits.

Input to Channel B.

4

5 (FAN3216)

OUTB

Gate Drive Output B (inverted from the input): Held LOW unless required input is present and V is

DD

above UVLO threshold.

5 (FAN3217)

6

OUTB

VDD

Gate Drive Output B: Held LOW unless required input(s) are present and V is above UVLO threshold.

DD

Supply Voltage. Provides power to the IC.

7 (FAN3216)

OUTA

Gate Drive Output A (inverted from the input): Held LOW unless required input is present and V is

DD

above UVLO threshold.

7 (FAN3217)

8

OUTA

NC

Gate Drive Output A: Held LOW unless required input(s) are present and V is above UVLO threshold.

DD

No Connect. This pin can be grounded or left floating.

OUTPUT LOGIC

FAN3216 (x = A or B)

FAN3217 (x = A or B)

INx

OUTx

INx

0 (Note 7)

1

OUTx

0

1

0

1

1 (Note 7)

7. Default input signal if no external connection is made.

www.onsemi.com

2

FAN3216 / FAN3217

BLOCK DIAGRAMS

NC

1

2

8

NC

V_DD

100kW

INA

7

6

OUTA

VDD

100kW

UVLO

GND

INB

3

4

V_{DD_OK}

V

100kW

5

OUTB

100kW

Figure 4. FAN3216 Block Diagram

NC

1

2

8

NC

INA

7

6

OUTA

VDD

100kW

UVLO

GND

INB

3

4

V_{DD_OK}

5

OUTB

100kW

Figure 5. FAN3217 Block Diagram

www.onsemi.com

3

FAN3216 / FAN3217

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min.

−0.3

Max.

Unit

V

DD

VDD to PGND

20.0

V

INA and INB to GND

OUTA and OUTB to GND

GND − 0.3

V

DD

V

DD

+ 0.3

V

IN

V

OUT

+ 0.3

V

T

Lead Soldering Temperature (10 Seconds)

Junction Temperature

260

°C

L

T

−55

−65

150

J

T

Storage Temperature

STG

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min.

4.5

0

Max.

Unit

V

DD

Supply Voltage Range

18.0

V

IN

Input Voltage INA and INB

V

DD

V

T

A

Operating Ambient Temperature

−40

125

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

www.onsemi.com

4

FAN3216 / FAN3217

ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, V = 12 V, T = −40°C to +125°C. Currents are defined as positive into the device and negative out of the

DD

J

device.)

Symbol

SUPPLY

Parameter

Conditions

Min

Typ

Max

Unit

V

Operating Range

4.5

18.0

1.2

V

DD

I

Supply Current, Inputs Not

Connected

0.75

mA

V

Turn−On Voltage

Turn−Off Voltage

INA = V , INB = 0 V

3.45

3.25

3.9

3.7

4.35

4.15

V

ON

DD

V

OFF

INA = V , INB = 0 V

DD

INPUTS

V

INx Logic Low Threshold

INx Logic High Threshold

TTL Logic Hysteresis Voltage

Non−Inverting Input Current

Inverting Input Current

0.8

1.2

1.6

0.4

V

IL_T

IH_T

V

2.0

0.8

175

1.0

V

HYS_T

0.2

V

I

IN from 0 to V

−1.0

−175

mA

IN+

DD

IN−

DD

OUTPUTS

I

OUT Current, Mid−Voltage,

OUTx at V /2, C

= 0.22 mF,

=0.1 mF,

2.4

−1.6

3

A

SINK

DD

LOAD

Sinking (Note 8)

f = 1 kHz

I

OUT Current, Mid−Voltage,

Sourcing (Note 8)

OUTx at V /2, C

SOURCE

DD

LOAD

f = 1 kHz

I

OUT Current, Peak, Sinking

(Note 8)

C

= 0.1 mF, f = 1 kHz

PK_SINK

LOAD

I

OUT Current, Peak, Sourcing

(Note 8)

−3

PK_SOURCE

t

Output Rise Time (Note 9)

Output Fall Time (Note 9)

C

= 1000 pF

12

9

22

17

34

ns

RISE

LOAD

FALL

t

Output Propagation Delay,

TTL Inputs (Note 9)

0 – 5 V , 1 V/ns Slew Rate

10

19

,

IN

D1 D2

t

Propagation Matching Between

Channels

INA = INB, OUTA and OUTB at

50% Point

1

2

ns

DEL.MATCH

I

Output Reverse Current

Withstand (Note 8)

500

mA

RVS

8. Not tested in production.

9. See Timing Diagrams of Figure 6 and Figure 7.

TIMING DIAGRAMS

90%

10%

Output

Input

10%

V_INH

V_INL

Input

V_INL

t_D1

t_D2

t_D1

t_D2

t_RISE

t_FALL

t_RISE

Figure 6. Non−Inverting Timing Diagram

Figure 7. Inverting Timing Diagram

www.onsemi.com

5

FAN3216 / FAN3217

TYPICAL PERFORMANCE CHARACTERISTICS

Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted.

A

DD

Figure 8. I_DD(Static) vs. Supply Voltage (Note 10)

Figure 9. I_DD(Static) vs. Temperature (Note 10)

Figure 10. I_DD(Static) vs. Frequency

Figure 11. I_DD(1 nF Load) vs. Frequency

Figure 12. Input Thresholds vs. Supply Voltage

Figure 13. Input Thresholds vs. Temperature

www.onsemi.com

6

FAN3216 / FAN3217

TYPICAL PERFORMANCE CHARACTERISTICS

Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted. (continued)

A

DD

Figure 14. UVLO Threshold vs. Temperature

IN fall to OUT rise

IN rise to OUT fall

IN fall to OUT rise

Figure 15. Propagation Delay vs. Supply Voltage

Figure 16. Propagation Delay vs. Supply Voltage

IN or EN rise to OUT rise

IN fall to OUT rise

IN rise to OUT fall

IN or EN fall to OUT fall

Figure 17. Propagation Delays vs. Temperature

Figure 18. Propagation Delays vs. Temperature

www.onsemi.com

7

FAN3216 / FAN3217

TYPICAL PERFORMANCE CHARACTERISTICS

Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted. (continued)

A

DD

Figure 19. Fall Time vs. Supply Voltage

Figure 20. Rise Time vs. Supply Voltage

Figure 21. Rise and Fall Times vs. Temperature

www.onsemi.com

8

FAN3216 / FAN3217

TYPICAL PERFORMANCE CHARACTERISTICS

Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted. (continued)

A

DD

Figure 22. Rise/Fall Waveforms with 2.2 nF Load

Figure 23. Rise/Fall Waveforms with 10 nF Load

Figure 24. Quasi−Static Source Current

Figure 25. Quasi−Static Sink Current with

with V_DD= 12 V (Note 11)

V_DD= 12 V (Note 11)

Figure 26. Quasi−Static Source Current

Figure 27. Quasi−Static Sink Current with

with V_DD= 8 V (Note 11)

V_DD= 8 V (Note 11)

10.For any inverting inputs pulled low, non−inverting inputs pulled high, or outputs driven high, static I increases by the current flowing through

DD

the corresponding pull−up/down resistor shown in Figure 6 and Figure 7.

11. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current−measurement loop.

www.onsemi.com

9

FAN3216 / FAN3217

TEST CIRCUIT

V

DD

120 mF

4.7 mF

ceramic

Al. El.

Current Probe

LECROY AP015

I

OUT

C

LOAD

IN

1 mF

ceramic

V

OUT

1 kHz

0.1 mF

Figure 28. Quasi−Static I_OUT/ V_OUTTest Circuit

APPLICATIONS INFORMATION

Input Thresholds

the current as OUT swings between 1/3 to 2/3 V and the

DD

The FAN3216 and the FAN3217 drivers consist of two

identical channels that may be used independently at rated

current or connected in parallel to double the individual

current capacity.

MOS devices pull the output to the HIGH or LOW rail.

The purpose of the MillerDrive™ architecture is to speed

up switching by providing high current during the Miller

plateau region when the gate−drain capacitance of the

MOSFET is being charged or discharged as part of the

turn−on / turn−off process.

The input thresholds meet industry−standard TTL−logic

thresholds independent of the V voltage, and there is a

DD

hysteresis voltage of approximately 0.4 V. These levels

permit the inputs to be driven from a range of input logic

signal levels for which a voltage over 2 V is considered logic

HIGH. The driving signal for the TTL inputs should have

fast rising and falling edges with a slew rate of 6 V/ms or

faster, so a rise time from 0 to 3.3 V should be 550 ns or less.

With reduced slew rate, circuit noise could cause the driver

input voltage to exceed the hysteresis voltage and retrigger

the driver input, causing erratic operation.

For applications with zero voltage switching during the

MOSFET turn−on or turn−off interval, the driver supplies

high peak current for fast switching even though the Miller

plateau is not present. This situation often occurs in

synchronous rectifier applications because the body diode is

generally conducting before the MOSFET is switched ON.

The output pin slew rate is determined by V voltage and

DD

the load on the output. It is not user adjustable, but a series

resistor can be added if a slower rise or fall time at the

MOSFET gate is needed.

Static Supply Current

V

DD

In the I

(static) typical performance characteristics

DD

shown in Figure 8 and Figure 9, each curve is produced with

both inputs floating and both outputs LOW to indicate the

lowest static I current. For other states, additional current

DD

flows through the 100 kW resistors on the inputs and outputs

shown in the block diagram of each part (see Figure 6 and

Input

stage

V

OUT

Figure 7). In these cases, the actual static I current is the

DD

value obtained from the curves plus this additional current.

MillerDrive Gate Drive Technology

FAN3216 and FAN3217 gate drivers incorporate the

MillerDrive architecture shown in Figure 29. For the output

stage, a combination of bipolar and MOS devices provide

large currents over a wide range of supply voltage and

temperature variations. The bipolar devices carry the bulk of

Figure 29. MillerDrive Output Architecture

www.onsemi.com

10

FAN3216 / FAN3217

Under−Voltage Lockout

• Keep the driver as close to the load as possible to

minimize the length of high−current traces. This

reduces the series inductance to improve high−speed

switching, while reducing the loop area that can radiate

EMI to the driver inputs and surrounding circuitry.

• If the inputs to a channel are not externally connected,

the internal 100 kW resistors indicated on block

diagrams command a low output. In noisy

environments, it may be necessary to tie inputs of an

unused channel to VDD or GND using short traces to

prevent noise from causing spurious output switching.

• Many high−speed power circuits can be susceptible to

noise injected from their own output or other external

sources, possibly causing output re−triggering. These

effects can be obvious if the circuit is tested in

The FAN321x startup logic is optimized to drive

ground−referenced N−channel MOSFETs with an

under−voltage lockout (UVLO) function to ensure that the

IC starts up in an orderly fashion. When V is rising, yet

DD

below the 3.9 V operational level, this circuit holds the

output LOW, regardless of the status of the input pins. After

the part is active, the supply voltage must drop 0.2 V before

the part shuts down. This hysteresis helps prevent chatter

when low V supply voltages have noise from the power

DD

switching. This configuration is not suitable for driving

high−side P−channel MOSFETs because the low output

voltage of the driver would turn the P−channel MOSFET on

with V below 3.9 V.

DD

V_DDBypass Capacitor Guidelines

To enable this IC to turn a device ON quickly, a local

high-frequency bypass capacitor, C , with low ESR and

breadboard or non−optimal circuit layouts with long

input or output leads. For best results, make

BYP

ESL should be connected between the VDD and GND pins

with minimal trace length. This capacitor is in addition to the

bulk electrolytic capacitance of 10 mF to 47 mF commonly

found on driver and controller bias circuits.

connections to all pins as short and direct as possible.

• FAN3216 and FAN3217 are pin−compatible with many

other industry−standard drivers.

• The turn−on and turn−off current paths should be

minimized, as discussed in the following section.

A typical criterion for choosing the value of C

is to

BYP

keep the ripple voltage on the V supply to ≤5%. This is

DD

often achieved with a value ≥20 times the equivalent load

Figure 30 shows the pulsed gate drive current path when

the gate driver is supplying gate charge to turn the MOSFET

on. The current is supplied from the local bypass capacitor,

capacitance C

, defined here as Q

/V . Ceramic

GATE DD

EQV

capacitors of 0.1 mF to 1 mF or larger are common choices,

as are dielectrics, such as X5R and X7R with good

temperature characteristics and high pulse current

capability.

C

, and flows through the driver to the MOSFET gate and

BYP

to ground. To reach the high peak currents possible, the

resistance and inductance in the path should be minimized.

If circuit noise affects normal operation, the value of C

The localized C

acts to contain the high peak current

BYP

may be increased to 50−100 times the C

, or C

EQV

may

pulses within this driver−MOSFET circuit, preventing them

from disturbing the sensitive analog circuitry in the PWM

controller.

BYP

be split into two capacitors. One should be a larger value,

based on equivalent load capacitance, and the other a smaller

value, such as 1−10 nF mounted closest to the VDD and

GND pins to carry the higher frequency components of the

current pulses. The bypass capacitor must provide the pulsed

current from both of the driver channels and, if the drivers

are switching simultaneously, the combined peak current

V

DD

V

DS

C

BYP

sourced from the C

would be twice as large as when a

BYP

single channel is switching.

FAN321x

Layout and Connection Guidelines

PWM

The FAN3216 and FAN3217 gate drivers incorporates

fast-reacting input circuits, short propagation delays, and

powerful output stages capable of delivering current peaks

over 2 A to facilitate voltage transition times from under

10 ns to over 150 ns. The following layout and connection

guidelines are strongly recommended:

• Keep high−current output and power ground paths

separate from logic input signals and signal ground

paths. This is especially critical for TTL−level logic

thresholds at driver input pins

Figure 30. Current Path for MOSFET Turn−On

Figure 31 shows the current path when the gate driver

turns the MOSFET OFF. Ideally, the driver shunts the

current directly to the source of the MOSFET in a small

circuit loop. For fast turn−off times, the resistance and

inductance in this path should be minimized.

www.onsemi.com

11

FAN3216 / FAN3217

V

DD

V

DS

VDD

Turn−on threshold

C

BYP

FAN321x

IN−

PWM

IN+

(VDD)

Figure 31. Current Path for MOSFET Turn−Off

Operational Waveforms

At power-up, the driver output remains LOW until the

V

voltage reaches the turn−on threshold. The magnitude

DD

OUT

of the OUT pulses rises with V until steady−state V is

DD

reached. The non−inverting operation illustrated in

Figure 32 shows that the output remains LOW until the

UVLO threshold is reached, then the output is in−phase with

the input.

Figure 33. Inverting Startup Waveforms

Thermal Guidelines

Gate drivers used to switch MOSFETs and IGBTs at high

frequencies can dissipate significant amounts of power. It is

important to determine the driver power dissipation and the

resulting junction temperature in the application to ensure

that the part is operating within acceptable temperature

limits.

VDD

Turn−on threshold

The total power dissipation in a gate driver is the sum of

IN−

two components, P

and P

:

GATE

P_TOTAL+ P_GATE) P_DYNAMIC

DYNAMIC

(eq. 1)

IN+

P

GATE

(Gate Driving Loss): The most significant power

loss results from supplying gate current (charge per unit

time) to switch the load MOSFET on and off at the switching

frequency. The power dissipation that results from driving

a MOSFET at a specified gate−source voltage, V , with

GS

gate charge, Q , at switching frequency, f , is determined

G

SW

by:

OUT

P_GATE+ Q_G V_GS f_SW n

(eq. 2)

where n is the number of driver channels in use (1 or 2).

Figure 32. Non−Inverting Startup Waveforms

P

(Dynamic Pre−Drive Shoot−through

/

DYNAMIC

The inverting configuration of startup waveforms are

shown in Figure 33. With IN+ tied to VDD and the input

signal applied to IN–, the OUT pulses are inverted with

respect to the input. At power−up, the inverted output

Current): A power loss resulting from internal current

consumption under dynamic operating conditions,

including pin pull−up / pull−down resistors, can be obtained

using the graphs in the Typical Performance Characteristics

to determine the current I

drawn from V under

remains LOW until the V voltage reaches the turn−on

DYNAMIC

DD

actual operating conditions:

threshold, then it follows the input with inverted phase.

www.onsemi.com

12

FAN3216 / FAN3217

P_DYNAMIC+ I_DYNAMIC V_DD n

(eq. 3)

switching frequency of 500 kHz, the total power dissipation

is:

Once the power dissipated in the driver is determined, the

driver junction rise with respect to circuit board can be

evaluated using the following thermal equation, assuming

was determined for a similar thermal design (heat

sinking and air flow):

P_GATE+ 60nC 7 V 500 kHz 2 + 0.42 W

P_DYNAMIC+ 3 mA 7 V 2 + 0.042 W

P_TOTAL+ 0.46 W

(eq. 5)

(eq. 6)

(eq. 7)

Y

JB

T_J+ P_TOTAL y_JB) T_B

(eq. 4)

The SOIC−8 has

a

junction−to−board thermal

characterization parameter of Y = 43°C/W. In a system

JB

where:

T = driver junction temperature;

application, the localized temperature around the device is

a function of the layout and construction of the PCB along

with airflow across the surfaces. To ensure reliable

operation, the maximum junction temperature of the device

must be prevented from exceeding the maximum rating of

J

Y

JB

= (psi) thermal characterization parameter relating

temperature rise to total power dissipation; and

T = board temperature in location as defined in the Thermal

B

Characteristics table.

150°C; with 80% derating, T would be limited to 120°C.

J

Rearranging Equation 4 determines the board temperature

In the forward converter with synchronous rectifier

shown in the typical application diagrams, the FDMS8660S

is a reasonable MOSFET selection. The gate charge for each

required to maintain the junction temperature below 120°C:

T_B+ T_J* P_TOTAL y_JB

(eq. 8)

SR MOSFET would be 60 nC with V = V = 7 V. At a

GS

DD

T_B+ 120°C * 0.46 W 43°CńW + 100°C

(eq. 9)

www.onsemi.com

13

FAN3216 / FAN3217

TYPICAL APPLICATION DIAGRAMS

V

IN

V

IN

V

OUT

FAN3217

8

1

2

3

4

PWM

PWMA

GND

7

6

5

1

2

3

4

8

7

6

5

OUTA

VDD

Vbias

Timing/

Isolation

PWMB

OUTB

FAN3217

Figure 34. Forward Converter with Synchronous

Rectification

Figure 35. Primary−Side Dual Driver in a

Push−Pull Converter

V_IN

FAN3217

8

7

6

5

1

2

3

4

PWM−A

A

B

GND

VDD

PWM−B

Vbias

FAN3217

8

7

6

5

1

2

3

4

PWM−C

PWM−D

A

B

Phase Shift

Controller

Vbias

GND

VDD

Figure 36. Phase−Shifted Full−Bridge with Two Gate Drive Transformers (Simplified)

ORDERING INFORMATION

Part Number

Logic

Input Threshold

Package

Packing Method Quantity per Reel

FAN3216TMX

Dual Inverting Channels

TTL

SOIC−8

Tape & Reel

2,500

FAN3217TMX

Dual Non−Inverting

Channels

TTL

SOIC−8

www.onsemi.com

14

FAN3216 / FAN3217


型号：	FAN3217TMX
厂家：	ONSEMI
描述：	TTL 输入，双非反向输出，峰值 3A 汲电流，3A 源电流，低压侧门极驱动器驱动驱动器
文件：	总17页 (文件大小：954K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN3217TMX [ONSEMI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E