FAN3850TUC13X35 [ONSEMI]
Consumer Circuit, CMOS, PBGA6;
| 型号： | FAN3850TUC13X35 |
| 厂家： | 
ONSEMI |
| 描述： | Consumer Circuit, CMOS, PBGA6 商用集成电路 |
| 文件： | 总11页 (文件大小：1365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2012
FAN3850T
Microphone Pre-Amplifier with Temperature
Compensation and Digital Output
Description
Features
The FAN3850T integrates a pre-amplifier, LDO, and
Analog-to-Digital Converter (ADC) to convert Electret
Condenser Microphone (ECM) outputs to digital Pulse
Density Modulation (PDM) data streams. The pre-
amplifier accepts analog signals from the ECM and drives
an over-sampled sigma delta ADC and outputs PDM
data. The PDM digital audio has the advantage of noise
rejection and interface-to-mobile handset processors.
. Optimized for Mobile Handset and Notebook PC
Microphone Applications
. Accepts Input from Electret Condenser Microphones
. Pulse Density Modulation (PDM) Output
. Standard 5-Wire Digital Interface
. Amplifier Gain: 15.7dB or 13.7dB
The FAN3850T is powered from the system supply rails
up to 3.63V, with a low power consumption of only
0.85mW, and less than 20μW in Power-Down Mode.
The device compensates for the temperature variation
of the microphone element to achieve a flat sensitivity
response over-temperature.
. Negative Temperature Coefficient to Compensate for
ECM Positive Temperature Coefficient
. Low Input Capacitance, High PSR, 20kHz
Pre-Amplifier
. Low-Power, 1.5µA Sleep Mode
. Typical 420µA Supply Current
. Signal to Noise Ratio of 62.4dB(A)
. Total Harmonic Distortion: 0.01%
. Input Clock Frequency Range of 1-4MHz
. Integrated Low Drop-Out Regulator (LDO)
. Small 1.26mm x 0.86mm 6-Ball WLCSP
Sleep
LDO
Mode Ctrl
CLOCK
INPUT
Pre-Amp
ADC
DATA
SELECT
Applications
GND
.
.
.
.
Electret Condenser Microphones with Digital Output
Mobile Handsets
Figure 1. Block Diagram
Headset Accessories
Personal Computers (PC)
Ordering Information
Gain
Option
Operating
Temperature Range
Packing
Method
Part Number
Package
FAN3850TUC15X35
15.7dB
6-Ball, Wafer-Level Chip-Scale
Package (WLCSP)
3000 Unit
Tape & Reel
-30°C to +85°C
FAN3850TUC13X35
13.7dB
Note:
1. Alternate gain options and temperature coefficient slopes are possible. Please contact a Fairchild representative.
© 2011 Fairchild Semiconductor Corporation
FAN3850T • Rev. 3.0.2
www.fairchildsemi.com
Pin Configuration
Figure 2. Pin Configuration (Top View)
Description
Pin Definitions
Pin#
A1
Name
CLOCK
GND
Type
Input
Input
Output
Input
Input
Input
Clock Input
B1
Ground Pin
C1
A2
DATA
PDM Output – 1-Bit ADC
Rising or Falling Clock-Edge Select
Microphone Input
SELECT
INPUT
VDD
B2
C2
Device Power Pin
© 2011 Fairchild Semiconductor Corporation
FAN3850T • Rev. 3.0.2
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDD
Parameter
Min.
-0.3
-0.3
Max.
4.0
Unit
V
DC Supply Voltage
VIO
Analog and Digital I/O
VCC+0.3
V
Human Body Model, JESD22-A114(2),
All Pins Except Microphone Input
Human Body Model, JESD22-A114(2),
Microphone Input
±7
kV
V
ESD
±300
Note:
2. This device is fabricated using CMOS technology and is therefore susceptible to damage from electrostatic
discharges. Appropriate precautions must be taken during handling and storage of this device to prevent
exposure to ESD.
Reliability Information
Symbol
TJ
Parameter
Min.
Typ.
Max.
+150
+125
+260
Unit
°C
Junction Temperature
TSTG
Storage Temperature Range
Peak Reflow Temperature
-65
°C
TREFLOW
°C
Thermal Resistance, JEDEC Standard,
Multilayer Test Boards, Still Air
90
°C/W
JA
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Temperature Range
Supply Voltage Range
Min.
-30
Typ.
Max.
+85
3.63
10
Unit
°C
VDD
1.64
1.80
V
tRF-CLK
Clock Rise and Fall Time
ns
© 2011 Fairchild Semiconductor Corporation
FAN3850T • Rev. 3.0.2
www.fairchildsemi.com
3
Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB (SPL), fCLK=2.4MHz,
duty cycle = 50%, and CMIC=15pF.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VDD
Supply Voltage Range
1.64
1.80
3.63
V
INPUT=AC Coupled to GND,
CLOCK=On, No Load
IDD
Supply Current
420
1.4
μA
μA
ISLEEP
Sleep Mode Current
fCLK=GND
8.0
INPUT=AC Coupled to GND, Test
Signal on VDD=217Hz Square
Wave and Broad Band Noise(3)
both 100mVP-P
PSR
Power Supply Rejection(7)
-80
dBFS
INNOM Nominal Sensitivity(4)
INPUT=94dBSPL
-26
dBFS
dB(A)
SNR
Signal-to-Noise Ratio
Input Referred Noise(7)
fIN=1kHz 1Pa, A-Weighted
62.4
20Hz to 20kHz, A-Weighted
15.7dB Gain
eN
5.3
8.6
µVRMS
%
THD
Total Harmonic Distortion(5) fIN=1kHz, INPUT=-26dBFS
0.01
0.2
0.10
1.0
50Hz ≤ fIN ≤ 1kHz, INPUT=-20dBFS
THD+N THD and Noise(7)
fIN=1kHz, INPUT=-5dBFS
1.0
5.0
%
fIN=1kHz, INPUT=0dBFS
5.0
10.0
tc
Temperature Coefficient(7,11) Gain Measured at 50˚C and -10˚C
-0.035
0.2
dB/˚C
CIN
Input Capacitance(7,11)
INPUT
INPUT
pF
RIN
VIL
Input Resistance(7,11)
>100
1.5
GΩ
V
CLOCK & SELECT Input,
Logic LOW Level
0.3
CLOCK & SELECT Input,
Logic HIGH Level
VIH
VOL
VOH
VDD+0.3
0.35×VDD
V
Data Output, Logic LOW
Level
V
Data Output, Logic HIGH
Level
0.65×VDD
120
V
Maximum Input Signal for
15.7dB of Gain(5)
fIN=1 kHz, THD+N < 10%;
DC Level=0V
VIN15dB
VOUT
503
mVPP
Acoustic Overload Point(11)
THD < 10%
dBSPL
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FAN3850T • Rev. 3.0.2
www.fairchildsemi.com
4
Electrical Characteristics (Continued)
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB (SPL), fCLK=2.4MHz,
duty cycle = 50%, and CMIC=15pF.
Symbol
Parameter
Condition
Min.
Typ. Max.
Unit
Time from CLOCK Transition
to Data Becoming Valid
On Falling Edge of CLOCK,
SELECT=GND, CLOAD=15pF
tA
18
43
ns
Time from CLOCK Transition
to Data Becoming Hi-Z
On Rising Edge of CLOCK,
SELECT=GND, CLOAD=15pF
tB
tA
tB
0
18
0
5
56
5
16
16
ns
ns
ns
Time from CLOCK Transition
to Data Becoming Valid
On Rising Edge of CLOCK,
SELECT=VDD, CLOAD=15pF
Time from CLOCK Transition
to Data Becoming Hi-Z
On Falling Edge of CLOCK,
SELECT=VDD, CLOAD=15pF
fCLK
Input CLOCK Frequency(8)
CLOCK Duty Cycle(7)
Wake-Up Time(9)
Active Mode
1.0
40
2.4
50
4.0
60
MHz
%
CLKdc
tWAKEUP
fCLK=2.4MHz
fCLK=2.4MHz
0.35
0.01
2.00
1.00
100
ms
ms
pF
tFALLASLEEP Fall-Asleep Time(10)
CLOAD Load Capacitance on Data
Notes:
0
3. Pseudo-random noise with triangular probability density function. Bandwidth up to 10MHz.
4. Assumes 120dB(SPL) is mapped to 0dBFS.
5. Assumes an input -41, or -38dBV, depending on the part-specific gain.
6. Verified by design simulation, showing idle tones and low noise level modulation to be typical 96dB.
7. Guaranteed by characterization.
8. All parameters are tested at 2.4MHz. Frequency range guaranteed by characterization.
9. Device wakes up when fCLK ≥ 300kHz.
10. Device falls asleep when fCLK ≤ 70kHz.
11. Guaranteed by design.
12. Temperature coefficient is calculated by measuring gain in db at 50˚C and -10°C and dividing by 60 (Gain(50°C)
– Gain(-10°C)/60).
Figure 3. Interface Timing
© 2011 Fairchild Semiconductor Corporation
FAN3850T • Rev. 3.0.2
www.fairchildsemi.com
5
Typical Performance Characteristics
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB(SPL), fCLK=2.4MHz, and
duty cycle=50%.
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
‐10.00
‐20.00
0.001
0.010
0.100
1.000
10.000
100.000
1000.000
Input Signal (mVpp)
SNR (dBa)
THD (dB)
SINAD (dB)
Figure 4. THD, SINAD, and SNR vs. Input Amplitude
100.0
80.0
60.0
40.0
20.0
0.0
‐100.0
‐90.0
‐80.0
‐70.0
‐60.0
‐50.0
‐40.0
‐30.0
‐20.0
‐10.0
0.0
‐20.0
Signal Output Level (dBFs)
SNR (dBa)
THD (dB)
SINAD (dB)
Noise (dBFS)
Figure 5. THD, SINAD, and SNR vs. Output Level
© 2011 Fairchild Semiconductor Corporation
FAN3850T • Rev. 3.0.2
www.fairchildsemi.com
6
16.8
16.6
16.4
16.2
16.0
15.8
15.6
15.4
15.2
15.0
14.8
Temperature ˚C
Figure 6. Gain vs. Temperature (~.035db/˚C)(1)
Note:
13. Alternate temperature coefficient slopes are possible. Please contact a Fairchild representative.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN3850T • Rev. 3.0.2
7
Applications Information
VDD
Audio
SPEAKER
Output
CLOCK
DATA
INPUT
Pre-
Amp.
ADC
SELECT
SDI
Clk
SDO
L/R
Serial Port
Noise Shaper
Interpolation
Low Pass Filter
Decimation
Applications Software
Figure 7. Mono Microphone Application Circuit
VDD
Audio
SPEAKER
Output
CLOCK
INPUT
Pre-
Amp
DATA
ADC
SELECT
SDI
Clk
SDO
L/R
Serial Port
Noise Shaper
Interpolation
Low Pass Filter
Decimation
VDD
CLOCK
DATA
Applications Software
INPUT
Pre-
Amp
ADC
SELECT
Figure 8. Stereo Microphone Application Circuit
© 2011 Fairchild Semiconductor Corporation
FAN3850T • Rev. 3.0.2
www.fairchildsemi.com
8
Figure 9. MIC Element Drawing
Applications Information
A 0.1µF decoupling capacitor is required for VDD. It can
be located either inside the microphone or on the PCB
very close to the VDD pin.
A 100Ω resistance is recommended on the clock output
of the device driving the FAN3850T to minimize ringing
and improve signal integrity.
Due to high input impedance, careful consideration
should be taken to remove all flux used during the
reflow soldering process.
For optimal PSR, route a trace to the VDD pin. Do not
place a VDD plane under the device.
© 2011 Fairchild Semiconductor Corporation
FAN3850T • Rev. 3.0.2
www.fairchildsemi.com
9
Physical Dimensions
F
0.03 C
E
A
2X
0.570
(Ø0.120)
A1
0.485
B
D
CU PAD
PIN A1
AREA
(Ø0.220)
SOLDER MASK
0.03 C
2X
RECOMMENDED LAND
PATTERN (NSMD)
TOP VIEW
0.06 C
0.300
0.197±0.013
0.080±0.010
0.01 C
C
E
0.254
SEATING
PLANE
D
SIDE VIEWS
NOTES:
0.005
C A B
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
0.570
Ø0.120±0.010
6X
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
C
B
A
0.485
D. DATUM C, THE SEATING PLANE IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
(Y) +/-0.018
F
2
1
E. PACKAGE TYPICAL HEIGHT IS 273 MICRONS
±23 MICRONS (254-300 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
(X) +/-0.018
BOTTOM VIEW
G. DRAWING FILENAME: UC006AHrev3.
Figure 10. 6-Ball, Wafer-Level Chip-Scale Package (WLCSP)
Table 1. Product-Specific Dimensions
D
E
X
Y
1.260mm
0.860mm
0.145mm
0.145mm
Ball Composition: SN97.5-Ag2.5
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FAN3850T • Rev. 3.0.2
www.fairchildsemi.com
10
© 2011 Fairchild Semiconductor Corporation
FAN3850T • Rev. 3.0.2
www.fairchildsemi.com
11
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