FAN4860UC54X [ONSEMI]
3 MHz, Synchronous TinyBoost Regulator;
| 型号： | FAN4860UC54X |
| 厂家： | 
ONSEMI |
| 描述： | 3 MHz, Synchronous TinyBoost Regulator 开关 |
| 文件： | 总21页 (文件大小：1409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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February 2014
FAN4860
3 MHz, Synchronous TinyBoost™ Regulator
Features
Description
. Operates with Few External Components: 1 H Inductor
The FAN4860 is a low-power boost regulator designed to
provide a regulated 3.3 V, 5.0 V or 5.4 V output from a single
cell Lithium or Li-Ion battery. Output voltage options are fixed
at 3.3 V, 5.0 V, or 5.4 V with a guaranteed maximum load
current of 200 mA at VIN=2.3 V and 300 mA at VIN=3.3 V.
Input current in Shutdown Mode is less than 1 µA, which
maximizes battery life.
and 0402 Case Size Input and Output Capacitors
. Input Voltage Range from 2.3 V to 5.4 V
. Fixed 3.3 V, 5.0 V, or 5.4 V Output Voltage Options
. Maximum Load Current >150 mA at VIN=2.3 V
. Maximum Load Current 300 mA at VIN=3.3 V, VOUT=5.4 V
. Maximum Load Current 300 mA at VIN=3.3 V, VOUT=5.0 V
. Maximum Load Current 300 mA at VIN=2.7 V, VOUT=3.3 V
. Up to 92% Efficient
Light-load PFM operation is automatic and “glitch-free”. The
regulator maintains output regulation at no-load with as low
as 37 µA quiescent current.
The combination of built-in power transistors, synchronous
rectification, and low supply current make the FAN4860 ideal
for battery powered applications.
. Low Operating Quiescent Current
. True Load Disconnect During Shutdown
The FAN4860 is available in 6-bump 0.4 mm pitch Wafer-
Level Chip Scale Package (WLCSP) and a 6-lead 2x2 mm
ultra-thin MLP package.
. Variable On-time Pulse Frequency Modulation (PFM) with
Light-Load Power-Saving Mode
. Internal Synchronous Rectifier
(No External Diode Needed)
. Thermal Shutdown and Overload Protection
. 6-Pin 2 x 2 mm UMLP
. 6-Bump WLCSP, 0.4 mm Pitch
Applications
. USB “On the Go” 5 V Supply
. 5 V Supply – HDMI, H-Bridge Motor Drivers
. Powering 3.3 V Core Rails
Figure 1. Typical Application
. PDAs, Portable Media Players
. Cell Phones, Smart Phones, Portable Instruments
Ordering Information
Part Number
FAN4860UC5X
FAN4860UMP5X
FAN4860UC33X
FAN4860UC54X
Operating Temperature Range
-40°C to 85°C
Package
Packing Method
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
WLCSP, 0.4 mm Pitch
UMLP-6, 2 x 2 mm
WLCSP, 0.4 mm Pitch
WLCSP, 0.4 mm Pitch
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
Block Diagrams
Figure 2. IC Block Diagram
Pin Configurations
Figure 3. WLCSP (Top View)
Figure 4. WLCSP (Bottom View)
Figure 5. 2x2 mm UMLP (Top View)
Pin Definitions
Pin #
Name
WLCSP UMLP
Description
A1
B1
C1
C2
B2
6
5
4
3
2
VIN
SW
Input Voltage. Connect to Li-Ion battery input power source and input capacitor (CIN).
Switching Node. Connect to inductor.
EN
Enable. When this pin is HIGH, the circuit is enabled. This pin should not be left floating.
Feedback. Output voltage sense point for VOUT. Connect to output capacitor (COUT).
Output Voltage. This pin is both the output voltage terminal as well as an IC bias supply.
FB
VOUT
Ground. Power and signal ground reference for the IC. All voltages are measured with
respect to this pin.
A2
1, P1
GND
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
VIN
Parameter
Min.
-0.3
–2
Max.
5.5
6
Units
VIN Pin
VOUT Pin
FB Pin
V
V
V
VOUT
VFB
–2
6
DC
-0.3
-1.0
-0.3
5.5
6.5
5.5
VSW
VEN
SW Node
EN Pin
V
V
Transient: 10 ns, 3 MHz
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
2
1
Electrostatic Discharge
Protection Level
ESD
kV
TJ
TSTG
TL
Junction Temperature
Storage Temperature
–40
–65
+150
+150
+260
°C
°C
°C
Lead Soldering Temperature, 10 Seconds
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
2.3
Max.
4.5
Units
5.4 VOUT
5.0 VOUT
3.3 VOUT
VIN
Supply Voltage
2.3
4.5
V
2.3
3.2
IOUT
TA
Output Current
200
+85
+125
mA
°C
Ambient Temperature
Junction Temperature
–40
–40
TJ
°C
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer
2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature
TJ(max) at a given ambient temperate TA.
Symbol
Parameter
Typical
130
Units
°C/W
°C/W
WLCSP
UMLP
Junction-to-Ambient Thermal Resistance
JA
57
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
3
Electrical Specifications
Minimum and maximum values are at VIN=VEN=2.3 V to 4.5 V (2.5 to 3.2 VIN for 3.3 VOUT option), TA=-40°C to +85°C;
circuit of Figure 1, unless otherwise noted. Typical values are at TA=25°C, VIN=VEN=3.6 V for VOUT=5.0 V / 5.4 V, and
VIN=VEN=2.7 V for VOUT=3.3 V.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
Quiescent: VIN=3.6 V, IOUT=0, EN=VIN
Shutdown: EN=0, VIN=3.6 V
37
0.5
37
45
5.4 VOUT
1.5
Quiescent: VIN=3.6 V, IOUT=0, EN=VIN
Shutdown: EN=0, VIN=3.6 V
45
A
1.5
IIN
VIN Input Current
5.0 VOUT
3.3 VOUT
0.5
50
Quiescent: VIN=2.7 V, IOUT=0, EN=VIN
Shutdown: EN=0, VIN=2.7 V
65
1.5
nA
0.5
10
ILK_OUT VOUT Leakage Current
ILK_RVSR VOUT to VIN Reverse Leakage
VOUT=0, EN=0, VIN≥3 V
V
OUT=5.4 V, VIN=3.6 V, EN=0
VOUT=5.0 V, VIN=3.6 V, EN=0
VOUT=3.3 V, VIN=3.0 V, EN=0
VIN Rising
2.5
2.3
A
VUVLO
Under-Voltage Lockout
2.2
V
VUVLO_HY
Under-Voltage Lockout Hysteresis
190
mV
S
VENH
VENL
Enable HIGH Voltage
1.05
V
V
Enable LOW Voltage
0.4
1.00
5.50
5.50
5.50
5.15
5.15
5.15
3.41
5.475
5.125
3.380
255
ILK_EN
Enable Input Leakage Current
0.01
5.40
5.40
5.40
5.05
5.05
5.05
3.33
5.400
5.050
3.330
230
A
V
IN from 2.3 V to 4.5 V, IOUT≤200 mA
5.15
5.20
5.15
4.80
4.85
4.85
3.17
5.325
4.975
3.280
185
5.4 VOUT
VIN from 2.7 V to 4.5 V, IOUT≤200 mA
VIN from 3.3 V to 4.5 V, IOUT≤300 mA
Output Voltage
VOUT
VIN from 2.3 V to 4.5 V, IOUT≤200 mA
V
Accuracy(1)
5.0 VOUT
VIN from 2.7 V to 4.5 V, IOUT≤200 mA
VIN from 3.3 V to 4.5 V, IOUT≤300 mA
VIN from 2.5 V to 3.2 V, IOUT≤200 mA
Referred to VOUT=5.4 V
Referred to VOUT=5.0 V
Referred to VOUT=3.3 V
VIN=3.6 V, VOUT=5.4 V, IOUT=200 mA
VIN=3.6 V, VOUT=5.0 V, IOUT=200 mA
VIN=2.7 V, VOUT=3.3 V, IOUT=200 mA
VIN=2.3 V
3.3 VOUT
VREF
Reference Accuracy
V
tOFF
Off Time
195
240
265
ns
240
290
350
200
5.4 VOUT
VIN=3.3 V
300
VIN=3.6 V
400
400
VIN=2.3 V
200
300
Maximum Output
IOUT
mA
mA
Current(1)
5.0 VOUT
VIN=3.3 V
VIN=3.6 V
VIN=2.5 V
250
300
1000
930
3.3 VOUT
5.4 VOUT
VIN=2.7 V
VIN=3.6 V, VOUT>VIN
VIN=3.6 V, VOUT>VIN
VIN=2.7 V, VOUT>VIN
1400
1100
800
1500
1320
950
SW Peak Current
Limit
ISW
5.0 VOUT
3.3 VOUT
650
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
4
Electrical Specifications
Minimum and maximum values are at VIN=VEN=2.3 V to 4.5 V (2.5 to 3.2 VIN for 3.3 VOUT option), TA=-40°C to +85°C;
circuit of Figure 1, unless otherwise noted. Typical values are at TA=25°C, VIN=VEN=3.6 V for VOUT=5.0 V / 5.4 V, and
VIN=VEN=2.7 V for VOUT=3.3 V.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
5.4 VOUT
VIN=3.6 V, VOUT < VIN
900
850
700
270
100
250
300
400
150
30
Soft-Start Input Peak
Current Limit(2)
ISS
5.0 VOUT
3.3 VOUT
5.4 VOUT
5.0 VOUT
3.3 VOUT
VIN=3.6 V, VOUT < VIN
VIN=2.7 V, VOUT < VIN
VIN=3.6 V, IOUT=200 mA
VIN=3.6 V, IOUT=200 mA
VIN=2.7 V, IOUT=200 mA
VIN=3.6 V
mA
400
tSS
Soft-Start Time(3)
300
s
750
N-Channel Boost Switch
P-Channel Sync Rectifier
Thermal Shutdown
RDS(ON)
TTSD
mΩ
VIN=3.6 V
ILOAD=10 mA
°C
°C
TTSD_HYS Thermal Shutdown Hysteresis
Notes:
1. ILOAD from 0 to IOUT; also includes load transient response. VOUT measured from mid-point of output voltage ripple.
Effective capacitance of COUT > 1.5 F.
2. Guaranteed by design and characterization; not tested in production.
3. Elapsed time from rising EN until regulated VOUT.
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
5
5.4 VOUT Typical Characteristics
Unless otherwise specified; circuit per Figure 1, 3.6 VIN, and TA=25°C.
Figure 6. Efficiency vs. VIN
Figure 7. Efficiency vs. Temperature, 3.6 VIN
Figure 8. Line and Load Regulation
Figure 9. Quiescent Current
Figure 10. Maximum DC Load Current
Figure 11. Peak Inductor Current
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
6
5.4 VOUT Typical Characteristics
Unless otherwise specified; circuit per Figure 1, 3.6 VIN, and TA=25°C.
Figure 12. 0-50 mA Load Transient, 100 ns Step
Figure 13. 50-200 mA Load Transient, 100 ns Step
Figure 14. Line Transient, 5 mA Load, 10 µs Step
Figure 15. Line Transient, 200 mA Load, 10 µs Step
5.0 VOUT Typical Characteristics
Unless otherwise specified; circuit per Figure 1, 3.6 VIN, and TA=25°C.
95
92
89
86
100
95
90
85
2.5 Vin
83
80
-40C
3.3 Vin
3.6 Vin
+25C
+85C
4.5 Vin
80
75
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Load Current (mA)
Load Current (mA)
Figure 16. Efficiency vs. VIN
Figure 17. Efficiency vs. Temperature, 3.6 VIN
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
7
5.0 VOUT Typical Characteristics
Unless otherwise specified; circuit per Figure 1, 3.6 VIN, and TA=25°C.
50
50
25
2.5 Vin
-40C
+25C
+85C
3.3 Vin
25
3.6 Vin
4.5 Vin
0
0
-25
-50
-75
-25
-50
-75
-100
-100
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Load Current (mA)
Load Current (mA)
Figure 18. Line and Load Regulation
Figure 19. Load Regulation vs. Temperature, 3.6 VIN
4000
3200
2400
1600
800
50
-40C
+25C
45
40
35
30
25
+85C
2.5 Vin
3.6 Vin
4.5 Vin
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0
50
100
150
200
250
300
Input Voltage(V)
Load Current (mA)
Figure 20. Switching Frequency
Figure 21. Quiescent Current
Figure 22. Maximum DC Load Current
Figure 23. Peak Inductor Current
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
8
5.0 VOUT Typical Characteristics
Unless otherwise specified; circuit per Figure 1, 3.6 VIN, and TA=25°C.
Figure 24. Output Ripple, 10 mA PFM Load
Figure 25. Output Ripple, 200 mA PWM Load
Figure 26. 0-50 mA Load Transient, 100 ns Step
Figure 27. 50-200 mA Load Transient, 100 ns Step
Figure 28. Line Transient, 5 mA Load, 10 µs Step
Figure 29. Line Transient, 200 mA Load, 10 µs Step
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN4860 • Rev. 1.1.1
9
5.0 VOUT Typical Characteristics
Unless otherwise specified; circuit per Figure 1, 3.6 VIN, and TA=25°C.
Figure 30. Startup, No Load
Figure 31. Startup, 33 Load
Figure 33. Shutdown, 33 Load
Figure 35. Short-Circuit Response
Figure 32. Shutdown, 1 k Load
Figure 34. Overload Protection
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN4860 • Rev. 1.1.1
10
3.3 VOUT Typical Characteristics
Unless otherwise specified; circuit per Figure 1, 3.0 VIN, and TA=25°C.
100
95
98
95
92
89
86
83
90
85
2.5 Vin
80
-40C
+25C
+85C
2.7 Vin
3.0 Vin
3.2 Vin
75
0
50
100
150
200
250
300
300
3.5
0
50
100
150
200
250
300
Load Current (mA)
Load Current (mA)
Figure 36. Efficiency vs. VIN
Figure 37. Efficiency vs. Temperature, 3.0 VIN
40
20
40
2.5 Vin
2.7 Vin
3.0 Vin
3.2 Vin
-40C
+25C
+85C
20
0
0
-20
-40
-60
-80
-20
-40
-60
-80
0
50
100
150
200
250
0
50
100
150
200
250
300
Load Current (mA)
Load Current (mA)
Figure 38. Line and Load Regulation
Figure 39. Load Regulation vs. Temperature, 3.0 VIN
55
50
45
40
35
30
700
600
500
400
-40C
+25C
+85C
-40C
+25C
+85C
300
200
2.0
2.3
2.6
2.9
3.2
2.0
2.3
2.6
2.9
3.2
3.5
Input Voltage(V)
Input Voltage(V)
Figure 40. Quiescent Current
Figure 41. Maximum DC Load Current
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
11
3.3 VOUT Typical Characteristics
Unless otherwise specified; circuit per Figure 1, 3.0 VIN, and TA=25°C.
Figure 42. Output Ripple, 10 mA PFM Load
Figure 43. Output Ripple, 200 mA PWM Load
Figure 44. Startup, No Load
Figure 45. Startup, 22 Load
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN4860 • Rev. 1.1.1
12
Functional Description
Circuit Description
PFM Mode
The FAN4860 is a synchronous boost regulator, typically
operating at 3 MHz in Continuous Conduction Mode
(CCM), which occurs at moderate to heavy load current
and low VIN voltages.
If VOUT > VREF when the minimum off-time has ended, the
regulator enters PFM Mode. Boost pulses are inhibited until
VOUT < VREF. The minimum on-time is increased to enable
the output to pump up sufficiently with each PFM boost
pulse. Therefore, the regulator behaves like a constant on-
time regulator, with the bottom of its output voltage ripple at
5.05 V in PFM Mode.
At light-load currents, the converter switches automatically to
power-saving PFM Mode. The regulator automatically and
smoothly
transitions
between
quasi-fixed-frequency
continuous conduction PWM Mode and variable-frequency
PFM Mode to maintain the highest possible efficiency over
the full range of load current and input voltage.
Table 1. Operating States
Mode
LIN
Description
Linear Startup
Invoked When:
VIN > VOUT
PWM Mode Regulation
SS
Boost Soft-Start
VOUT < VREG
VOUT=VREG
The FAN4860 uses a minimum on-time and computed
minimum off-time to regulate VOUT. The regulator achieves
excellent transient response by employing current mode
modulation. This technique causes the regulator output to
exhibit a load line. During PWM Mode, the output voltage
drops slightly as the input current rises. With a constant VIN,
this appears as a constant output resistance.
BST
Boost Operating Mode
Shutdown and Startup
If EN is LOW, all bias circuits are off and the regulator is in
Shutdown Mode. During shutdown, true load disconnect
between battery and load prevents current flow from VIN to
VOUT, as well as reverse flow from VOUT to VIN.
The “droop” caused by the output resistance when a load is
applied allows the regulator to respond smoothly to load
transients with negligible overshoot.
LIN State
When EN rises, if VIN > UVLO, the regulator first attempts to
bring VOUT within about 1V of VIN by using the internal fixed
current source from VIN (ILIN1). The current is limited to about
630 mA during LIN1 Mode.
700
3.3 Vout
5.0 Vout
600
If VOUT reaches VIN-1V during LIN1 Mode, the SS state is
initiated. Otherwise, LIN1 times out after 16 clock counts and
the LIN2 Mode is entered.
500
400
300
200
100
In LIN2 Mode, the current source is incremented to 850 mA.
If VOUT fails to reach VIN-1 V after 64 clock counts, a fault
condition is declared.
SS State
Upon the successful completion of the LIN state (VOUT>VIN-
1 V), the regulator begins switching with boost pulses current
limited to about 50% of nominal level, incrementing to full
scale over a period of 32 clock counts.
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Input Voltage (V)
Figure 46. Output Resistance (ROUT
)
If the output fails to achieve 90% of its set point within 96 clock
counts at full-scale current limit, a fault condition is declared.
When the regulator is in PWM CCM Mode and the target
VOUT = 5.05 V, VOUT is a function of ILOAD and can be
computed as:
BST State
This is the normal operating mode of the regulator. The
regulator uses a minimum tOFF-minimum tON modulation
VOUT 5.05 ROUT ILOAD
For example, at VIN=3.3 V, and ILOAD=200 mA, VOUT drops to:
(1)
V
IN
V
OUT
scheme. Minimum tOFF is proportional to
, which keeps
the regulator’s switching frequency reasonably constant in
CCM. tON(MIN) is proportional to VIN and is higher if the inductor
current reaches 0 before tOFF(MIN) during the prior cycle.
VOUT 5.05 0.38 0.2 4.974V
(1A)
(1B)
To ensure that VOUT does not pump significantly above the
regulation point, the boost switch remains off as long as
At VIN=2.3 V, and ILOAD=200 mA, VOUT drops to:
VOUT 5.05 0.68 0.2 4.914V
FB > VREF
.
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
13
The VIN-dependent LIN Mode charging current is illustrated
in Figure 49.
Fault State
The regulator enters the FAULT state under any of the
following conditions:
. VOUT fails to achieve the voltage required to advance from
LIN state to SS state.
. VOUT fails to achieve the voltage required to advance from
SS state to BST state.
. Sustained (32 CLK counts) pulse-by-pulse current limit
during the BST state.
. The regulator moves from BST to LIN state due to a short
circuit or output overload (VOUT < VIN-1 V).
Once a fault is triggered, the regulator stops switching and
presents a high-impedance path between VIN and VOUT. After
waiting 480 CLK counts, a restart is attempted.
Figure 49. LIN Mode Current vs. VIN
Soft-Start and Fault Timing
The soft-start timing for each state, and the fault times, are
determined by the fault clock, whose period is inversely
proportional to VIN. This allows the regulator more time to
charge larger values of COUT when VIN is lower. With higher
VIN, this also reduces power delivered to VOUT during each
cycle in current limit.
Over-Temperature Protection (OTP)
The regulator shuts down when the thermal shutdown
threshold is reached. Restart, with soft-start, occurs when
the IC has cooled by about 30°C.
The number of clock counts for each state is illustrated in
Figure 47.
Over-Current Protection (OCP)
During Boost Mode, the FAN4860 employs a cycle-by-cycle
peak current limit to protect switching elements. Sustained
current limit, for 32 consecutive fault clock counts, initiates a
fault condition.
During an overload condition, as VOUT collapses to
approximately VIN-1 V, the synchronous rectifier is
immediately switched off and a fault condition is declared.
Automatic restart occurs once the overload/short is removed
and the fault timer completes counting.
Figure 47. Fault Response into Short Circuit
The fault clock period as a function of VIN is shown in Figure 48.
Figure 48. Fault Clock Period vs. VIN
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
14
Application Information
CEFF varies with manufacturer, dielectric material, case size,
and temperature. Some manufacturers may be able to
provide an X5R capacitor in 0402 case size that retains CEFF
>1.5 F with 5V bias; others may not. If this CEFF cannot be
economically obtained and 0402 case size is required, the IC
can work with the 0402 capacitor as long as the minimum
VIN is restricted to >2.7 V.
External Component Selection
Table 2 shows the recommended external components for
the FAN4860:
Table 2. External Components
REF
Description
Manufacturer
For best performance, a 10 V-rated 0603 output capacitor is
recommended (Kemet C0603C475K8PAC, or equivalent).
Since it retains greater CEFF under bias and over
temperature, output ripple can is reduced and transient
capability enhanced.
1.0 µH, 0.8 A,
190 m, 0805
Murata LQM21PN1R0MC0,
or equivalent
L1
Murata GRM155R60J225M
TDK C1005X5R0J225M
Kemet C0603C475K8PAC
TDK C1608X5R1A475K
2.2 µF, 6.3 V, X5R,
0402
CIN
4.7 µF, 10 V, X5R,
0603(4)
Output Voltage Ripple
COUT
Output voltage ripple is inversely proportional to COUT
During tON, when the boost switch is on, all load current is
supplied by COUT
.
Note:
.
4. A 6.3 V-rated 0603 capacitor may be used for COUT
such as Murata GRM188R60J225M. All datasheet
,
ILOAD
VRIPPLE(PP) tON
parameters are valid with the 6.3 V-rated capacitor.
Due to DC bias effects, the 10 V capacitor offers a
performance enhancement; particularly output ripple
and transient response, without any size increase.
(2)
COUT
and
VIN
tON tSW D tSW 1
(3)
(4)
VOUT
Output Capacitance (COUT
)
Therefore:
Stability
VIN
ILOAD
VRIPPLE(PP) tSW 1
The effective capacitance (CEFF) of small, high-value,
ceramic capacitors decrease as their bias voltage increases,
as shown in Figure 50.
VOUT
COUT
where:
1
tSW
(5)
fSW
As can be seen from Equation 4, the maximum VRIPPLE
occurs when VIN is minimum and ILOAD is maximum.
Startup
Input current limiting is in effect during soft-start, which limits
the current available to charge COUT. If the output fails to
achieve regulation within the time period described in the
soft-start section above; a FAULT occurs, causing the circuit
to shut down, then restart after a significant time period. If
COUT is a very high value, the circuit may not start on the first
attempt, but eventually achieves regulation if no load is
present. If a high-current load and high capacitance are both
present during soft-start, the circuit may fail to achieve
regulation and continually attempt soft-start, only to have
Figure 50. CEFF for 4.7 F, 0603, X5R, 6.3 V
(Murata GRM188R60J475K)
COUT discharged by the load when in the FAULT state.
The circuit can start with higher values of COUT under full
load if VIN is higher, since:
FAN4860 is guaranteed for stable operation with the
minimum value of CEFF (CEFF(MIN)) outlined in Table 3.
IRIPPLE
V
IN
IOUT I
LIM(PK)
(6)
Table 3. Minimum CEFF Required for Stability
Operating Conditions
2
VOUT
C
EFF(MIN) (F)
Generally, the limitation occurs in BST Mode.
VIN (V)
2.3 to 4.5
2.7 to 4.5
2.3 to 4.5
ILOAD (mA)
0 to 200
1.5
1.0
1.0
0 to 200
0 to 150
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
15
The FAN4860 starts on the first pass (without triggering a
FAULT) under the following conditions for CEFF(MAX)
Layout Guideline
:
Table 4. Maximum CEFF for First-Pass Startup
Operating Conditions
C
EFF(MAX) (F)
RLOAD(MIN) (Ω)
VIN (V)
5.4 VOUT
27
5.0 VOUT 3.3 VOUT
> 2.3
> 2.7
> 2.7
25
25
33
16
16
20
10
15
22
27
37
CEFF values shown in Table 4 typically apply to the lowest
VIN. The presence of higher VIN enhances ability to start into
larger CEFF at full load.
Transient Protection
Figure 52. WLCSP Suggested Layout (Top View)
To protect against external voltage transients caused by
ESD discharge events, or improper external connections,
some applications employ an external transient voltage
suppressor (TVS) and Schottky diode (D1 in Figure 51).
Figure 51. FAN4860 with External Transient Protection
The TVS is designed to clamp the FB line (system VOUT) to
+10 V or –2 V during external transient events. The Schottky
diode protects the output devices from the positive
excursion. The FB pin can tolerate up to 14 V of positive
excursion, while both the FB and VOUT pins can tolerate
negative voltages.
Figure 53. UMLP Suggested Layout (Top View)
The FAN4860 includes a circuit to detect a missing or
defective D1 by comparing VOUT to FB. If VOUT – FB > about
0.7 V, the IC shuts down. The IC remains shut down until
VOUT < UVLO and VIN < UVLO+0.7 or EN is toggled.
COUT2 may be necessary to preserve load transient response
when the Schottky is used. When a load is applied at the FB
pin, the forward voltage of the D1 rapidly increases before
the regulator can respond or the inductor current can
change. This causes an immediate drop of up to 300 mV,
depending on D1’s characteristics if COUT2 is absent. COUT2
supplies instantaneous current to the load while the regulator
adjusts the inductor current. A value of at least half of the
minimum value of COUT should be used for COUT2. COUT2
needs to withstand the maximum voltage at the FB pin as
the TVS is clamping.
The maximum DC output current available is reduced with
this circuit, due to the additional dissipation of D1.
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
16
Physical Dimensions
F
0.03 C
E
A
2X
0.40
B
D
A1
BALL A1
INDEX AREA
(Ø0.20)
Cu Pad
0.40
F
(Ø0.30)
Solder Mask
Opening
0.03 C
2X
TOP VIEW
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.06 C
E
0.378±0.018
0.208±0.021
0.625
0.547
0.05 C
SEATING PLANE
D
C
SIDE VIEWS
Ø0.260±0.010
6X
NOTES:
0.40
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
0.005
C A B
C
B
A
C. DIMENSIONS AND TOLERANCES PER
ASMEY14.5M, 1994.
(Y) +/-0.018
F
0.40
D. DATUM C, THE SEATING PLANE IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
2
1
(X) +/-0.018
E. PACKAGE TYPICAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
BOTTOM VIEW
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILENAME: UC006ACrev4.
Figure 54. 6-Lead, 0.4 mm Pitch, WLCSP Package
Product-Specific Dimensions
Product
D
E
X
Y
FAN4860UC5X
1.230mm ±0.030 mm
0.880 mm ±0.030 mm
0.240 mm
0.215 mm
FAN4860UC33X
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/UC/UC006AC.pdf.
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
17
Physical Dimensions
0.10 C
A
2.0
2X
B
1.45
2.0
(0.25)
PIN1
IDENT
0.10 C
0.80 1.80
2X
0.50
6X
TOP VIEW
0.65
0.35
6X
0.55 MAX
A
0.10 C
0.08 C
RECOMMENDED LAND PATTERN
(0.15)
C
0.05
0.00
SEATING
PLANE
SIDE VIEW
NOTES:
A. PACKAGE CONFORMS TO JEDEC MO-229
EXCEPT WHERE NOTED.
1.35
1.45
PIN1
IDENT
3
1
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
0.70
0.80
0.35
0.25
D. LANDPATTERN RECOMMENDATION IS BASED
ON FSC DESIGN ONLY.
6X
0.10 C A B
0.05 C
E. DRAWING FILENAME: MKT-UMLP06Erev2.
4
6
0.65
0.35
0.25
6X
BOTTOM VIEW
Figure 55. 6-Lead, UMLP Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/UM/UMLP06E.pdf.
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
18
© 2010 Fairchild Semiconductor Corporation
FAN4860 • Rev. 1.1.1
www.fairchildsemi.com
19
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