FAN48685UC08X [ONSEMI]

Fixed-Output Synchronous TinyBoost® Regulator;


型号：	FAN48685UC08X
厂家：	ONSEMI
描述：	Fixed-Output Synchronous TinyBoost® Regulator 开关输出元件
文件：	总12页 (文件大小：547K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

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Fixed-Output Synchronous

TinyBoost⁾Regulator

WLCSP9

CASE 567QW

FAN48685

Description

MARKING DIAGRAM

The FAN48685 is a low−power boost regulator designed to provide

a minimum voltage−regulated rail from a standard single−cell Li−Ion

battery and advanced battery chemistries. Even below the minimum

system battery voltage, the device maintains the output voltage

regulation for an output load current of 800 mA. The combination of

built−in power transistors, synchronous rectification, and low supply

current suit the FAN48685 for battery−powered applications.

The FAN48685 is available in a 9−bump, 0.4 mm pitch,

Wafer−Level Chip−Scale Package (WLCSP).

AWLYYWWG

= Specific Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

Features

• Input Voltage Range: 2.5 V to 5.5 V

• 800 mA Max. Load Capability

• Forced Pass−Through Mode

= Pb−Free Package

(Note: Microdot may be in either location)

• Three Output Voltage Programmability (3.6 V / 5.0 V / 5.45 V) via

MODE Pins

• 9−Bump, 0.4 mm Pitch WLCSP

• Four External Components: 0603 Inductor, 0402 Case Size Input,

0402 2 x Output Capacitors

• This is a Pb−Free Device

Applications

• NFC Module Power

VOUT

PVIN

FAN48685

CIN

COUT

MODE 1

MODE 0

PGND

Figure 1. Typical Application

ORDERING INFORMATION

Part Number

Operating Temperature Range

−40°C to 85°C

Package

Packing Method

Device Marking

FAN48685UC08X

9−Bump, 0.4 mm Pitch,

Tape & Reel

WLCSP Package

Publication Order Number:

August, 2021 − Rev. 1

FAN48685/D

FAN48685

Recommended External Components

Table 1. RECOMMENDED COMPONENTS

Component

Description

Vendor

Parameter

Typical Value

Unit

470 nH 0603

(1.6 mm x 0.8 mm x 0.8 mm max)

DFE18SANR47ME

Murata

0.47

DCR

ISAT

3.1

COUT

CIN

2 x 22 mF, 6.3 V, X5R, 0402

GRM155R60J226ME11

Murata

(1.0 mm x 0.5 mm)

10 mF, 6.3 V, X5R, 0402

(1.0 mm x 0.5 mm)

C1005X5R0J106M050BC

TDK

Pin Configuration

VOUT

PVIN

VOUT

MODE 0

PGND

MODE 1

PGND

Top View

(Bumps Down)

Bottom View

(Bumps Up)

Figure 2. Pin Assignment

Pin Descriptions

Table 2. PIN DESCRIPTIONS

Pin #

Name

Description

VOUT

Output Voltage: This pin is the output voltage terminal. Connect directly to COUT.

PVIN

Input Voltage: Connect to Li−Ion battery input power source and CIN.

Switching Node: Connect to inductor.

MODE 0

PGND

MODE 0: In combination with MODE 1 selects the operation of the part.

Power Ground: This is the power return for the IC. COUT and CIN capacitors should be

returned with the shortest path possible to these pins.

MODE 1

MODE 1: In combination with MODE 0 selects the operation of the part.

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FAN48685

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

Unit

PVIN

Voltage on PVIN Pin

Voltage on VOUT Pin

−0.3

6.5

(1)

VOUT

−0.3

6.5

(1)

VSW

VCTRL

ESD

SW Node

−0.3

6.5

(1)

MODE 0, MODE 1

6.5

Electrostatic Discharge Protection Level

Human Body Model, ANSI/ESDA/

2.0

1.0

JEDEC JS−001−2012

Charged Device Model, JESD22−C101

(2)

Junction Temperature

−40

−65

150

260

°C

Storage Temperature

STG

Lead Soldering Temperature, 10 Seconds

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Lesser of 6.5 V or PVIN + 0.3 V.

2. Please refer to Thermal Shutdown Protection in the Application information.

Table 4. RECOMMENDED OPERATING CONDITIONS

Symbol

PVIN

Parameter

Min

Typ

Max

5.5

Unit

Supply Voltage Range

Inductor

2.5

0.470

0.611

°C

CIN

Input Capacitance

Output Capacitance

Maximum Output Current

Ambient Temperature

Junction Temperature

(3)

COUT

IOUT

2 x 22

800

−40

125

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

3. The minimum effective capacitance at the output for stability is 5 uF which includes the voltage derated affect with 5.45 V DC applied.

Table 5. THERMAL PROPERTIES

Symbol

Parameter

Junction−to−Ambient Thermal Resistance

Typical

Unit

°C/W

NOTE: Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p

boards with vias in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature,

, at a given ambient temperature, T .

J(max)

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FAN48685

Table 6. ELECTRICAL CHARACTERISTICS (Notes 4, 5)

Minimum and maximum values are at PVIN = 2.5 V to VOUT – 200 mV at T = −40°C to +85°C, while typical values are at T = 25°C and

PVIN = 3.8 V, VOUT = 5 V otherwise noted.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Power Supplies

IQ When part is in Forced

Pass−Through

No Load

Q_PT

Under−Voltage Lockout

PVIN Rising

PVIN Falling

2.10

2.00

2.15

2.05

2.24

2.13

UVLO_RISE

UVLO_FALL

Output Accuracy

Regulated Output Voltage

PVIN = 2.5 V, MODE[1:0] = 10,

3.537

3.510

4.913

4.875

5.355

5.314

3.600

5.000

5.450

3.663

3.690

5.088

5.125

5.545

5.586

O_ACC

No Load, PWM Mode, T = −10°C to +50°C

PVIN = 2.5 V, MODE[1:0] = 10,

No Load, PWM Mode

PVIN = 3.8 V, MODE[1:0] = 01,

No Load, PWM Mode, T = −10°C to +50°C

PVIN = 3.8 V, MODE[1:0] = 01,

No Load, PWM Mode

PVIN = 3.8 V, MODE[1:0] = 11,

No Load, PWM Mode, T = −10°C to +50°C

PVIN = 3.8 V, MODE[1:0] = 11,

No Load, PWM Mode

Regulator

Switching Frequency

IL peak Current Limit

No Load, PVIN = 3.8 V

2.25

2.88

2.50

3.63

2.75

4.46

200

MHz

PVIN = 2.5 V, Open Loop (Note 6)

SWLIM

LIN

Soft−Start Input Linear

Current Limit

I/O Levels

Low−Level Input Voltage

High−Level Input Voltage

0.4

1.2

PVIN

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Min and Max limits are specified by design, test and/or statistical analysis.

5. Refer to Typical Characteristics waveforms/graphs for closed loop data and variation with input supply and temperature. Electrical

specifications reflect open loop steady state data.

6. Current Limit specifications is tested open loop, for typical close loop current limit data, refer to typical performance characteristics

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FAN48685

Table 7. SYSTEM SPECIFICATIONS (Note 7)

The following system specifications are guaranteed by designed and are not performed in production testing. Recommended operating

conditions, unless otherwise noted, PVIN = 2.5 V to VOUT – 200 mV, TA = 40°C to 85°C, VOUT = 5.45 V otherwise noted. Typical val-

ues are given PVIN = 3.8 V and TA = 25°C. System Specifications area based on circuit per Figure 1. L = 0.47 mH (0603 DFE1608CK−

R47M 70 mW/ 3.0 A) CIN = 10 uF (0402 C1005X5R0J106M050BC TDK) COUT = 2 x 22 uF (0402 GRM155R60J226ME11 MURATA.)

Symbol

Efficiency

Parameter

Conditions

Min

Typ

Max

Unit

Efficiency

VOUT = 5.45 V, IOUT = 100 mA

VOUT = 5.45 V, IOUT = 300 mA

VOUT = 5.45 V, IOUT = 500 mA

IOUT MAX

IOUT Max.

800

OUT

VOUT Regulation

LOAD

Load Regulation

Line Regulation

200 mA < IOUT < 600 mA, VOUT = 5.45 V

−5

mV/A

mV/V

REG

LINE

3.0 V < PVIN < 4.2 V , IOUT = 550 mA,

VOUT = 5.45 V

Output Ripple

VOUT Change

IOUT = 550 mA, VOUT = 5.45 V, PVIN = 3.8 V

IOUT = 450 mA, VOUT = 3.6 V, PVIN = 3.0 V

RIPPLE

VOUT Transitions

MODE[1:0] 00 > 01 to 95% of VOUT,

VOUT = Forced Pass−Through Mode > 5 V,

IOUT = 1 mA

150

100

1.5

200

SETTLE

MODE[1:0] 00 > 10 to 95% of VOUT,

VOUT = Forced Pass−Through Mode > 3.6 V,

IOUT = 1 mA, PVIN = 2.5 V to VOUT – 200 mV

Soft−Start

MODE[1:0] = 00, VOUT = PVIN (Start up into

Forced Pass−Through Mode)

Noise

en_bw

Output Noise Voltage

(Integrated)

VOUT = 5 V, IOUT = 550 mA,

Freq = 0 Hz to 200 kHz

140

750

500

300

VOUT = 5 V, IOUT = 550 mA,

Freq = 50 kHz to 2 MHz

VOUT = 5 V and 3.6 V, IOUT = 550 mA,

Freq = 13.5 MHz 200 kHz

Transients

Load Transient

IOUT = 10 mA ↔ 400 mA, T = T = 1 ms,

TRRP

VOUT = 5.45 V

TRRP

PVIN = 3.0 V ↔ 3.5 V, T = T = 10 ms,

IOUT = 550 mA, VOUT = 5.45 V

7. System Specifications are tested closed loop while using the recommended external components as listed on Table 1.

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FAN48685

Typical Performance Characteristics

Unless otherwise specified; PVIN = 3.8 V, VOUT =

C1005X5R0J106M050BC TDK) COUT = 2 x 22 mF (0402

GRM155R60J226ME11 MURATA), L = 0.47 mH (0603,

70 mW, DFE1608CK−R47M).

5.45 V, T = 25°C, and circuit and components according to

Figure 1.

Components:

CIN = 10 mF

(0402

Figure 3. Efficiency vs. Load Current and Input Voltage

Figure 4. Efficiency vs. Load Current and Temperature

Figure 5. Output Regulation vs. Load Current and

Input Voltage

Figure 6. Output Ripple vs. Load Current and Input

Voltage

Figure 7. Frequency vs. Load Current and Input

Voltage

Figure 8. Quiescent Current vs. Input Voltage and

Temperature

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FAN48685

Typical Performance Characteristics

Unless otherwise specified; PVIN = 3.8 V, VOUT =

C1005X5R0J106M050BC TDK) COUT = 2 x 22 mF (0402

GRM155R60J226ME11 MURATA), L = 0.47 mH (0603,

70 mW, DFE1608CK−R47M).

5.45 V, T = 25°C, and circuit and components according to

Figure 1.

Components:

CIN = 10 mF

(0402

Figure 9. Load Transient, 10 e 400 mA, 1 ms Edge

Figure 10. Line Transient, 3.0 V e 3.5 V, 10 ms Edge,

550 mA Load

Figure 11. VOUT Change: Forced PT to BOOST

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FAN48685

APPLICATION INFORMATION

Operation Description

Mode Transition

The FAN48685 is low−power boost regulator designed to

provide a minimum voltage regulated rail from a standard

single−cell Li−Ion battery. The device offers superior

features for NFC applications. PWM switching frequency is

maintain away from the sub carrier of NFC application

avoiding interference. The FAN48685 automatically goes to

100% duty cycle when the input voltage nears the output

voltage. The part can also be placed in forced pass through

mode by pulling both mode pins low.

Pass−Through to Boost Mode

When going from pass−through mode to boost mode,

initially there is a delay for the internal digital circuitry to

power up the analog circuitry. After, analog circuitry is

powered, the internal DAC will begin to start stepping from

2.45 V. As soon as the internal DAC step is greater than

PVIN, the VOUT of the device begins to increase until it

reaches its final VOUT target value. The device is designed

to transitions under no load, care should be taken in system

design to ensure the load is not applied during VOUT

transitions.

Startup Behavior

Startup Description

When going from boost mode to pass−through mode, the

output voltage decay will be determined by the amount of

load at the VOUT.

The device is designed to startup with no load allowing the

implementation of input current controls that support lower

capacity batteries without inducing brown out. Care should

be taken in the system design to ensure load is applied after

regulation has been reached and output capacitance is a

suitable value to avoid fault time−outs occurring. The device

can startup in either boost mode or forced pass−through

mode. When starting in boost mode, the part has a linear

mode which limits the battery current to 90 mA (typ.) to

avoid large inrush currents from the battery. In linear mode,

if VOUT fails to reach PVIN target within 1.5 ms, a fault

condition is declared and the device waits 20 ms to attempt

an automatic restart. Once VOUT charges up to PVIN, the

linear mode current limit is disabled and the output voltage

is ramped to the final value via the DAC that programs the

output.

Boost to Boost Mode

When going from boost mode to a higher VOUT boost

mode, the internal DAC starts its step from the current

VOUT until the final VOUT target. Since there is no latency

for the analog to be powered up, immediately after the DAC

stepping, the VOUT of the device begins to increase until it

reaches its final VOUT target value.

When going from boost mode to a lower VOUT boost

mode, the output voltage decay will be determined by the

amount of load at the VOUT.

Protection Features

VOUT Fault

During startup, if the VOUT fails to reach PVIN target

within 1.5 ms, the part declares a fault. Once the fault is

triggered, the regulator stops switching and presents a

high−impedance path between PVIN and VOUT.

When starting up in forced pass−through mode, the output

voltage is charged using the same linear mode mechanism

until VOUT reaches PVIN.

Modes of Operation

Current Limit Protection (OCP)

PWM Description

FAN48685 has a current limit feature, which protects

itself and load during overloading conditions. When the

inductor peak current is reached and held for 2 ms, the device

goes into a fault. The part restarts every 20 ms once fault

occurs.

During PWM mode, the output voltage is regulated by

switching at a constant frequency and then modulating the

energy per cycle to control the power to the load.

Forced Pass−Through Mode

When both mode pins are pulled low, the part will be

forced in pass−through mode. The output voltage is around:

VOUT = (PVIN − (IOUT* (DCR of L +HIGH SIDE FET

RDSON)) during this mode.

Thermal Shutdown Protection (TSP)

When the die temperature increases, due to a high load

condition and/or a high ambient temperature; the output

switching is disabled until the die temperature falls

sufficiently. The junction temperature at which the thermal

shutdown activates is nominally 150°C with a 15°C

hysteresis.

Automatic Pass−Through Mode

In normal operation, the device automatically transitions

from boost mode to pass−through mode if PVIN is within

about 150 mV of VOUT boost voltage. In pass−through

mode, the device has a low impedance path between PVIN

and VOUT. Entry into pass−through mode occurs when

PVIN is sufficiently close to VOUT that minimum on−time

persists for 16 cycles. In Automatic pass−through mode,

there is short−circuit protection which protects both the IC

and external components.

Automatic Pass−Through Mode Protection

During automatic pass−through mode, the device is

short−circuit protected, if the voltage difference between

PVIN and VOUT exceed more than 300 mV for 10 us, then

a fault is declared. The part will restart every 20 ms.

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FAN48685

Under−Voltage Lockout (UVLO)

Once PVIN reaches UVLO rising the part will begin to

switch and begin the startup process. When PVIN falls to

UVLO falling, the part stops switching and output voltage

starts decays to 0 V.

Control Pin Functionality

Table 8. MODE PINS FUNCTIONALITY (Note 8)

Mode 1

Mode 0

Status of Device

Forced Pass−Through Mode;

VOUT = PVIN

Active; VOUT = 5.00 V

Active; VOUT = 3.60 V

Active; VOUT = 5.45 V

8. Recommended to have logic levels transitions and fall times

typically at 100 ns. MODE Pins have smart pulls down of

300 kW (typ.) and are only activated when at logic LOW.

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FAN48685

ADDITIONAL APPLICATIONS INFORMATION

Application Guidelines

overload conditions. Saturation effects causes the inductor

current ripple to become higher under high loading, as only

the peak of the inductor current ripple is controlled.

Input Capacitor Considerations

The 10 mF ceramic 0402 (1005 metric) input capacitor

should be placed as close as possible between the PVIN pin

and GND to minimize the parasitic inductance. If a long wire

is used to bring power to the IC, additional “bulk”

capacitance (electrolytic or tantalum) should be placed (on

Evaluation board) between CIN and the power source lead

to reduce the ringing that can occur between the inductance

of the power source leads and CIN. The effective

capacitance value decreases as PVIN increases due to DC

bias effects.

Layout Considerations

The layout recommendations below highlight various

top−copper pours using different colors. To minimize spikes

at VOUT, COUT must be placed as close as possible to

PGND and VOUT, as shown in Figure 12.

For thermal reasons, it is suggested to maximize the pour

area for all planes other than SW. Especially the ground pour

should be set to fill all available PCB surface area and tied

to internal layers with a cluster of thermal vias.

Output Capacitor Considerations

The two 22 mF ceramic 0402 (1005 metric) output

capacitor should be placed as close as possible between the

VOUT pin and GND to minimize the parasitic inductance.

The effective capacitance value decreases as VOUT

increases due to DC bias effects. Therefore, a minimum 5 uF

capacitance is required to maintain stable regulation at the

output.

If the output capacitance is increased beyond the

recommended two 22 mF ceramic the system design should

be evaluated to ensure that the part does not enter fault state

or hiccup during start−up as the device charges the output

capacitance.

CIN

COUT

FAN48685

Inductor Considerations

The FAN48685 employs a peak current limiting, so peak

inductor current can reach 3.63 A for a short duration during

Figure 12. Recommended Layout

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WLCSP9 1.215x1.215x0.581

CASE 567QW

ISSUE B

DATE 24 FEB 2023

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON13355G

WLCSP9 1.215x1.215x0.581

PAGE 1 OF 1

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

FAN48685UC08X [ONSEMI]

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