FAN53527UC84X [ONSEMI]
3.0A Step Down Switching Voltage Regulator;
| 型号： | FAN53527UC84X |
| 厂家： | 
ONSEMI |
| 描述： | 3.0A Step Down Switching Voltage Regulator |
| 文件： | 总21页 (文件大小：688K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Buck Regulator, 3.0 A
FAN53527
Descriptions
The FAN53527 is a step−down switching voltage regulator with an
input voltage supply range of 2.5 V to 5.5 V. Device settings can be
2
programmed through an I C interface, or the IC can be operated in
stand−alone mode with pin controls for enable, output voltage, and
Auto PFM or Forced PWM operation.
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Using a proprietary architecture with synchronous rectification, the
FAN53527 is capable of delivering 3.0 A continuous at over 80%
efficiency, and maintain that efficiency with load currents as low as
10 mA. At moderate and light loads, Pulse Frequency Modulation
(PFM) is used to operate in Power−Save Mode where excellent
transient response is maintained. In Shutdown Mode, the supply
current drops below 1 mA, further reducing power consumption. At
higher loads, the device automatically transitions to fixed−frequency
PWM control, operating typically at 2.4 MHz.
WLCSP−15
CASE 567QS
MARKING DIAGRAM
1
2
K
Y
K
Z
Pin−1
Mark
X
The FAN53527 is available in a 15−bump, 1.310 mm x 2.015 mm,
0.4 mm ball pitch, Wafer−Level Chip−Scale Package (WLCSP).
12
KK
X
Y
Z
= Alphanumeric Device Marking
= Lot Run Code
= Alphabetical Year Code
= 2−Weeks Date Code
= Assembly Plant Code
Features
2
• I C Compatible Interface or Stand−Alone Operation
• Fixed−Frequency PWM Operation: 2.4 MHz
• Auto PFM Mode for High Efficiency at Light−Load
• Best−in−Class Load Transient Response
• Wide Input Voltage Range: 2.5 V to 5.5 V
• Continuous Output Current Capability: 3.0 A
• Low Quiescent Current: 48 mA
VIN
SW
L1
CIN CBYP
VOUT
COUT1 COUT2
FAN53527
EN
VSEL
SCL
SDA
• Low Shutdown Current: <1 mA
MODE
• Input Under−Voltage Lockout (UVLO)
• Thermal Shutdown and Overload Protection
• Programmable/ Selectable Output Voltage:
AGND
PGND
2
Figure 1. Typical Application
♦ 1 V to 1.39375 V in 6.25 mV Steps (I C Programmable)
♦ 1.125 V & 1.081 V (Pin Selectable Values)
• Programmable Output Voltage Transition Slew Rate
ORDERING INFORMATION
See detailed ordering and shipping information on
page 2 of this data sheet.
Applications
• Application, Graphic, and DSP Processors
• Hard Disk Drives, LPDDR4, LPDDR5
• Smart Phones
• Gaming Devices
• Tablets, Netbooks, Ultra−Mobile PCs
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
December, 2019 − Rev. 0
FAN53527/D
FAN53527
Table 1. ORDERING INFORMATION
Power−Up Defaults
DVS Range / Step
Temperature
Range
Device
Marking
VSEL0
VSEL1
Size
Part Number
Package
Packing Method
FAN53527UC84X
1.125 V
1.081 V
1.000 V to
1.39375 V / 6.25 mV
−40 to 85_C
WLCSP
Tape & Reel
LQ
Table 2. RECOMMENDED EXTERNAL COMPONENTS
Voltage
Rating
Component
Manufacturer
TDK
Part Number
Value
4.7 mF
Case Size
C
C1608X5R1A475K
0603
0603/1608 (1.6 mm x 0.8 mm)
0201
10 V
10 V
6.3 V
IN
OUT1/2
C
Murata
Murata
Toko
GRM188R61A226ME15D
GRM033R60J104KE19D
DFE201612E−R47N
2 x 22 mF
0.1 mF
C
BYP
L1
0.47 mH
ISAT = 6.1 A
DCR = 21 mW
0805/2012 (2.0 mm x 1.2 mm) Max
Height: 0.8 mm
Table 3. RECOMMENDED ALTERNATE COMPONENTS
Voltage
Rating
Component
Manufacturer
Murata
Part Number
Value
Case Size
C
GRM188R60J476ME15
CLIGT2016URM47MNE
2 x 47 mF
0603/1608 (1.6 mm x 0.8 mm)
2.0 x 1.6 x 1.0 mm
6.3 V
OUT1/2
L1
SEMCO
0.47 mH
ISAT = 4.0 A
DCR = 30 mW
NOTE:
C
is optional and used to filter any high frequency component on VIN bus.
BYP
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2
FAN53527
PIN CONFIGURATION
VIN
A1
SW
A2
PGND
A3
A3
B3
C3
D3
E3
A2
B2
C2
D2
E2
A1
B1
C1
D1
E1
VIN
B1
SW
B2
PGND
B3
VIN
C1
MODE
C2
AGND
C3
VSEL
D1
EN
D2
SDA
D3
AGND
E1
SCL
E2
VOUT
E3
Top View
Bottom View
Figure 2. Pin Configuration
Table 4. PIN DEFINITIONS
Pin
Name
Description
A1, B1, C1
VIN
Input Voltage
Power input to converter. Place input decoupling capacitor, CIN, as close to this pin as
A2, B2
A3, B3
SW
Switching Node
Connect to one side of the inductor.
PGND
Power Ground
The low−side MOSFET is referenced to this pin. CIN and COUT should be returned to this pin with mini-
mal path resistance.
C3
E2
D3
E3
D1
AGND
SCL
Analog Ground
Ground pin for control circuitry.
Serial Interface Clock
2
I C Clock input pin. Avoid routing near noise sensitive traces.
SDA
Serial Interface Data
2
I C input/output data line pin. Do not leave this pin floating.
VOUT
VSEL
Output Voltage Feedback
Connect to positive side of output capacitor.
Output Voltage Selection
Selects between registers VSEL0 or VSEL1 programmed voltages.
LOW = VSEL0 and HIGH = VSEL1.
C2
MODE
PFM/PWM MODE
Selects between Automatic PFM/PWM (Auto PFM) operation and Forced PWM operation.
LOW = Auto PFM/PWM and HIGH = Forced PWM.
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3
FAN53527
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Voltage on SW, VIN Pins
Parameter
Min
−0.3
−0.3
−0.3
−0.3
−0.3
Max
7.0
Unit
V
IN
IC Not Switching
IC Switching
V
5.0
Voltage on EN Pin
VIN (Note 1)
VIN (Note 1)
5.0
Voltage on All Other Pins
Voltage on VOUT Pin
IC Not Switching
V
OUT
V
V/ms
V
V
Maximum Slew Rate of V > 6.5V, PWM Switching
100
INOV_SLEW
IN
ESD
Human Body Model, ANSI/ESDA/JEDEC JS−001−2012
Charged Device Model per JESD22−C101
Junction Temperature
2000
1000
T
J
−40
−65
+150
+150
+260
°C
°C
°C
T
STG
Storage Temperature
T
L
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Lesser of 7V or V + 0.3 V.
IN
Table 6. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.5
0
Typ
Max
5.5
Unit
V
V
IN
Supply Voltage Range
Output Current
I
3.0
A
OUT
T
Operating Ambient Temperature
Operating Junction Temperature
−40
−40
+85
+125
°C
°C
A
T
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 7. THERMAL PROPERTIES
Symbol
Parameter
Min
Typ
Max
Unit
θ
JA
Junction−to−Ambient Thermal Resistance
42
°C/W
NOTE: Junction−to−ambient thermal resistance is a function of application and board layout. This data is simulated with four−layer 2s2p
boards with vias in accordance to JESD51− JEDEC standard. Special attention must be paid not to exceed the junction
temperature T
at a given ambient temperate T .
J(max)
A
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FAN53527
Table 8. ELECTRICAL CHARACTERISTICS Minimum and maximum values are at V = 3.6 V, T = −40°C to +85°C, unless
IN
A
otherwise noted. Typical values are at T = 25°C, V = 3.6 V, and V
= 1.081 V.
A
IN
OUT
Symbol
Parameter
Condition
Min
Typ
Max
Unit
POWER SUPPLIES
I
Quiescent Current
EN Pin = V , Auto PFM, No Load
48
13
mA
mA
mA
Q
IN
EN Pin = V , Forced PWM, No Load
IN
I
H/W Shutdown Supply Current
Sleep
EN Pin = GND, SDA/SCL = V or
0.1
3.0
3.0
SD
IN
GND, 2.5 V ≤ V ≤ 5.5 V
IN
EN Pin = V , [BUCK_ENx] = “0”, SDA/
0.1
mA
IN
SCL = V or GND, 2.5 V ≤ V ≤ 5.5 V
IN
IN
V
Under−Voltage Lockout Threshold
Under−Voltage Lockout Hysteresis
V
IN
Rising
2.32
350
2.45
V
UVLO
V
mV
UVHYST
EN, VSEL, MODE, SDA, SCL
V
high−Level Input Voltage
low−Level Input Voltage
Input Bias Current
2.5 V ≤ V ≤ 5.5 V
1.1
V
V
IH
IN
V
2.5 V ≤ V ≤ 5.5 V
0.4
1
IL
IN
I
IN
Input Tied to GND or VIN
0.01
mA
V
OUT
REGULATION
V
REG
Output Voltage Accuracy (Note 2)
Auto PFM, V
OUT
= 1.0000 to 1.39375 V,
−2.5
−1.5
2.5
1.5
%
OUT
I
= 0 to 3 A, 2.5 V ≤ V ≤ 5.5 V
IN
Forced PWM, V
= 1.0000 to
OUT
1.39375 V, I
= 0 to 3A, 2.5 V ≤ V
OUT
IN
≤ 5.5 V
DV
/ DI
Load Regulation (Note 2)
Line Regulation (Note 2)
Transient Response (Note 2)
I = 1 A to 3 A
OUT
0.02
0.02
15
%/A
%/V
mV
OUT
LOAD
DV
/ DV
2.5 V ≤ V ≤ 5.5 V, I
= 1 A
OUT
IN
IN
OUT
V
I
r
Step 1 mA ⇔ 500 mA,
TRSP
LOAD
t = t = 100 ns, Forced PWM
f
I
r
Step 1 mA ⇔ 500 mA,
19
60
70
LOAD
t = t = 100 ns, Auto PFM
f
I
Step 1 mA ⇔ 3 A,
LOAD
t = t = 100 ns, Forced PWM
r
f
I
Step 1 mA ⇔ 3 A,
LOAD
t = t = 100 ns, Auto PFM
r
f
POWER SWITCH / PROTECTION
I
P−MOS Peak Current Limit
Thermal Shutdown
4.00
5.50
4.75
150
17
5.50
A
°C
°C
V
LIMPK
T
LIMIT
HYST
SDWN
T
Thermal Shutdown Hysteresis
Input OVP Shutdown
V
Rising Threshold
Falling Threshold
6.15
5.73
DAC
Resolution
7
Bits
Differential Nonlinearity (Note 2)
0.5
LSB
SOFT−START
t
SS
Regulator Enable to Regulated V
R > 5W, From EN Rising Edge to
LOAD
75
ms
OUT
95% V
and C
= 2x22 mF
OUT
OUT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by Design. Characterized on the ATE or Bench.
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FAN53527
Table 9. I2C TIMING SPECIFICATIONS Minimum and maximum values are at V = 3.6 V, T = −40°C to +85°C, unless otherwise
IN
A
noted. Typical values are at T = 25°C, V = 3.6 V, and V
= 1.081 V. Guaranteed by Design.
A
IN
OUT
Symbol
Parameter
Condition
Min
Typ
Max
Unit
POWER SUPPLIES
Standard Mode
Fast Mode
100
400
Fast Mode Plus
1000
3400
1700
f
SCL Clock Frequency
kHz
SCL
High−Speed Mode, C ≤ 100 pF
B
High−Speed Mode, C ≤ 400 pF
B
Standard Mode
Fast Mode
4.7
1.3
0.5
4
Bus−Free Time between STOP and
ms
ms
ns
t
BUF
START Conditions
Fast Mode Plus
Standard Mode
Fast Mode
600
260
160
4.7
1.3
0.5
160
320
4
START or REPEATED START
Hold Time
t
HD;STA
Fast Mode Plus
High−Speed Mode
Standard Mode
Fast Mode
ms
Fast Mode Plus
t
SCL LOW Period
SCL HIGH Period
LOW
High−Speed Mode, C ≤ 100 pF
B
ns
High−Speed Mode, C ≤ 400 pF
B
Standard Mode
Fast Mode
ms
600
260
60
Fast Mode Plus
t
HIGH
ns
High−Speed Mode, C ≤ 100 pF
B
High−Speed Mode, C ≤ 400 pF
120
4.7
600
260
160
250
100
50
B
Standard Mode
Fast Mode
ms
t
t
Repeated START Setup Time
Data Setup Time
SU;STA
Fast Mode Plus
High−Speed Mode
Standard Mode
Fast Mode
ns
ns
SU;DAT
Fast Mode Plus
High−Speed Mode
Standard Mode
Fast Mode
10
0
0
0
0
0
3.45
900
450
70
ms
Fast Mode Plus
t
Data Hold Time
SCL Rise Time
HD;DAT
ns
High−Speed Mode, C ≤ 100 pF
B
High−Speed Mode, C ≤ 400 pF
150
1000
300
120
80
B
Standard Mode
Fast Mode
20+0.1C
B
20+0.1C
20+0.1C
B
Fast Mode Plus
t
ns
B
RCL
High−Speed Mode, C ≤ 100 pF
10
B
High−Speed Mode, C ≤ 400 pF
20
160
B
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FAN53527
Table 9. I2C TIMING SPECIFICATIONS Minimum and maximum values are at V = 3.6 V, T = −40°C to +85°C, unless otherwise
IN
A
noted. Typical values are at T = 25°C, V = 3.6 V, and V
= 1.081 V. Guaranteed by Design.
A
IN
OUT
Symbol
Parameter
Condition
Min
Typ
Max
Unit
POWER SUPPLIES
Standard Mode
Fast Mode
20+0.1C
300
300
120
40
B
20+0.1C
B
Fast Mode Plus
20+0.1C
t
SCL Fall Time
ns
ns
ns
B
FCL
High−Speed Mode, C ≤ 100 pF
10
B
High−Speed Mode, C ≤ 400 pF
20
10
20
80
B
High−Speed Mode, C ≤ 100 pF
80
B
Rise Time of SCL After a REPEATED
START Condition and After ACK Bit
t
RCL1
High−Speed Mode, C ≤ 400 pF
160
1000
300
120
80
B
Standard Mode
Fast Mode
20+0.1C
20+0.1C
20+0.1C
B
B
Fast Mode Plus
t
SDA Rise Time
SDA Fall Time
B
RDA
High−Speed Mode, C ≤ 100 pF
10
B
High−Speed Mode, C ≤ 400 pF
20
160
300
300
120
80
B
Standard Mode
Fast Mode
20+0.1C
20+0.1C
20+0.1C
B
B
Fast Mode Plus
t
ns
B
FDA
High−Speed Mode, C ≤ 100 pF
10
B
High−Speed Mode, C ≤ 400 pF
20
4
160
B
Standard Mode
Fast Mode
ms
600
120
160
t
Stop Condition Setup Time
SU;STO
Fast Mode Plus
High−Speed Mode
ns
C
Capacitive Load for SDA and SCL
400
pF
B
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FAN53527
Timing Diagrams
tF
tSU;STA
tBUF
SDA
tR
TSU;DAT
tHD;STO
tHIGH
tHD;DAT
SCL
tLOW
tHD;STA
tHD;STA
REPEATED
START
START
STOP
START
Figure 3. I2C Interface Timing for Fast Plus, Fast, and Slow Modes
REPEATED
START
STOP
tFDA
tRDA
tSU;DAT
SDAH
tSU;STA
tRCL1
tFCL
tHIGH
tHD;DAT
note A
tRCL
tSU;STO
SCLH
tLOW
tHD;STA
REPEATED
START
= MCS Current Source Pull−up
= RP Resistor Pull−up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 4. I2C Interface Timing for High−Speed Mode
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FAN53527
TYPICAL CHARACTERISTICS
Unless otherwise specified; circuit per Typical Application using Recommended External Components,
T = 25°C, V = 3.6 V, V
= 1.081 V, Auto PFM Mode
A
IN
OUT
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
3.0Vin
3.6Vin
3.8Vin
4.35Vin
4.6Vin
−40°C
+25°C
+85°C
1
10
100
Load Current (mA)
1000
1
10
100
1000
Load Current (mA)
Figure 5. Efficiency versus Load Current and Input
Voltage
Figure 6. Efficiency versus Load Current and
Temperature
1.1
1.09
1.08
900
800
700
600
500
400
300
200
4.35Vin
1.07
1.06
1.05
3.8Vin
3.6Vin
3.0Vin
PWM Entry
PFM Entry
0
500
1000
1500
2000
2500
3000
2.8
3.3
3.8
4.3
4.8 5.3
Load Current (mA)
Input Voltage (V)
Figure 7. Output regulation versus Load Current and
Input Voltage
Figure 8. PWM/PFM Entry Level versus Input Voltage
3000
45
40
35
30
25
20
15
10
5
4.35Vin Auto
3.6Vin Auto
2500
2000
1500
1000
500
4.35Vin FPWM
3.6Vin FPWM
3.6Vin FPWM
4.35Vin FPWM
3.6Vin Auto
4.35Vin Auto
0
0
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
Load Current (mA)
Load Current (mA)
Figure 9. Frequency versus Load Current versus
Auto PFM and Forced PWM
Figure 10. Output Ripple versus Load Current
versus Auto PFM and Forced PWM
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FAN53527
TYPICAL CHARACTERISTICS
Unless otherwise specified; circuit per Typical Application using Recommended External Components,
T = 25°C, V = 3.6 V, V = 1.081 V, Auto PFM Mode
A
IN
OUT
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
+85°C
+25°C
−40°C
+85°C
+25°C
−40°C
2.8
3.3
3.8
4.3
4.8
5.3
2.8
3.3
3.8
4.3
4.8
5.3
Input Voltage (V)
Input Voltage (V)
Figure 11. Quiescent Current versus Input Voltage
and Temperature in Forced PWM
Figure 12. Quiescent Current versus Input Voltage
and Temperature in Auto PFM
3.6V DC Offset
V
EN
1V DC Offset
Figure 13. Line Transient, 3.6 Ve4.2 V, 1A,
Figure 14. Start−Up into 5.4 kW Load
10 ms Edge
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FAN53527
TYPICAL CHARACTERISTICS
Unless otherwise specified; circuit per Typical Application using Recommended External Components,
T = 25°C, V = 3.6 V, V = 1.081 V, Auto PFM Mode
A
IN
OUT
1V DC Offset
1V DC Offset
Figure 15. Load Transient, 1 mAe500 mA,
Figure 16. Load Transient, 1 mAe500 mA,
100 ns Edge, Forced PWM
100 ns Edge, Auto PFM
1V DC Offset
1V DC Offset
Figure 17. Load Transient, 1 mAe3 A, 100 ns Edge,
Figure 18. Load Transient, 1 mAe3 A, 100 ns Edge,
Forced PWM
Auto PFM
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FAN53527
Operating Description
VSEL pin or simply by setting the MODE pin high. See
Table 2.
The FAN53527 is a step−down switching voltage
regulator that delivers a programmable output voltage from
an input voltage supply of 2.5 V to 5.5 V. Using a proprietary
architecture with synchronous rectification, the FAN53527
is capable of delivering 3.0 A at over 80% efficiency. The
regulator operates at a nominal frequency of 2.4 MHz at full
load, which reduces the value of the external components to
330 nH or 470 nH for the output inductor and 44 μF for the
output capacitor. High efficiency is maintained at light load
with single−pulse PFM.
Enable and Soft−Start
When the EN pin is LOW; the IC is shut down, all internal
circuits are off, and the part draws very little current. In this
2
state, I C can be written to or read from as long as input
voltage is above the UVLO. The registers keep the content
when the EN pin is LOW. The registers are reset to default
values during a Power On Reset (POR). When the
OUTPUT_DISCHARGE bit in the Control register is
enabled (logic HIGH) and the EN pin is LOW or the
BUCK_ENx bit is LOW, an 11 W load is connected from
VOUT to GND to discharge the output capacitors.
Raising EN while the BUCK_ENx bit is HIGH activates
the part and begins the soft−start cycle. During soft−start, the
modulator’s internal reference is ramped slowly to minimize
surge currents on the input and prevent overshoot of the
output voltage. Synchronous rectification is inhibited,
allowing the IC to start into a pre−charged capacitive load.
If large values of output capacitance are used, the
2
An I C−compatible interface allows transfers up to
3.4 Mbps. This communication interface can be used to:
• Dynamically re−program the output voltage in 6.25 mV
increments;
• Reprogram the mode to enable or disable PFM;
• Control voltage transition slew rate; or
• Enable / disable the regulator
Control Scheme
The FAN53527 uses
a
proprietary non−linear,
regulator may fail to start. The maximum C
capacitance
OUT
fixed−frequency PWM modulator to deliver a fast load
transient response, while maintaining a constant switching
frequency over a wide range of operating conditions. The
regulator performance is independent of the output
capacitor ESR, allowing for the use of ceramic output
capacitors. Although this type of operation normally results
in a switching frequency that varies with input voltage and
load current, an internal frequency loop holds the switching
frequency constant over a large range of input voltages and
load currents.
For very light loads, the FAN53527 operates in
Discontinuous Current Mode (DCM) single−pulse PFM,
which produces low output ripple compared with other PFM
architectures. Transition between PWM and PFM is
relatively seamless, providing a smooth transition between
DCM and CCM Modes.
for starting with a heavy constant−current load is
approximately:
320m
COUTMAX [ (ILMPK * ILOAD) @
(eq. 1)
VOUT
where C
is expressed in μF and I
is the
OUTMAX
LOAD
load current during soft−start, expressed in A.
If the regulator is at its current limit for 16 consecutive
current limit cycles, the regulator shuts down and enters
tri−state before reattempting soft−start 1700 ms later. This
limits the duty cycle of full output current during soft−start
to prevent excessive heating.
The IC allows for software enable of the regulator, when
EN is HIGH, through the BUCK_EN bits. BUCK_EN0 and
BUCK_EN1 are both set to “1” by default. These options
start after a POR, regardless of the state of the VSEL pin.
PFM can be disabled by programming the MODE bits in
the CONTROL register in combination with the state of the
Table 10. HARDWARE AND SOFTWARE ENABLE
Control Pins
BUCK_ENx Bits
EN
0
VSEL
MODE
BUCK_EN0
BUCK_EN1
Mode Bits
XX
Operation
Shutdown
V
OUT
X
X
0
0
1
1
0
0
1
1
X
X
0
0
0
0
X
1
X
1
X
0
1
1
X
X
0
1
X
X
X
0
X
X
1
1
X
X
0
1
N/A
N/A
1
XX
Shutdown
1
X0
Auto PFM
NSEL0
NSEL0
NSEL1
NSEL1
N/A
1
X1
Forced PWM
Auto PFM
1
0X
1
1X
Forced PWM
Shutdown
1
XX
1
XX
Forced PWM
Shutdown
NSEL0
N/A
1
XX
1
XX
Forced PWM
NSEL1
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12
FAN53527
VSEL Pin and I2C Programming Output Voltage
The output voltage is set by the NSELx control bits in
VSEL0 and VSEL1 registers. The output is given as:
VSEL0 and VSEL HIGH corresponds to VSEL1. Upon
POR, VSEL0 and VSEL1 are reset to their default voltages,
as shown in Table 1.
ƪ ƫ
( )
OUT + 1.000 V ) NSELx * 64 @ 6.25 mV
(eq. 2)
V
Transition Slew Rate Limiting
When transitioning from a low to high voltage, the IC can
be programmed for one of eight possible slew rates using the
SLEW bits in the Control register, as shown in the table
below.
For example, if NSEL =1010000 (80 decimal), then V
= 1.000 + 0.100 = 1.100 V.
Output voltage can also be controlled by toggling the
VSEL pin LOW or HIGH. VSEL LOW corresponds to
OUT
Table 11. TRANSITION SLEW RATE
Decimal
Bin
000
001
010
011
100
101
110
111
Slew Rate
0
1
2
3
4
5
6
7
64.00
32.00
16.00
8.00
mV/ms
mV/ms
mV/ms
mV/ms
mV/ms
mV/ms
mV/ms
mV/ms
4.00
2.00
1.00
0.50
Thermal Shutdown
Transitions from high to low voltage rely on the output
When the die temperature increases, due to a high load
condition and/or high ambient temperature, the output
switching is disabled until the die temperature falls
sufficiently. The junction temperature at which the thermal
shutdown activates is nominally 150°C with a 17°C hysteresis.
load to discharge V
to the new set point. Once the
OUT
high−to−low transition begins, the IC stops switching until
has reached the new set point.
V
OUT
Under−Voltage Lockout (UVLO)
When EN is HIGH, the under−voltage lockout keeps the
part from operating until the input supply voltage rises
HIGH enough to properly operate. This ensures proper
operation of the regulator during startup or shutdown.
Monitor Register (Reg05)
The Monitor register indicates of the regulation state of
the IC. If the IC is enabled and is regulating, its value is
(1000 0001).
Input Over−Voltage Protection (OVP)
I2C Interface
When V exceeds V
(~ 6.2 V), the IC stops
IN
SDWN
The serial interface is compatible with Standard, Fast,
switching to protect the circuitry from internal spikes above
6.5 V. An internal filter prevents the circuit from shutting
down due to noise spikes.
2
Fast Plus, and HS Mode I C BusR specifications. The SCL
line is an input and its SDA line is a bi−directional
open−drain output; it can only pull down the bus when
active. The SDA line only pulls LOW during data reads and
when signaling ACK. All data is shifted in MSB (bit 7) first.
Current Limiting
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum current
threshold is reached in the high−side switch. Upon reaching
this point, the high−side switch turns off, preventing high
currents from causing damage. 16 consecutive current limit
cycles in current limit, cause the regulator to shut down and
stay off for about 1700 ms before attempting a restart.
I2C Slave Address
The slave address uses the standard 7 most significant bits
for defining the address and the LSB as the read/write bit. In
doing so, the first word consists of bit [7:5] and the second
word utilizes bits [4:1]. Thus the slave address is 60. Other
slave addresses can be assigned. Contact an
On Semiconductor representative.
Table 12. I2C SLAVE ADDRESS
Bits
7
6
5
4
3
2
1
0
Address
60
1
1
0
0
0
0
0
X
Other slave addresses can be assigned. Contact an ON Semiconductor representative.
www.onsemi.com
13
FAN53527
Bus Timing
During a read from the FAN53527, the master issues a
REPEATED START after sending the register address and
before resending the slave address. The REPEATED
START is a 1 to 0 transition on SDA while SCL is HIGH, as
shown in Figure 22.
As shown in Figure 19 data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow sufficient time for the data to set up before
the next SCL rising edge.
Slave Releases
tSU;STA
tHD;STA
Data change allowed
ACK(0) or
NACK(1)
SLADDR
MS Bit
SDA
SCL
SDA
Figure 22. REPEATED START Timing
tH
tSU
High−Speed (HS) Mode
SCL
The protocols for High−Speed (HS), Low−Speed (LS),
and Fast−Speed (FS) Modes are identical; except the bus
speed for HS Mode is 3.4 MHz. HS Mode is entered when
the bus master sends the HS master code 00001XXX after
a START condition (Figure 20). The master code is sent in
Fast or Fast−Plus Mode (less than 1 MHz clock); slaves do
not ACK this transmission.
Figure 19. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 20.
The master generates a REPEATED START condition
(Figure 22) that causes all slaves on the bus to switch to HS
tHD;STA
Slave Address
MS Bit
SDA
2
Mode. The master then sends I C packets, as described
above, using the HS Mode clock rate and timing.
SCL
The bus remains in HS Mode until a STOP bit (Figure 21)
is sent by the master. While in HS Mode, packets are
separated by REPEATED START conditions (Figure 22).
Figure 20. START Bit
A transaction ends with a STOP condition, defined as
SDA transitioning from 0 to 1 with SCL high, as shown in
Figure 21.
Read and Write Transactions
The following figures outline the sequences for data read
and write. Bus control is signified by the shading of the
packet, defined as:
Slave Releases
Master Drives
tHD;STO
Master Drives Bus
ACK(0) or
NACK(1)
•
•
and
SDA
SCL
Slave Drives Bus
All addresses and data are MSB first.
Figure 21. STOP Bit
Table 13. I2C BIT DEFINITIONS FOR FIGURE 23 AND FIGURE 24
Symbol
Definition
S
P
R
A
A
START, see Figure 20
STOP, see Figure 21
REPEATED START, see Figure 22
ACK. The slave drives SDA to 0 acknowledge the preceding packet.
NACK. The slave sends a 1 to NACK the preceding packet.
0
0
0
7 bits
8 bits
8 bits
Data
S
Slave Address
0
A
Reg Addr
A
A
P
Figure 23. Write Transaction
0
0
0
1
7 bits
Slave Address
8 bits
Reg Addr
7 bits
8 bits
Data
S
0
A
A
R
Slave Address
1
A
A
P
Figure 24. Write Transaction Followed by a Read Transaction
www.onsemi.com
14
FAN53527
REGISTER DESCRIPTION
Table 14. REGISTER MAP
Hex
Address
Name
VSEL0
VSEL1
Function
Default
11010100
11001101
00
01
Controls V
Controls V
settings when VSEL pin = LOW
settings when VSEL pin = HIGH
OUT
OUT
Determines whether V
of positive transitions
output discharge is enabled and also the slew rate
OUT
02
CONTROL
10000000
03
04
05
ID1
ID2
Read−only register identifies vendor and chip type
Read−only register identifies die revision
Indicates device status
10000101
00000000
00000000
MONITOR
Table 15. BIT DEFINITIONS
Bit
Name
Type
Default
Description
VSEL0
Register Address: 00
Software buck enable. When EN pin is LOW, the regulator is
off. When EN pin is HIGH, BUCK_EN bit takes precedent.
7
BUCK_EN0
NSEL0
R/W
R/W
1
1010100
Sets the V
value for VSEL0 setting. V
= 1.000 +
OUT
OUT
6.25 mV * (d−64); where d is the decimal value of NSEL0 from
6:0
64 to 255.
VSEL1
Register Address: 01
Software buck enable. When EN pin is LOW, the regulator is
off. When EN pin is HIGH, BUCK_EN bit takes precedent.
7
BUCK_EN1
NSEL1
R/W
R/W
1
1001101
Sets the V
value for VSEL1 setting. V
= 1.000 +
OUT
OUT
6.25 mV * (d−64); where d is the decimal value of NSEL1 from
6:0
64 to 255.
CONTROL
Register Address: 02
0
1
The internal pull−down is not enabled when the converter is
disabled
7
OUTPUT_ DISCHARGE
R/W
R/W
The internal pull−down will be activated when the converter is
disabled
Sets the slew rate for positive voltage transitions. Refer to the
Transition Slew Rate Limiting section for details.
6:4
3
SLEW
Reserved
RESET
000
0
0
Always reads back 0.
R/W
R/W
Setting to 1 resets all registers to default values. Always reads
back 0.
2
In combination with the VSEL and MODE pin, the MODE bits
configure the buck to operate in either Auto PFM or Forced
PWM Mode. The bits are don’t−care if the Mode pin is high.
1:0
MODE
00
Refer to the Hardware and Software Enable table for details.
ID1
Register Address: 03
7:5
VENDOR
Reserved
DIE_ID
R
R
R
100
0
Signifies On Semiconductor as the IC vendor.
Always reads back 0.
4
3:0
0101
DIE ID − FAN53527
ID2
Register Address: 04
7:4
Reserved
DIE_REV
R
R
0000
0000
Always reads back 0000
3:0
FAN53527 Die Revision
MONITOR
7
Register Address: 05
PGOOD
R
0
1: Buck is enabled and soft−start is completed.
www.onsemi.com
15
FAN53527
Table 15. BIT DEFINITIONS
Bit
Name
Type
Default
Description
MONITOR
Register Address: 05
6
5
UVLO
OVP
R
R
R
0
0
0
1: Signifies VIN is less than the UVLO threshold.
1: Signifies VIN is greater than the OVP threshold.
1: Signifies a positive voltage transition is in progress and the
output voltage has not yet reached its new setpoint.
4
POS
This bit is set to “1” during IC soft−start.
R
R
0
0
1: Signifies a negative voltage transition is in progress and the
output voltage has not yet reached its new setpoint.
This bit is set to “1” during IC soft−start.
3
2
NEG
1: Indicates that a register reset was performed. This bit is
cleared after register 5 is read.
RESET−STAT
1
0
OT
R
R
0
0
1: Signifies the thermal shutdown is active.
1: Buck enabled; 0 buck disabled.
BUCK_STATUS
APPLICATION INFORMATION
Selecting the Inductor
The output inductor must meet both the required
inductance and the energy−handling capability of the
application. The inductor value affects the average current
limit, the output voltage ripple, and the efficiency.
The ripple current (ΔI) of the regulator is:
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current.
Inductor Current Rating
VOUT
VIN*VOUT
The current-limit circuit can allow substantial peak
currents to flow through L1 under worst−case conditions. If
it is possible for the load to draw such currents, the inductor
should be capable of sustaining the current or failing in a safe
manner.
@ ǒ Ǔ
DI [
(eq. 3)
VIN
L @ fSW
The maximum average load current, I
is
MAX(LOAD),
related to the peak current limit, I
current such that:
by the ripple
LIM(PK)
,
DI
2
IMAX(LOAD) + ILIM(PK)
*
Output Capacitor and VOUT Ripple
(eq. 4)
Increasing C
has negligible effect on loop stability
OUT
The FAN53527 is optimized for operation with
L = 470 nH, but is stable with inductances up to 1.0 μH
(nominal). The inductor should be rated to maintain at least
and can be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, DV
is calculated by:
,
OUT
80% of its value at I
. Failure to do so decreases the
LIM(PK)
f
SW @ COUT @ ESR2
2 @ D @ (1 * D)
1
amount of DC current the IC can deliver.
+ DI ƪ
ƫ
DVOUT
)
(eq. 6)
L
8 @ fSW @ COUT
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since ΔI increases, the
RMS current increases, as do core and skin−effect losses:
where C
is the effective output capacitance.
OUT
The capacitance of C
decreases at higher output
OUT
voltages, which results in higher DV
. Equation 6 is only
OUT
DI2
12
2
valid for CCM operation, which occurs in PWM Mode.
The FAN53527 can be used with either 2 x 22 mF (0603)
or 2 x 47 mF (0603) output capacitor configuration. If a
tighter ripple and transient specification is need from the
FAN53527, then the 2 x 47 mF is recommended.
+ Ǹ
IRMS
IOUT(DC)
)
(eq. 5)
The increased RMS current produces higher losses
through the R
ESR.
of the IC MOSFETs and the inductor
DS(ON)
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current.
The lowest DV
is obtained when the IC is in PWM
OUT
Mode and, therefore, operating at 2.4 MHz. In PFM Mode,
is reduced, causing DV to increase.
f
SW
OUT
ESL Effects
The increased RMS current produces higher losses
The Equivalent Series Inductance (ESL) of the output
capacitor network should be kept low to minimize the
through the R
ESR.
of the IC MOSFETs and the inductor
DS(ON)
www.onsemi.com
16
FAN53527
square−wave component of output ripple that results from
the division ratio C ESL and the output inductor (L ).
The square−wave component due to the ESL can be
2. Calculate total power dissipation using:
OUT
OUT
1
ǒ Ǔ
* 1
PT + VOUT @ ILOAD
@
(eq. 8)
(eq. 9)
h
estimated as:
3. Estimate inductor copper losses using:
ESLCOUT
PL + ILOAD2 @ DCRL
(eq. 7)
DVOUT(SQ) [ VIN
@
L1
4. Determine IC losses by removing inductor losses
(step 3) from total dissipation:
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired C value.
OUT
PIC + PT * PL
(eq. 10)
To minimize ESL, use capacitors with the lowest ratio of
length to width. Placing additional small−value capacitors
near the load also reduces the high−frequency ripple
components.
5. Determine device operating temperature:
DT + PIC @ QJA TIC + TA ) DT
(eq. 11)
and
Note that the R
linearly with temperature at about 1.4%/°C. This causes the
efficiency (η) to degrade with increasing die temperature.
Input Capacitor
of the power MOSFETs increases
DS(ON)
The ceramic input capacitors should be placed as close as
possible between the VIN and PGND pins to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or
tantalum) should be placed between CIN and the power
source lead to reduce under−damped ringing that can occur
Layout Recommendations
1. The input capacitor (C ) should be connected as
IN
close as possible to the VIN and GND pins.
Connect to VIN and GND using only top metal.
Do not route through vias.
between the inductance of the power source leads and C .
IN
Thermal Considerations
Heat is removed from the IC through the solder bumps to
the PCB copper. The junction−to−ambient thermal
2. Place the inductor (L) as close as possible to the
IC. Use short wide traces for the main current
paths.
resistance (θ )is largely a function of the PCB layout (size,
JA
3. The output capacitor (C
) should be as close as
OUT
copper weight, and trace width) and the temperature rise
possible to the IC. Connection to GND should be
on top metal. Feedback signal connection to
VOUT should be routed away from noisy
components and traces (e.g. SW line). For remote
sensing application, place one or all output
capacitors near the load and if there are also output
capacitors placed near the inductor, the maximum
trace resistance between the inductor and the load
should not exceed 30 mW.
from junction to ambient (ΔT).
For the FAN53527, θ is 42°C/W when mounted on its
four−layer with vias evaluation board in still air with 2 oz.
outer layer copper weight and 1 oz. inner layer.
For long−term reliable operation, the junction
JA
temperature (T ) should be maintained below 125°C.
J
To calculate maximum operating temperature (<125°C)
for a specific application:
1. Use efficiency graphs to determine efficiency for
the desired V , V
, and load conditions.
OUT
IN
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17
FAN53527
Figure 25. TOP Layer (component side)
Figure 26. Mid−Layer 1
Figure 27. Mid−Layer 2
Figure 28. BOTTOM Layer
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18
FAN53527
REMOTE SENSING
1. Feedback trace connects to “+” side of the output capacitor.
VIN
2. For remote sensing, place one or all output
capacitors near the load.
C
C
IN
BYP
EN
VSEL
MODE
VOUT
SW
L1
FAN53527
V
DD
C
C
OUT
Core
OUT_LOAD
Processor
(System Load)
PGND
AGND
GND
3. If there are also output capacitors placed near the inductor, the maximum trace resistance between
the inductor and the load should not exceed 30 mW.
Figure 29. Remote Sensing Schematic
Table 16. PRODUCT SPECIFIC DIMENSIONS
D
E
X
Y
2.015 0 03 mm
1.310 0.03 mm
0.255 mm
0.2075 mm
TinyBuck is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
2
ON Semiconductor is licensed by the Philips Corporation to carry the I C bus protocol.
www.onsemi.com
19
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP15 2.015x1.31x0.586
CASE 567QS
ISSUE O
DATE 31 OCT 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13347G
WLCSP15 2.015x1.31x0.586
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
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For additional information, please contact your local Sales Representative at
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