FAN5353MPX [ONSEMI]
3Mhz，3A 同步降压稳压器;
| 型号： | FAN5353MPX |
| 厂家： | 
ONSEMI |
| 描述： | 3Mhz，3A 同步降压稳压器 开关 光电二极管 稳压器 |
| 文件： | 总15页 (文件大小：1186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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December 2013
FAN5353
3 MHz, 3 A Synchronous Buck Regulator
Description
Features
The FAN5353 is a step-down switching voltage regulator that
delivers an adjustable output from an input voltage supply of
. 3 MHz Fixed-Frequency Operation
. Best-in-Class Load Transient
. 3 A Output Current Capability
. 2.7 V to 5.5 V Input Voltage Range
. Adjustable Output Voltage: 0.8 V to 90% of VIN
. Power Good Output
2.7 V to 5.5 V. Using
a proprietary architecture with
synchronous rectification, the FAN5353 is capable of
delivering 3 A at over 85% efficiency. The regulator operates
at a nominal fixed frequency of 3 MHz, which reduces the
value of the external components to 470 nH for the output
inductor and 10 µF for the output capacitor. Additional output
capacitance can be added without affecting stability if tighter
regulation during transients is required. The regulator
includes an open-drain power good (PGOOD) signal that
pulls low when the output is not in regulation.
. Internal Soft-Start
. Input Under-Voltage Lockout (UVLO)
. Thermal Shutdown and Overload Protection
. 12-Lead, 3 x 3.5 mm MLP
In shutdown mode, the supply current drops below 1 µA,
reducing power consumption.
FAN5353 is available in a 12-lead 3x3.5 mm MLP package.
Applications
R2
AGND
. Set-Top Box
R1
FB
1
2
3
4
5
6
12
11
10
9
. Hard Disk Drive
. Communications Cards
. DSP Power
VOUT
PGND
PGND
SW
PGOOD
EN
COUT
CVCC
P1
(GND)
VCC
PVIN
PVIN
8
SW
7
CIN1
CIN
Figure 1. Typical Application
Ordering Information
Part Number
Temp. Range
-40 to 85°C
Package
MLP-12, 3 x 3.5 mm
Packing Method
Tape and Reel
FAN5353MPX
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
Table 1. Recommended External Components for 3 A Maximum Load Current
Component
Description
Vendor
Parameter
Typ.
Units
Vishay — IHLP1616ABER47M01
Coiltronics — SD12-R47-R
TDK — VLC5020T-R47N,
L
0.47
µH
L1
470 nH nominal
DCR
20
mΩ
MURATA — LQH55PNR47NT0
2 pieces
10 µF, 6.3 V, X5R, 0805
COUT
CIN
GRM21BR60J106M (Murata)
C2012X5R0J106M (TDK)
C
C
10.0
10
µF
10 µF, 6.3 V, X5R, 0805
GRM155R71E103K (Murata)
C1005X7R1E103K (TDK)
CIN1
10 nF, 25 V, X7R, 0402
nF
GRM188R60J475K (Murata)
C1608X5R0J475K (TDK)
CVCC
C
R
4.7
1
4.7 µF, 6.3 V, X5R, 0603
Resistor: 1 Ω 0402
µF
R3(1)
any
Ω
Note:
1. R3 is optional and improves IC power supply noise rejection. See Layout recommendations for more information.
Pin Configuration
FB
VOUT
PGND
PGND
SW
1
2
3
4
5
6
12 NC
11 PGOOD
10 EN
P1
(GND)
9
8
7
VCC
PVIN
PVIN
SW
Figure 2. 12-Pin, 3 x 3.5 mm MLP (Top View)
Pin Definitions
Pin # Name
Description
FB. Connect to resistor divider. The IC regulates this pin to 0.8 V.
VOUT. Sense pin for VOUT. Connect to COUT.
1
2
FB
VOUT
Power Ground. Low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a
minimal path to these pins.
3, 4
PGND
Switching Node. Connect to inductor.
5, 6
P1
SW
Ground. All signals are referenced to this pin.
GND
PVIN
Power Input Voltage. Connect to input power source. Connect to CIN with minimal path.
7, 8
IC Bias Supply. Connect to input power source. Use a separate bypass capacitor CVCC from this pin
to the P1 GND terminal between pins 1 and 12.
9
VCC
Enable. The device is in shutdown mode when this pin is LOW. Do not leave this pin floating.
Power Good. This open-drain pin pulls LOW if the output falls out of regulation or is in soft-start.
This pin has no function and should be tied to GND.
10
11
EN
PGOOD
NC
12
Note:
2. P1 is the bottom heat-sink pad. Ground plane should flow through pins 3, 4, 12, and P1 and can be extended through pin
11 if PGOOD’s function is not required to improve IC cooling.
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum
ratings are stress ratings only.
Symbol Parameter
Voltage on SW, PVIN, VCC Pins
Voltage on Other Pins
Min.
Max.
Unit
IC Not Switching
IC Switching
-0.3
-0.3
-0.3
7.0
V
VIN
6.5
VCC + 0.3(3)
15
V
VINOV_SLEW Maximum Slew Rate of VIN Above 6.5 V when PWM is Switching
RPGOOD Pull-Up Resistance from PGOOD to VCC
V/ms
kΩ
1
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
2
Electrostatic Discharge
Protection Level
ESD
kV
2
TJ
TSTG
TL
Junction Temperature
Storage Temperature
–40
–65
+150
+150
+260
°C
°C
°C
Lead Soldering Temperature, 10 Seconds
Note:
3. Lesser of 7 V or VCC+0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter
Min.
Typ.
Max.
Unit
VCC, VIN
VOUT
IOUT
L
Supply Voltage Range
2.7
0.8
0
5.5
V
V
Output Voltage Range
Output Current
90% Duty Cycle
3
A
Inductor
0.47
10
µH
µF
µF
°C
°C
CIN
Input Capacitor
COUT
TA
Output Capacitor
20
Operating Ambient Temperature
Operating Junction Temperature
-40
-40
+85
TJ
+125
Thermal Properties
Symbol Parameter
Min.
Typ.
46
Max.
Unit
Junction-to-Ambient Thermal Resistance(4)
°C/W
θJA
Note:
4. Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer
1s2p boards in accordance to JESD51- JEDEC standard. Special attention must be paid not to exceed junction
temperature TJ(max) at a given ambient temperate TA.
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
3
Electrical Characteristics
Minimum and maximum values are at VIN = 2.7 V to 5.5 V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = 25°C, VIN =5 V.
Symbol Parameter
Power Supplies
Conditions
Min.
Typ. Max.
Unit
IQ
Quiescent Current
ILOAD = 0, VOUT=1.2 V
EN = GND
14
mA
µA
V
I SD
Shutdown Supply Current
0.1
2.83
2.30
530
3.0
V
IN Rising
2.95
2.40
VUVLO
Under-Voltage Lockout Threshold
VIN Falling
2.10
1.05
V
VUVHYST Under-Voltage Lockout Hysteresis
mV
Logic Pins
VIH
VIL
HIGH-Level Input Voltage
LOW-Level Input Voltage
Logic Input Hysteresis Voltage
Input Bias Current
V
0.4
V
VLHYST
IIN
IOUTL
IOUTH
100
mV
µA
mA
µA
Input tied to GND or VIN
VPGOOD = 0.4 V
0.01
1.00
1
PGOOD Pull-Down Current
PGOOD HIGH Leakage Current
VPGOOD = VIN
0.01
1.00
VOUT Regulation
TA = 25°C
0.792
0.788
0.800 0.808
0.800 0.812
V
V
Output Reference DC Accuracy
VREF
VREG
Measured at FB Pin
VOUT DC Accuracy
At VOUT pin W.R.T. Calculated
Value, ILOAD = 500 mA
1.6%
+1.6
%
∆VOUT
∆ILOAD
Load Regulation
IOUT(DC) = 0 to 3 A
–0.03
%/A
∆VOUT
∆VIN
2.7 V ≤ VIN ≤ 5.5 V,
IOUT(DC) = 1.5 A
Line Regulation
0.01
±20
%/V
mV
ILOAD step 0.1 A to 1.5 A,
tr = tf = 100 ns, VOUT=1.2 V
Transient Response
Power Switch and Protection
RDS(ON)P P-channel MOSFET On Resistance
RDS(ON)N N-channel MOSFET On Resistance
60
40
mΩ
mΩ
A
ILIMPK
TLIMIT
THYST
P-MOS Peak Current Limit
Thermal Shutdown
3.75
4.55
150
20
5.50
°C
°C
V
Thermal Shutdown Hysteresis
Rising Threshold
Falling Threshold
6.2
VSDWN
Input OVP Shutdown
5.50
2.7
5.85
V
Frequency Control
fSW
Oscillator Frequency
3.0
3.3
MHz
Soft-Start
210
340
10
250
420
RLOAD > 5 Ω, to VOUT = 1.2 V
RLOAD > 5 Ω, to VOUT = 1.8 V
µs
µs
tSS
Regulator Enable to Regulated VOUT
Soft-Start VOUT Slew Rate
VSLEW
V/ms
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
4
Typical Characteristics
Unless otherwise specified, VIN = 5 V, VOUT = 1.2 V, circuit of Figure 1, and components per Table 1.
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
VIN = 3.3V
VIN = 5V
VIN = 3.3V
VIN = 5V
1
10
100
1000
10000
1
10
100
1000
10000
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 3. Efficiency vs. ILOAD at VOUT = 1.2 V
Figure 4. Efficiency vs. ILOAD at VOUT = 1.8 V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
VIN = 4.2V
VIN = 5V
VIN = 3.3V
VIN = 5V
1
10
100
1000
10000
1
10
100
1000
10000
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 5. Efficiency vs. ILOAD at VOUT = 2.5 V
Figure 6. Efficiency vs. ILOAD at VOUT = 3.3 V
1
16
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
15
14
13
12
11
10
9
85°C
25°C
–40°C
85°C
25°C
-40°C
8
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
VIN Input Voltage (V)
Input Voltage(V)
Figure 7. Shutdown Supply Current vs. VIN, EN to 0 V
Figure 8. Quiescent Current vs. VIN, No Load
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
5
Typical Characteristics
Unless otherwise specified, VIN = 5 V, VOUT = 1.2 V, circuit of Figure 1, and components per Table 1.
VOUT
VOUT
IL
IL
Iload
Iload
Figure 9. Load Transient Response: 100 mA to 1.5 A to
100 mA, tr=tf=100 ns, Horizontal Scale = 5 µs/div.
Figure 10. Load Transient Response: 500 mA to 3 A to
500 mA, tr=tf=100 ns, Horizontal Scale = 5 µs/div.
20
3.5
3.0
2.5
2.0
18
5VIN,1.2VOUT
16
3.3VIN,1.2VOUT
14
12
10
8
5VIN, 3.3VOUT
1.5
1.0
0.5
-
VIN = 4.1V
VIN = 4.0V
VIN = 3.9V
VIN = 3.8V
6
4
2
0
0
0.5
1
1.5
Load Current (A)
2
2.5
3
0.1
1
10
100
1000
10000
Load Current (mA)
Figure 11. Output Voltage Ripple vs. Load Current
Figure 12. Effect of tOFF Minimum on Reducing the
Switching Frequency at Large Duty Cycles, VOUT = 3.3 V
90
80
70
60
VIN
50
1.2VOUT,1.5A load
40
VOUT
1.2VOUT, 3A load
3.3VOUT,1.5A load
30
20
0.01
0.1
1
10
100
Frequency (KHz)
Figure 13. Power Supply Rejection Ratio
Figure 14. Line Transient Response with 1 A load,
10 µs/div.
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
6
Typical Characteristics
Unless otherwise specified, VIN = 5 V, VOUT = 1.2 V, circuit of Figure 1, and components per Table 1.
VEN
VIN=VEN
VOUT
VOUT
VPG
VPG
Isupply
Isupply
Figure 15. Soft-Start: EN Voltage Raised After VIN =5.0 V,
ILOAD = 0, Horizontal Scale = 100 µs/div.
Figure 16. Soft-Start: EN Pin Tied to VCC,
ILOAD = 0, Horizontal Scale = 1 ms/div.
VEN
VIN=VEN
VOUT
VOUT
VPG
VPG
Isupply
Isupply
Figure 17. Soft-Start: EN Pin Raised after VIN = 5.0 V,
Figure 18. Soft-Start: EN Pin Tied to VCC, RLOAD =
R
LOAD = 400 mΩ. COUT = 100 µF, Horizontal Scale =
400 mΩ, COUT = 100 µF, Horizontal Scale = 1 ms/div.
100µs/div.
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
7
Typical Characteristics
Unless otherwise specified, VIN = 5 V, VOUT = 1.2 V, circuit of Figure 1, and components per Table 1.
VOUT
VOUT
IL
IL
VPG
VPG
Figure 19. VOUT to GND Short Circuit, 200 µs/div.
Figure 20. VOUT to GND Short Circuit, 5 µs/div.
VEN
VOUT
VOUT
IL
IL
VPG
VPG
Figure 22. Progressive Overload, 200 µs/div.
Figure 21. Over-Current at Startup: RLOAD = 200 mΩ.,
50 µs/div.
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
8
Operation Description
The FAN5353 is a step-down switching voltage regulator
that delivers an adjustable output from an input voltage
supply of 2.7 V to 5.5 V. Using a proprietary architecture with
synchronous rectification, the FAN5353 is capable of
delivering 3 A at over 80% efficiency. The regulator operates
at a nominal frequency of 3 MHz at full load, which reduces
the value of the external components to 470 nH for the
output inductor and 20 µF for the output capacitor.
PGOOD Pin
The PGOOD pin is an open drain output that indicates the IC
is in regulation when its state is open. PGOOD requires an
external pull-up resistor. PGOOD pulls LOW under the
following conditions:
1. The IC has operated in cycle-by-cycle current limit for
eight or more consecutive PWM cycles.
2. The circuit is disabled; either after a fault occurs, or
when EN is LOW.
Control Scheme
The FAN5353 uses a proprietary non-linear, fixed-frequency
PWM modulator to deliver a fast load transient response,
while maintaining a constant switching frequency over a wide
range of operating conditions. The regulator performance is
independent of the output capacitor ESR, allowing for the use
of ceramic output capacitors. Although this type of operation
normally results in a switching frequency that varies with input
voltage and load current, an internal frequency loop holds the
switching frequency constant over a large range of input
voltages and load currents.
3. The IC is performing a soft-start.
Under-Voltage Lockout
When EN is HIGH, the under-voltage lockout keeps the part
from operating until the input supply voltage rises high
enough to properly operate. This ensures no misbehavior of
the regulator during startup or shutdown.
Input Over-Voltage Protection (OVP)
When VIN exceeds VSDWN (about 6.2 V) the IC stops switching,
to protect the circuitry from internal spikes above 6.5 V. An
internal 40 µs filter prevents the circuit from shutting down due
to noise spikes. For the circuit to fully protect the internal
circuitry, the VIN slew rate above 6.2 V must be limited to no
more than 15 V/ms when the IC is switching.
Setting the Output Voltage
The output voltage is set by the R1, R2, and VREF (0.8 V):
V
− V
REF
R1
R2
OUT
=
V
(1)
(2)
REF
R1 must be set at or below 100 kΩ. Therefore:
The IC protects itself if VIN overshoots to 7 V during initial
power-up as long as the VIN transition from 0 to 7 V occurs in
less than 10 µs (10% to 90%).
R1• 0.8
R2 =
(
V
− 0.8
)
OUT
Current Limiting
For example, for VOUT = 1.2 V, R1 = 100 kΩ, R2 = 200 kΩ.
A heavy load or short circuit on the output causes the current
in the inductor to increase until a maximum current threshold
is reached in the high-side switch. Upon reaching this point,
the high-side switch turns off, preventing high currents from
causing damage. 16 consecutive PWM cycles in current limit
cause the regulator to shut down and stay off for about
1200µs before attempting a restart.
Enable and Soft Start
When the EN pin is LOW, the IC is shut down, all internal
circuits are off, and the part draws very little current. Raising
EN above its threshold voltage activates the part and starts
the soft-start cycle. During soft-start, the modulator’s internal
reference is ramped slowly to minimize any large surge
currents on the input and prevents any overshoot of the
output voltage.
In the event of a short circuit, the soft-start circuit attempts to
restart and produces an over-current fault after about 50 µs,
which results in a duty cycle of less than 10%, providing
current into a short circuit.
If large values of output capacitance are used, the regulator
may fail to start. If VOUT fails to achieve regulation within
320 µs from the beginning of soft-start, the regulator shuts
down and waits 1200 µs before attempting a restart. If the
regulator is at its current limit for more than about 60 µs, the
regulator shuts down before restarting 1200 µs later. This
limits the COUT capacitance when a heavy load is applied
during the startup. For a typical FAN5353 starting with a
resistive load:
Thermal Shutdown
When the die temperature increases, due to a high load
condition and/or a high ambient temperature, the output
switching is disabled until the temperature on the die has
fallen sufficiently. The junction temperature at which the
thermal shutdown activates is nominally 150°C with a
20°C hysteresis.
COUTMAX(µF) ≈ 400 −100 ∗ILOAD(A)
V
(3)
OUT
where
I
=
LOAD
R
LOAD
Synchronous rectification is inhibited during soft-start,
allowing the IC to start into a pre-charged load.
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
9
shows the effects of inductance higher or lower than the
recommended 470 nH on regulator performance.
Minimum Off-Time Effect on Switching
Frequency
tON(MIN) and tOFF(MIN) are both 45 ns. This imposes constraints
VOUT
Table 2. Effects of Increasing the Inductor
Value (from 470nH recommended value) on
Regulator Performance
on the maximum
that the FAN5353 can provide,
VIN
while still maintaining a fixed switching frequency in PWM
mode. While regulation is unaffected, the switching
frequency drops when the regulator cannot provide sufficient
duty cycle at 3 MHz to maintain regulation.
Transient
Response
∆VOUT (EQ. 8)
IMAX(LOAD)
Increase
Decrease
Degraded
The calculation for switching frequency is given as:
(4)
1
1
Inductor Current Rating
fSW = min
,
tSW(MAX) 333.3ns
The FAN5353’s current limit circuit can allow a peak current
of 5.5 A to flow through L1 under worst-case conditions. If it
is possible for the load to draw that much continuous current,
the inductor should be capable of sustaining that current or
failing in a safe manner.
where:
VOUT + IOUT •ROFF
VIN −IOUT •RON − VOUT
tSW(MAX) = 45ns • 1+
For space-constrained applications, a lower current rating for
L1 can be used. The FAN5353 may still protect these
inductors in the event of a short circuit, but may not be able
to protect the inductor from failure if the load is able to draw
higher currents than the DC rating of the inductor.
=
R
R
+ DCR
L
OFF
DSON_N
=
RON
R
+ DCR
L
DSON_P
Applications Information
Selecting the Inductor
The output inductor must meet both the required inductance
and the energy handling capability of the application. The
inductor value affects the average current limit, the output
voltage ripple, and the efficiency.
Output Capacitor
Table 1 suggests 0805 capacitors, but 0603 capacitors may
be used if space is at a premium. Due to voltage effects, the
0603 capacitors have a lower in-circuit capacitance than the
0805 package, which can degrade transient response and
output ripple.
Increasing COUT has no effect on loop stability and can
therefore be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, ∆VOUT, is:
The ripple current (∆I) of the regulator is:
VOUT
V
− VOUT
L • fSW
IN
∆I ≈
•
(5)
V
1
IN
∆VOUT = ∆I•
+ ESR
(8)
8• COUT • fSW
The maximum average load current, IMAX(LOAD) is related to
the peak current limit, ILIM(PK)by the ripple current as:
where COUT is the effective output capacitance. The
capacitance of COUT decreases at higher output voltages,
∆I
2
which results in higher ∆VOUT
.
IMAX(LOAD) = ILIM(PK)
−
(6)
If COUT is greater than 100 µF, the regulator may fail to start
under load.
The FAN5353 is optimized for operation with L=470 nH, but
is stable with inductances up to 1.2 µH (nominal). The
inductor should be rated to maintain at least 80% of its value
at ILIM(PK). Failure to do so lowers the amount of DC current
the IC can deliver.
If an inductor value greater than 1.0 µH is used, at least
30 µF of COUT should be used to ensure stability.
ESL Effects
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since ∆I increases, the
RMS current increases, as do core and skin effect losses.
The ESL (Equivalent Series Inductance) of the output
capacitor network should be kept low to minimize the square
wave component of output ripple that results from the
division ratio COUT’s ESL and the output inductor (LOUT). The
square wave component due to ESL can be estimated as:
∆I2
12
2
(7)
IRMS
=
IOUT(DC)
+
ESLCOUT
(9)
∆VOUT(SQ) ≈ VIN
•
L1
The increased RMS current produces higher losses through
the RDS(ON) of the IC MOSFETs as well as the inductor ESR.
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired COUT value. For
example, to obtain COUT = 20 µF, a single 22 µF 0805 would
produce twice the square wave ripple of 2 x 10 µF 0805.
Increasing the inductor value produces lower RMS currents,
but degrades transient response. For a given physical
inductor size, increased inductance usually results in an
inductor with lower saturation current.
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
10
To minimize ESL, try to use capacitors with the lowest ratio
of length to width. 0805s have lower ESL than 1206s. If low
output ripple is a chief concern, some vendors produce 0508
or 0612 capacitors with ultra-low ESL. Placing additional
small value capacitors near the load also reduces the high-
frequency ripple components.
VCC and VIN should be connected together by a thin trace
some distance from the IC, or through a resistor (shown as
R3 below), to isolate the switching spikes on PVIN from the
IC bias supply on VCC. If PCB area is at a premium, the
connection between PVIN and VCC can be made on another
PCB layer through vias. The via impedance provides some
filtering for the high-frequency spikes generated on PVIN.
Input Capacitor
PGND and AGND connect through the thermal pad of the
IC. Extending the PGND and AGND planes improves IC
cooling. The IC analog ground (AGND) is bonded to P1
between pins 1 and 12. Large AC ground currents should
return to pins 3 and 4 (PGND) either through the copper
under P1 between pins 6 and 7 or through a direct trace
from pins 3 and 4 (as shown for COUT1-COUT3).
The 10µF ceramic input capacitor should be placed as close
as possible between the VIN pin and PGND to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or tantalum)
should be placed between CIN and the power source lead to
reduce under-damped ringing that can occur between the
inductance of the power source leads and CIN.
EN and PGOOD connect through vias to the system control
logic.
The effective CIN capacitance value decreases as VIN
increases due to DC bias effects. This has no significant
impact on regulator performance.
CIN1 is an optional device used to provide a lower
impedance path for high-frequency switching edges/spikes,
which helps to reduce SW node and VIN ringing. CIN should
be placed as close as possible between PGND and VIN, as
shown below.
Layout Recommendations
The layout recommendations below highlight various top-
copper planes by using different colors. It includes COUT3
to demonstrate how to add COUT capacitance to reduce
ripple and transient excursions. The inductor in this
example is the TDK VLC5020T-R47N.
PGND connection back to inner planes should be
accomplished as series of vias distributed among the COUT
return track and CIN return plane between pins 6 and 7.
AGND
0402
VOUT
COUT1
COUT3
COUT2
1
2
3
4
5
6
12
11
10
9
CVCC
FAN5353
10µF
0805
10µF
0805
10µF
0805
P1
(GND)
PGND
R3
VCC
8
VIN
7
10µF
0805
CIN1 0402
SW
CIN
0.47µH
5 x 5 mm
PGND
Figure 23. 3 A Layout Recommendation
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
11
Physical Dimensions
2X
0.10 A
3.50
A
2.60
B
0.85
2.65
PIN#1 IDENT
3.00
2.84
0.10 B
TOP VIEW
2X
1.85
1.05
0.85
0.8 MAX
0.10 C
0.08 C
(0.2)
LAND PATTERN RECOMMENDATION
SIDE VIEW
0.05
0.00
C
2.60+/-0.05
(0.38)
SEATING PLANE
PIN#1 IDENT
NOTES:
1
6
A. CONFORMS TO JEDEC MO-229
VARIATION WFED-2.
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS
BASED ON IPC 7351 DESIGN GUIDELINES
E. LANDPATTERN EXTENSION TO INCLUDE
CENTER PAD TABS IS OPTIONAL
F. FILENAME AND REV: MKT-MLP12DREV1
1.60+/-0.05
0.25+/-0.05
0.45+/-0.05
(12X)
12
7
0.25+/-0.05 (12X)
0.50
0.10
0.05
C A B
BOTTOM VIEW
C
Figure 24. 12-Lead, 3x3.5 mm Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/ML/MLP12D.pdf.
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
12
© 2009 Fairchild Semiconductor Corporation
FAN5353 • Rev. 1.0.3
www.fairchildsemi.com
13
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相关型号：
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FAIRCHILD
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