FAN53555UC42X [ONSEMI]
Switching Regulator;
| 型号： | FAN53555UC42X |
| 厂家： | 
ONSEMI |
| 描述： | Switching Regulator 开关 |
| 文件： | 总25页 (文件大小：2053K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2013
FAN53555
5 A, 2.4 MHz, Digitally Programmable TinyBuck™ Regulator
Features
Description
The FAN53555 is a step-down switching voltage regulator
that delivers a digitally programmable output from an input
voltage supply of 2.5 V to 5.5 V. The output voltage is
programmed through an I2C interface capable of operating up
to 3.4 MHz.
. Fixed-Frequency Operation: 2.4 MHz
. Best-in-Class Load Transient
. Continuous Output Current Capability: 5 A
. Pulse Current Capability: 6.5 A (05 Option)
. 2.5 V to 5.5 V Input Voltage Range
. Digitally Programmable Output Voltage:
Using
a
proprietary architecture with synchronous
rectification, the FAN53555 is capable of delivering 5 A
continuous at over 80% efficiency, while maintaining over
80% efficiency at load currents as low as 10 mA. Pulse
currents as high as 6.5 A can be supported by the 05 option.
The regulator operates at a nominal fixed frequency of
2.4 MHz, which reduces the value of the external components
to 330 nH for the output induction and as low as 20 µF for the
output capacitor. Additional output capacitance can be added
to improve regulation during load transients without affecting
stability. Inductance up to 1.2 µH may be used with additional
output capacitance.
00/01/03/05/08/18 Options: 0.60-1.23 V in 10 mV
Steps
04/042/09/ Option: 0.603-1.411 V in 12.826 mV Steps
24 Option : 0.603-1.420 V in 12.967 mV Steps
13 Option: 0.80-1.43 V in 10 mV steps
. Programmable Slew Rate for Voltage Transitions
. I2C-Compatible Interface Up to 3.4 Mbps
. PFM Mode for High Efficiency in Light Load
. Quiescent Current in PFM Mode: 60 µA (Typical)
. Internal Soft-Start
At moderate and light loads, Pulse Frequency Modulation
(PFM) is used to operate in Power-Save Mode with a typical
quiescent current of 60 µA. Even with such a low quiescent
current, the part exhibits excellent transient response during
large load swings. At higher loads, the system automatically
switches to fixed-frequency control, operating at 2.4 MHz. In
Shutdown Mode, the supply current drops below 1 µA,
reducing power consumption. PFM Mode can be disabled if
constant frequency is desired. The FAN53555 is available in a
20-bump, 1.6 x 2 mm, WLCSP.
. Input Under-Voltage Lockout (UVLO)
. Thermal Shutdown and Overload Protection
. 20-Bump Wafer-Level Chip Scale Package (WLCSP)
Applications
PVIN
. Application, Graphic, and DSP Processors
CIN1
CIN
ARM™, Krait™, OMAP™, NovaThor™, ARMADA™
EN
SDA
VOUT
SW
. Hard Disk Drives
L1
COUT
. Tablets, Netbooks, Ultra-Mobile PCs
. Smart Phones
FAN53555
VDD
Core
SCL
VSEL
GND
Processor
. Gaming Devices
(System Load)
AGND
GND
Figure 1. Typical Application
All trademarks are the property of their respective owners.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
Ordering Information
Power-Up
Defaults
Max.
I2C
Slave
Address
Max.
RMS
Current
A1 PIN
Function
Pulse Temperature
Current
(50 ms)
Packing
Method
Part Number
Package
Range
VSEL0 VSEL1
FAN53555UC00X
FAN53555UC01X
FAN53555UC03X
FAN53555UC04X
FAN53555UC24X
1.05
0.90
0.90
1.10
1.225
1.20
OFF
N/A
VSEL
VSEL
PGOOD
VSEL
VSEL
VSEL
VSEL
VSEL
VSEL
VSEL
VSEL
VSEL
VSEL
VSEL
VSEL
VSEL
VSEL
5 A
5 A
5 A
5 A
4 A
4 A
5 A
5 A
4 A
4 A
3 A
3 A
5 A
5 A
5 A
5 A
5 A
N/A
N/A
N/A
N/A
N/A
N/A
6.5 A
6.5 A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.20
1.212
1.212
OFF
OFF
1.15
1.15
1.10
1.10
1.15
1.15
1.15
1.15
1.20
FAN53555BUC24X(1) 1.225
FAN53555UC05X
FAN53555BUC05X(1)
FAN53555UC08X
FAN53555BUC08X(1)
FAN53555BUC09X(1)
FAN53555UC09X
FAN53555UC13X
FAN53555BUC13X(1)
FAN53555UC18X
FAN53555BUC18X(1)
FAN53555UC042X(2)
Notes:
0.90
0.90
1.02
1.02
1.10
1.10
1.15
1.15
1.02
1.02
1.10
C0
WLCSP- Tape and
-40 to 85°C
20
Reel
C4
1. The FAN53555BUC24X, FAN53555BUC05X, FAN53555BUC08X, FAN53555BUC09X, FAN53555BUC13X, and
FAN53555BUC18X include backside lamination.
2. The 042 option is the same as the 04 option, except the I2C slave addresses.
Recommended External Components
Table 1. Recommended External Components for 5 A Maximum Load Current
Component
Description
Vendor
Parameter
Typ.
0.33
13
Unit
µH
L
L1
330 nH Nominal
See Table 2
DCR
m
2 Pieces;
22 F, 6.3 V, X5R, 0805
GRM21BR60J226M (Murata)
C2012X5R0J226M (TDK)
COUT
C
C
C
C
44
10
20
10
1 Piece;
10 F, 10 V, X5R, 0805
LMK212BJ106KG-T (Taiyo Yuden)
C2012X5R1A106M (TDK)
µF
nF
CIN
2 Pieces;
10 F, 6.3 V, X5R, 0805
GRM21BR60J106M (Murata)
C2012X5R0J106M (TDK)
GRM155R71E103K (Murata)
C1005X7R1E103K (TDK)
CIN1
10 nF, 25 V, X7R, 0402
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
2
Table 2. Recommended Inductors for High-Current Applications
Component Dimensions
(3)
Manufacturer
Part#
L (nH)
DCR (mΩ) IMAXDC
L
W
H
Vishay
Mag. Layers(4)
Mag. Layers
Inter-Technical
Bournes
IHLP1616ABERR47M01
MMD-04ABNR33M-M1-RU
MMD-04ABNR47M-M1-RU
SM1608-R33M
470
330
470
330
330
470
470
20.0
12.5
20.0
9.6
5.0
7.5
5.0
9.0
6.7
5.0
5.4
4.5
4.5
4.5
4.5
4.7
4.7
5.0
4.1
4.1
4.1
4.1
4.2
4.2
5.0
1.2
1.2
1.2
2.0
1.2
1.2
2.0
SRP4012-R33M
15.0
20.0
15.0
Bournes
SRP4012-R47M
TDK
VLC5020T-R47M
Notes:
3. IMAXDC is the lesser current to produce 40°C temperature rise or 30% inductance roll-off.
4. Preferred inductor value is 330 nH and all dynamic characterization was performed with this coil.
FAN53555-24, -08, and -09 Reduced Output Current (4 A Max. RMS. for 08, and 24, 3 A
Max. RMS for 09) Smaller Footprint Application
The FAN53555-24, -08, and -09 were developed to provide power for core processors with high-performance graphics
acceleration in Li-Ion-powered handheld devices. These applications require a very compact solution. The smaller input and
output capacitors in the table below assume that additional bypass capacitance exists across the battery in fairly close proximity
to the regulator(s). The CIN capacitors specified below are the capacitors that are required in very close proximity to VIN and
PGND (see layout recommendations in Figure 2 below).
Table 3. Recommended External Components for Lower-Current Applications with FAN53555-08-09-24
Component
Description
Vendor
Parameter
Typ.
Unit
L1
470 or 330 nH, 2016 case size
See Table 4
-08, ,24 Option
2 Pieces 22 F, 6.3 V, X5R, 0603
44
22
COUT
C1608X5R0J226M (TDK)
C
-09 Option
1 Piece 22 F, 6.3 V, X5R, 0603
µF
nF
1 Piece;
10 F, 10 V, X5R, 0402
CIN
GRM155R61A106M (Murata)-
C
C
10
10
CIN1
10 nF, 25 V, X5R, 0201
TMK063CG100DT-F (Taiyo Yuden)
Table 4. Recommended Inductors for Lower-Current Applications with FAN53555-08-09-24
Component Dimensions
(5)
Manufacturer
Part#
L (nH) DCR (mΩ Typ.) IMAXDC
L
W
H
Toko
Toko
DFE201612R-H-R33N
DFE201612C-R47N
330
470
470
470
25
40
30
30
3.2
3.2
3.1
3.1
2.0
2.0
2.0
2.0
1.6
1.6
1.6
1.6
1.2
1.2
1.2
0.9
Cyntek
SEMCO
Note:
PIFE20161B-R47MS-39
CIGT201610HMR47SCE
5. IMAXDC is the lesser current to produce 40°C temperature rise or 30% inductance roll-off.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
3
Layout
Figure 2. Reduced-Footprint Layout
Pin Configuration
VSEL*
A1
EN
A2
SCL
A3
VOUT
A4
A4
B4
C4
D4
E4
A3
B3
C3
D3
E3
A2
B2
C2
D2
E2
A1
B1
C1
D1
E1
SDA
B1
AGND
B4
B2
C2
D2
E2
B3
C3
D3
E3
GND
C1
C4
VIN
SW
D1
E1
D4
E4
A1 = VSEL for 00, 01, 04, 05, 08, 09, 13, 18, 24
A1 = PGOOD for 03
Figure 3. Top View
Figure 4. Bottom View
Pin Definitions
Pin #
Name
Description
VSEL
(Except -
03 Option)
Voltage Select. When this pin is LOW, VOUT is set by the VSEL0 register. When this pin is HIGH, VOUT
is set by the VSEL1 register.
A1
PGOOD
(03)
Power Good. This open-drain pin pulls LOW if an overload condition occurs or soft-start is in progress.
Enable. The device is in Shutdown Mode when this pin is LOW. All register values are kept during
shutdown. Options 00, 01, 03, 05, 08 09, 13, and 18 do not reset register values when EN is raised.
The 04, 24 and 042 options reset all registers to default values when EN pin is LOW. If pulled up to a
low-impedance voltage source greater than 1.8 V, use at least 100 series resistor.
A2
EN
I2C Serial Clock
A3
A4
B1
SCL
VOUT
SDA
VOUT. Sense pin for VOUT. Connect to COUT.
I2C Serial Data
Ground. Low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a minimal
path to these pins.
B2, B3,
C1 – C4
GND
AGND
VIN
Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents through
this pin.
B4
D1, D2,
E1, E2
Power Input Voltage. Connect to the input power source. Connect to CIN with minimal path.
Switching Node. Connect to the inductor.
D3, D4,
E3, E4
SW
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum
ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
IC Not Switching
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
7.0
6.5
2.0
Voltage on SW, VIN Pins
Voltage on EN Pin
V
V
IC Switching
Tied without Series Resistance)
VIN
(6)
VIN
Tied through Series Resistance of at Least 100
(6)
Voltage on All Other Pins IC Not Switching
Voltage on VOUT Pin
VIN
V
V
VOUT
3.0
VINOV_SLEW Maximum Slew Rate of VIN > 6.5 V, PWM Switching
100
V/ms
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
2500
1500
Electrostatic Discharge
Protection Level
ESD
V
TJ
TSTG
TL
Junction Temperature
Storage Temperature
-40
-65
+150
+150
+260
°C
°C
°C
Lead Soldering Temperature, 10 Seconds
Note:
6. Lesser of 7 V or VIN+0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
2.5
0
Typ.
Max.
5.5
5
Unit
VIN
IOUT
L
Supply Voltage Range
Output Current
Inductor
V
A
0.33
10
µH
µF
µF
°C
°C
CIN
COUT
TA
Input Capacitor
Output Capacitor
44
Operating Ambient Temperature
Operating Junction Temperature
-40
-40
+85
TJ
+125
Thermal Properties
Symbol
Parameter
Junction-to-Ambient Thermal Resistance(7)
Min.
Typ.
Max.
Unit
38
°C/W
JA
Note:
7. See Thermal Considerations in the Application Information section.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
5
Electrical Characteristics
Minimum and maximum values are at VIN=2.5 V to 5.5 V, TA=-40°C to +85°C, unless otherwise noted. Typical values are at
TA=25°C, VIN=5 V, and EN=HIGH.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Power Supplies
ILOAD=0
60
43
100
µA
mA
µA
µA
V
IQ
Quiescent Current
ILOAD=0, MODE Bit=1 (Forced PWM)
EN=GND
H/W Shutdown Supply Current
S/W Shutdown Supply Current
0.1
41
5.0
75
I SD
EN= VIN, BUCK_ENx=0
VIN Rising
VUVLO Under-Voltage Lockout Threshold
VUVHYST Under-Voltage Lockout Hysteresis
EN, VSEL, SDA, SCL
2.35
350
2.45
mV
VIH
VIL
HIGH-Level Input Voltage
LOW-Level Input Voltage
1.1
V
V
0.4
VLHYST Logic Input Hysteresis Voltage
IIN Input Bias Current
PGOOD (03 Option)
IOUTL PGOOD Pull-Down Current
IOUTH PGOOD HIGH Leakage Current
VOUT Regulation
160
mV
µA
Input Tied to GND or VIN
0.01
1.00
1
mA
µA
0.01
1.00
IOUT(DC)=0, Forced PWM,
VOUT=VSEL0 Default Value
-1.5
-2.0
1.5
4.0
%
%
2.5 V ≤ VIN ≤ 4.5 V,
08, 24
Options
VOUT from Minimum to
Maximum, IOUT(DC)=0 to
4 A, Auto PFM/PWM
2.5 V ≤ VIN ≤ 4.5 V,
VOUT from Minimum to
Maximum, IOUT(DC)=0 to
3 A, Auto PFM/PWM
09 Option
-2.0
-2.0
-3.0
4.0
4.0
5.0
%
%
VREG
VOUT DC Accuracy
2.5 V ≤ VIN ≤ 4.5 V,
13, 18
Options
VOUT from Minimum to
Maximum, IOUT(DC)=0 to
5 A, Auto PFM/PWM
2.5 V ≤ VIN ≤ 5.5 V,
All Other
Options
VOUT from Minimum to
Maximum, IOUT(DC)=0 to
5 A, Auto PFM/PWM
%
VOUT
ILOAD
Load Regulation
Line Regulation
IOUT(DC)=1 to 5 A
-0.1
%/A
VOUT
2.5 V ≤ VIN ≤ 5.5 V, IOUT(DC)=1.5 A
0.01
±40
%/V
mV
V
IN
ILOAD Step 0.1 A to 1.5 A,
tr=tf=100 ns, VOUT=1.2 V
VTRSP Transient Response
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
6
Electrical Characteristics
Minimum and maximum values are at VIN=2.5 V to 5.5 V, TA=-40°C to +85°C, unless otherwise noted. Typical values are at
TA=25°C, VIN=5 V, and EN=HIGH.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Power Switch and Protection
RDS(ON)P P-Channel MOSFET On Resistance
RDS(ON)N N-Channel MOSFET On Resistance
VIN=5 V
VIN=5 V
28
17
mΩ
mΩ
A
00, 01, 03, 04, 13, 18, 042 Options
05 Option
6.3
8.5
5.0
4.0
7.4
8.5
11.5
6.8
10.0
5.9
A
ILIMPK
P-MOS Peak Current Limit
08,24 Options
A
09 Option
4.75
150
17
5.5
TLIMIT
THYST
Thermal Shutdown
°C
°C
V
Thermal Shutdown Hysteresis
Rising Threshold
Falling Threshold
6.15
5.85
VSDWN Input OVP Shutdown
5.50
2.05
V
Frequency Control
fSW
DAC
Oscillator Frequency
2.40
6
2.75
0.5
MHz
Resolution
Differential Nonlinearity(8)
Bits
LSB
Timing
I2CEN
EN=HIGH to I2C Start
100
µs
µs
Soft-Start
RLOAD > 5 ; to VOUT=1.2 V;
00, 01, 03, 04, 042, 05, 09, and
13 Options
300
tSS
Regulator Enable to Regulated VOUT
2.5 V ≤ VIN ≤ 4.5 V; RLOAD =2 ; to
VOUT=1.127 V with 1.1 V Pre-Bias
Voltage; 08 and 18 Options
135 175
160
µs
ROFF
VOUT Pull-Down Resistance, Disabled
EN=0 or VIN<VUVLO
Ω
Note:
8. Monotonicity assured by design.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
7
I2C Timing Specifications
Guaranteed by design.
Symbol
Parameter
Condition
Standard Mode
Min.
Typ. Max.
Unit
100
400
Fast Mode
fSCL
SCL Clock Frequency
Fast Mode Plus
1000
3400
1700
4.7
kHz
High-Speed Mode, CB ≤100 pF
High-Speed Mode, CB ≤ 400 pF
Standard Mode
Bus-Free Time between STOP and
START Conditions
tBUF
Fast Mode
1.3
µs
Fast Mode Plus
0.5
Standard Mode
4
µs
ns
ns
ns
µs
µs
µs
ns
ns
µs
ns
ns
ns
ns
µs
ns
ns
ns
Fast Mode
600
START or REPEATED START
Hold Time
tHD;STA
Fast Mode Plus
260
High-Speed Mode
Standard Mode
160
4.7
Fast Mode
1.3
tLOW
SCL LOW Period
SCL HIGH Period
Fast Mode Plus
0.5
High-Speed Mode, CB ≤ 100 pF
High-Speed Mode, CB ≤ 400 pF
Standard Mode
160.0
320.0
4
Fast Mode
600
tHIGH
Fast Mode Plus
260
High-Speed Mode, CB ≤ 100 pF
High-Speed Mode, CB ≤ 400 pF
Standard Mode
60
120
4.7
Fast Mode
600.0
260.0
160.0
250
tSU;STA
REPEATED START Setup Time
Data Setup Time
Fast Mode Plus
High-Speed Mode
Standard Mode
Fast Mode
100
tSU;DAT
ns
Fast Mode Plus
50
High-Speed Mode
Standard Mode
10
0
0
0
0
0
3.45
900.00
450.00
70.00
150.00
µs
ns
ns
ns
ns
Fast Mode
tHD;DAT
Data Hold Time
SCL Rise Time
Fast Mode Plus
High-Speed Mode, CB ≤ 100 pF
High-Speed Mode, CB ≤ 400 pF
Standard Mode
20+0.1CB
20+0.1CB
20+0.1CB
10
20
1000
300
120
80
Fast Mode
tRCL
Fast Mode Plus
ns
High-Speed Mode, CB ≤ 100 pF
High-Speed Mode, CB ≤ 400 pF
160
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
8
I2C Timing Specifications (Continued)
Guaranteed by design.
Symbol
Parameter
Condition
Standard Mode
Min.
20+0.1CB
20+0.1CB
20+0.1CB
10
Typ. Max.
Unit
300
300
120
40
Fast Mode
tFCL
SCL Fall Time
Fast Mode Plus
ns
High-Speed Mode, CB ≤ 100 pF
High-Speed Mode, CB ≤ 400 pF
High-Speed Mode, CB ≤ 100 pF
20
10
80
Rise Time of SCL After a
REPEATED START Condition and
After ACK Bit
80
tRCL1
ns
ns
High-Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
20+0.1CB
1000
300
120
80
Fast Mode
20+0.1CB
20+0.1CB
tRDA
SDA Rise Time
SDA Fall Time
Fast Mode Plus
High-Speed Mode, CB ≤ 100 pF
High-Speed Mode, CB ≤ 400 pF
Standard Mode
10
20
20+0.1CB
160
300
300
120
80
Fast Mode
20+0.1CB
20+0.1CB
tFDA
Fast Mode Plus
ns
High-Speed Mode, CB ≤ 100 pF
High-Speed Mode, CB ≤ 400 pF
Standard Mode
10
20
4
160
µs
ns
ns
ns
pF
Fast Mode
600
120
160
tSU;STO
Stop Condition Setup Time
Fast Mode Plus
High-Speed Mode
CB
Capacitive Load for SDA and SCL
400
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
9
Timing Diagrams
tF
tSU;STA
tBUF
SDA
tR
TSU;DAT
tHD;STO
tHIGH
tHD;DAT
SCL
tLOW
tHD;STA
tHD;STA
REPEATED
START
START
STOP
START
Figure 5. I2C Interface Timing for Fast Plus, Fast, and Slow Modes
REPEATED
START
STOP
tFDA
tRDA
tSU;DAT
SDAH
tSU;STA
tRCL1
tFCL
tHIGH
tHD;DAT
note A
tRCL
tSU;STO
SCLH
tLOW
tHD;STA
REPEATED
START
= MCS Current Source Pull-up
= RP Resistor Pull-up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 6. I2C Interface Timing for High-Speed Mode
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
10
Typical Characteristics
Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25°C; circuit
and components according to Figure 1 and Table 1.
92%
90%
88%
86%
84%
82%
80%
78%
76%
92%
90%
88%
86%
84%
82%
80%
78%
76%
-40C
+25C
+85C
2.7 VIN
3.6 VIN
5.0 VIN
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
Load Current (mA)
Load Current (mA)
Figure 7. Efficiency vs. Load Current and Input Voltage
Figure 8. Efficiency vs. Load Current and Temperature
90%
88%
86%
84%
82%
80%
78%
76%
90%
2.7 VIN
88%
3.6 VIN
86%
84%
82%
80%
78%
76%
74%
72%
70%
5.0 VIN
74%
72%
70%
-40C
+25C
+85C
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
Load Current (mA)
Load Current (mA)
Figure 9. Efficiency vs. Load Current and Input Voltage,
VOUT=0.9 V
Figure 10. Efficiency vs. Load Current and Temperature,
VIN=5 V, VOUT=1.2 V
90%
90%
85%
80%
75%
2.7 VIN
3.6 VIN
85%
5.0 VIN
80%
75%
70%
65%
60%
3.6VIN, 1.2VOUT,L=MMD-04ABNR33M
70%
3.6VIN, 1.2VOUT,L=VLC5020T-R47M
5.0VIN, 1.2VOUT,L=MMD-04ABNR33M
65%
60%
5.0VIN, 1.2VOUT,L=VLC5020T-R47M
5.0VIN, 0.9VOUT,L=MMD-04ABNR33M
5.0VIN, 0.9VOUT,L=VLC5020T-R47M
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
6000
7000
Load Current (mA)
Load Current (mA)
Figure 11. Efficiency vs. Load Current and Input Voltage,
VOUT=0.6 V
Figure 12. Efficiency vs. Load Current, VIN=3.6 V and 5 V,
VOUT=1.2 V and 0.9 V
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
11
Typical Characteristics (Continued)
Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25°C; circuit
and components according to Figure 1 and Table 1.
25
20
15
10
5
20
16
12
8
2.7 VIN
3.6 VIN
5.0 VIN
2.7 VIN
3.6 VIN
5.0 VIN
4
0
0
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
Load Current (mA)
Load Current (mA)
Figure 13. Output Regulation vs. Load Current and Input
Voltage, VOUT=1.2 V
Figure 14. Output Regulation vs. Load Current and Input
Voltage, VOUT=0.9 V
1,000
1,000
800
800
600
600
400
400
PFM Exit
PFM Exit
PFM Enter
5.0 5.5
PFM Enter
5.0 5.5
200
200
2.5
3.0
3.5
4.0
4.5
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
Input Voltage (V)
Figure 15. PFM Entry / Exit Level vs. Input Voltage,
VOUT=1.2 V
Figure 16. PFM Entry / Exit Level vs. Input Voltage,
VOUT=0.9 V
25
3,000
2,500
2,000
1,500
3.6VIN, 1.2VOUT, Auto
3.6VIN, 1.2VOUT, PWM
5.0VIN, 1.2VOUT, Auto
5.0VIN, 1.2VOUT, PWM
5.0VIN, 0.9VOUT, Auto
20
15
10
5
1,000
3.6VIN, 1.2VOUT, Auto
3.6VIN, 0.9VOUT, Auto
500
5.0VIN, 1.2VOUT, Auto
5.0VIN, 0.9VOUT, Auto
0
0
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000 5000
Load Current (mA)
Load Current (mA)
Figure 17. Output Ripple vs. Load Current, VIN=5 V and
3.6 V, VOUT=1.2 V and 0.9 V, Auto and FPWM
Figure 18. Frequency vs. Load Current, VIN=5 V and 3.6 V,
VOUT=1.2 V and 0.9 V, Auto PWM
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
12
Typical Characteristics (Continued)
Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25°C; circuit and
components according to Figure 1 and Table 1.
80
70
60
50
40
30
20
60
50
40
30
20
10
0
-40C
+25C
+85C
-40C
+25C
+85C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Supply Voltage (V)
InputVoltage (V)
Figure 19. Quiescent Current vs. Input Voltage and
Temperature, Auto PWM
Figure 20. Quiescent Current vs. Input Voltage and
Temperature, FPWM
60
50
40
70
3.6VIN, 1.2VOUT, 2A Load
3.6VIN, 0.9VOUT, 2A Load
60
5.0VIN, 0.9VOUT, 18mA Load, PFM
50
40
30
20
30
EN_BUCK=0, -40C
EN_BUCK=0, +25C
20
EN_BUCK=0, +85C
EN=0, +25C
10
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
10
100
1,000
10,000
100,000
InputVoltage (V)
Frequency (Hz)
Figure 21. Shutdown Current vs. Input Voltage
and Temperature
Figure 22. PSRR vs. Frequency
Figure 23. Line Transient, 3-4 VIN, 1.2 VOUT, 10 µs Edge,
Figure 24. Line Transient, 3-4 VIN, 1.2 VOUT, 10 µs Edge,
1 A Load
50 Ω Load
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
13
Typical Characteristics (Continued)
Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25°C; circuit and
components according to Figure 1 and Table 1.
Figure 25. Load Transient, 5 VIN, 0.9 VOUT, 0.3-3 A,
100 ns Edge
Figure 26. Load Transient, 3.6 VIN, 1.2 VOUT, 0.3-3 A,
100 ns Edge
Figure 27. Load Transient, 3.6 VIN, 1.2 VOUT, 0.3-3 A,
100 ns Edge, COUT=4x22 µF
Figure 28. Load Transient, 3.6 VIN, 1.2 VOUT, 1.5-6 A,
100 ns Edge, COUT=4x22 µF
Figure 29. Input Over-Voltage Protection
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
14
Typical Characteristics (Continued)
Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25°C; circuit and
components according to Figure 1 and Table 1.
Figure 30. Startup / Shutdown, No Load, VOUT=0.9 V
Figure 31. Startup / Shutdown, 180 m Load, VOUT=0.9 V
Figure 32. Overload Protection and Recovery
Figure 33. Startup into Faulted Load, VOUT=0.9 V
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
15
Operation Description
The FAN53555 is a step-down switching voltage regulator that
delivers a programmable output voltage from an input voltage
supply of 2.5 V to 5.5 V. Using a proprietary architecture with
synchronous rectification, the FAN53555 is capable of
delivering 5 A at over 80% efficiency. Pulse currents as high
as 6.5 A can be supported by the 05 option. The regulator
operates at a nominal frequency of 2.4 MHz at full load, which
reduces the value of the external components to 330 nH for
the output inductor and 22 µF for the output capacitor. High
efficiency is maintained at light load with single-pulse PFM.
soft-start, allowing the IC to start into a pre-charged
capacitive load.
If large output capacitance values are used, the regulator may
fail to start. Maximum COUT capacitance for successfully starting
with a heavy constant-current load is approximately:
320
VOUT
COUTMAX
ILIMPK ILOAD
(1)
where COUTMAX is expressed in F and ILOAD is the load
current during soft-start, expressed in A.
The FAN53555 integrates an I2C-compatible interface,
allowing transfers up to 3.4 Mbps. This communication
interface can be used to:
If the regulator is at its current limit for 16 consecutive current
limit cycles, the regulator shuts down and enters 3-state
before reattempting soft-start 1700 ms later. This limits the
duty cycle of full output current during soft-start to prevent
excessive heating.
.
Dynamically re-program the output voltage in 10 mV,
12.826 mV (option 04, 042, and option 09) or 12.967
mV (option 24) increments;
The IC allows for software enable of the regulator, when EN is
HIGH, through the BUCK_EN bits. BUCK_EN0 and
BUCK_EN1 are both initialized HIGH in the 00, 04, 24, 042,
and 09 options. These options start after a POR regardless of
the state of the VSEL pin.
.
.
.
Reprogram the mode to enable or disable PFM;
Control voltage transition slew rate; or
Enable / disable the regulator.
Control Scheme
In the 01 and 05 options, BUCK_EN0 and BUCK_EN1 are
initialized to 10. Using these options, VSEL must be LOW
after a POR if the IC is powering the processor used to
communicate through I2C. The 03 option has the VSEL input
to the modulator logic internally tied LOW.
The FAN53555 uses a proprietary non-linear, fixed-frequency
PWM modulator to deliver a fast load transient response,
while maintaining a constant switching frequency over a wide
range of operating conditions. The regulator performance is
independent of the output capacitor ESR, allowing for the use
of ceramic output capacitors. Although this type of operation
normally results in a switching frequency that varies with input
voltage and load current, an internal frequency loop holds the
switching frequency constant over a large range of input
voltages and load currents.
Table 5. Hardware and Software Enable
Pins
BITS
EN VSEL BUCK_EN0 BUCK_EN1 Output
0
1
1
1
1
X
0
0
1
1
X
0
X
X
X
0
OFF
OFF
ON
For very light loads, the FAN53555 operates in Discontinuous
Current Diode (DCM) single-pulse PFM, which produces low
output ripple compared with other PFM architectures.
Transition between PWM and PFM is relatively seamless,
providing a smooth transition between DCM and CCM Modes.
1
X
X
OFF
ON
1
PFM can be disabled by programming the MODE bit HIGH in
the VSEL registers.
VSEL Pin and I2C Programming Output Voltage
Enable and Soft-Start
The output voltage is set by the NSELx control bits in VSEL0
and VSEL1 registers. The output voltage for options 00, 01,
03, 05, 08, and 18 is given as:
When the EN pin is LOW; the IC is shut down, all internal
circuits are off, and the part draws very little current. In this
state, I2C cannot be written to or read from. For all options
except the 04, 24 and 042 options, all register values are kept
while EN pin is LOW. For the 04, 24 and 042 options, registers
are reset to default values when EN pin is LOW. For all
options, registers are reset to default values during a Power
On Reset (POR).
VOUT 0.60V NSELx10mV
(2)
For example, when NSEL = 011111 (31 decimal), then VOUT
0.60 + 0.310 = 0.91 V.
=
For the 04, 042, and 09 options; the output voltage is given as:
When the OUTPUT_DISCHARGE bit in the CONTROL
register is enabled (logic HIGH) and the EN pin is LOW or the
BUCK_ENx bit is LOW, a load is connected from VOUT to
GND to discharge the output capacitors.
VOUT 0.603V NSELx12.826mV
(3)
(4)
For the 13 option, the output voltage is given as:
VOUT 0.80V NSELx10mV
Raising EN while the BUCK_ENx bit is HIGH activates the
part and begins the soft-start cycle. During soft-start, the
modulator’s internal reference is ramped slowly to minimize
surge currents on the input and prevent overshoot of the
output voltage. Synchronous rectification is inhibited during
For the 24 option, the output voltage is given as:
VOUT 0.603V NSELx 12.967mV
(5)
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
16
Output voltage can also be controlled by toggling the VSEL
pin LOW or HIGH. VSEL LOW corresponds to VSEL0 and
VSEL HIGH corresponds to VSEL1. Upon POR, VSEL0 and
VSEL1 are reset to their default voltages, shown in Table 9.
Thermal Shutdown
When the die temperature increases, due to a high load
condition and/or high ambient temperature, the output
switching is disabled until the die temperature falls sufficiently.
The junction temperature at which the thermal shutdown
activates is nominally 150°C with a 17°C hysteresis.
Transition Slew Rate Limiting
When transitioning from a low to high voltage, the IC can be
programmed for one of eight possible slew rates using the
SLEW bits in the CONTROL register.
Monitor Register (Reg05)
The Monitor register indicates of the regulation state of the IC.
If the IC is enabled and is regulating, its value is (1000 0000).
Table 6. Transition Slew Rate
I2C Interface
Decimal
Bin
Slew Rate
64.00
The FAN53555’s serial interface is compatible with Standard,
Fast, Fast Plus, and HS Mode I2C-Bus® specifications. The
FAN53555’s SCL line is an input and its SDA line is a bi-
directional open-drain output; it can only pull down the bus
when active. The SDA line only pulls LOW during data reads
and when signaling ACK. All data is shifted in MSB (bit 7) first.
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
32.00
16.00
8.00
4.00
2.00
1.00
0.50
I2C Slave Address
In hex notation, the slave address assumes a 0 LS Bit. The
hex slave address is C0 for all options except -42, which has a
hex slave address of C4.
Table 7. I2C Slave Address
Bits
Transitions from high to low voltage rely on the output load to
discharge VOUT to the new setpoint. Once the high-to-low
transition begins, the IC stops switching until VOUT has
reached the new setpoint.
Option
Hex
7
6
5
4
3
2
1
0
00 to 24
42
C0
C4
1
1
1
1
0
0
0
0
0
0
0
1
0
0
Under-Voltage Lockout
R/W
R/W
When EN is HIGH, the under-voltage lockout keeps the part
from operating until the input supply voltage rises HIGH
enough to properly operate. This ensures proper operation of
the regulator during startup or shutdown.
Other slave addresses can be assigned. Contact a Fairchild
Semiconductor representative.
Bus Timing
Input Over-Voltage Protection (OVP)
As shown in Figure 34, data is normally transferred when SCL
is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge of
SCL to allow ample time for the data to set up before the next
SCL rising edge.
When VIN exceeds VSDWN (about 6.2 V) the IC stops switching
to protect the circuitry from internal spikes above 6.5 V. An
internal filter prevents the circuit from shutting down due to
noise spikes.
Power Good (03 Option)
Data change allowed
The PGOOD pin is an open-drain output indicating that the
regulator is enabled when its state is HIGH. PGOOD pulls
LOW under the following conditions:
SDA
tH
.
Regulator is disabled (EN pin LOW, disabled by I2C, fault
time-out, UVLO, OVP, over-temperature);
tSU
SCL
.
Regulator is performing a soft-start.
Figure 34. Data Transfer Timing
PGOOD remains HIGH during I2C initiated VOUT transitions.
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which is
defined as SDA transitioning from 1 to 0 with SCL HIGH, as
shown in Figure 35.
Current Limiting
A heavy load or short circuit on the output causes the current
in the inductor to increase until a maximum current threshold
is reached in the high-side switch. Upon reaching this point,
the high-side switch turns off, preventing high currents from
causing damage. Sixteen consecutive current limit cycles in
current limit cause the regulator to shut down and stay off for
about 1700 s before attempting a restart.
tHD;STA
Slave Address
MS Bit
SDA
SCL
Figure 35. START Bit
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
17
A transaction ends with a STOP condition, which is defined as
SDA transitioning from 0 to 1 with SCL HIGH, as shown in
Figure 36.
Read and Write Transactions
The following figures outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
Slave Releases
Master Drives
tHD;STO
Master Drives Bus
All addresses and data are MSB first.
Table 8. I2C Bit Definitions for Figure 38 & Figure 39
Slave Drives Bus
defined as
and
.
ACK(0) or
NACK(1)
SDA
SCL
Symbol
Definition
REPEATED START, see Figure 37
STOP, see Figure 36
R
P
S
Figure 36. STOP Bit
During a read from the FAN53555, the master issues a
REPEATED START after sending the register address, and
before resending the slave address. The REPEATED START
is a 1 to 0 transition on SDA while SCL is HIGH, as shown in
Figure 37.
START, see Figure 35
ACK. The slave drives SDA to 0 to
acknowledge the preceding packet.
A
A
NACK. The slave sends a 1 to NACK the
preceding packet.
Slave Releases
tSU;STA
tHD;STA
R
P
REPEATED START, see Figure 37.
STOP, see Figure 36.
ACK(0) or
NACK(1)
SLADDR
MS Bit
SDA
SCL
Figure 37. REPEATED START Timing
High-Speed (HS) Mode
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) Modes are identical, except the bus speed
for HS mode is 3.4 MHz. HS Mode is entered when the bus
master sends the HS master code 00001XXX after a START
condition. The master code is sent in Fast or Fast-Plus Mode
(less than 1 MHz clock); slaves do not ACK this transmission.
The master generates a REPEATED START condition (Figure
35) that causes all slaves on the bus to switch to HS Mode.
The master then sends I2C packets, as described above,
using the HS Mode clock rate and timing.
The bus remains in HS Mode until a STOP bit (Figure 36) is
sent by the master. While in HS Mode, packets are separated
by REPEATED START conditions (Figure 37).
0
0
0
7 bits
8 bits
8 bits
Data
S
Slave Address
0
A
Reg Addr
A
A
P
Figure 38. Write Transaction
0
0
0
1
7 bits
Slave Address
8 bits
7 bits
8 bits
Data
S
0
A
Reg Addr
A
R
Slave Address
1
A
A
P
Figure 39. Read Transaction
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
18
Register Description
Table 9. Register Map
POR Default
Hex
Address
Name
Function
Option
00
VOUT
Binary
Hex
1.050
1.020
10101101
10101010
10011110
10100111
10110000
10100011
10100111
11111100
01101000
11101111
10101111
10110111
10100011
11100111
AD
AA
9E
A7
B0
A3
A7
FC
68
08, 18
01, 03, 05 0.900
00
VSEL0
Controls VOUT settings when VSEL pin = 0
04,
24
1.100
1.225
1.150
1.100
1.200
1.000
1.200
1.212
1.150
1.150
1.100
13
09
00
01, 05
04,
24
EF
AF
B7
A3
E7
01
02
03
VSEL1
Controls VOUT settings when VSEL pin = 1
Determines whether VOUT output discharge is
08, 18
13
09
00, 01, 03,
04, 05, 24
10000000
80
CONTROL enabled and also the slew rate of positive
transitions
08, 09, 18
00000000
10110000
10000000
10000001
10000011
10000100
10000101
10001000
10001100
0000XXXX
X0000000
00
B0
80
81
83
84
85
88
8C
0X
X0
13
00, 13, 24
01
03
ID1
ID2
Read-only register identifies vendor and chip type
Read-only register identifies die revision
04
05
08, 18
09
04
05
All
MONITOR Indicates device status
All
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
19
Bit Definitions
The following table defines the operation of each register bit. Bold indicates power-on default values.
Bit
Name
Value
Description
VSEL0
R/W
Register Address: 00
Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is HIGH,
BUCK_EN bit takes precedent.
7
6
BUCK_EN0
MODE0
1
0
Allow Auto-PFM Mode during light load
Forced PWM Mode
1
00 Option
101101
08, 18 Options
Sets VOUT value from 0.60 to 1.23 V (see Eq. (2)).
101010
01, 03, 05 Options
011110
5:0
NSEL0
04 Option
Sets VOUT value from 0.603 to 1.411 V (see Eq. (3)).
Sets VOUT value from 0.603 to 1.411 V (see Eq. (3)).
Sets VOUT value from 0.80 to 1.43 V (see Eq. (4))
Sets VOUT value from 0.603 to 1.420 V (see Eq. (5)).
100111
09 Option
100111
13 Option
100011
24 Option
110000
VSEL1
R/W
Register Address: 01
00, 04, 08, 09,13,
18, 24 Options
Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is HIGH,
BUCK_EN bit takes precedent.
1
7
BUCK_EN1
01, 05 Options
0
08, 13, 18, 24
Options
Allow AUTO-PFM Mode during light load
Forced PWM Mode
0
6
MODE1
00, 01, 04, 05, 09
Options
1
00 Option
111100
01, 05 Options
Sets VOUT value from 0.60 to 1.23 V (see Eq. (2)).
101000
08, 18 Options
110111
04 Option
101111
5:0
NSEL1
Sets VOUT value from 0.603 to 1.411 V (see Eq. (3)).
Sets VOUT value from 0.603 to 1.420 V (see Eq. (5)).
Sets VOUT value from 0.603 to 1.411 V (see Eq. (3)).
Sets VOUT value from 0.800 to 1.43 V (see Eq. (4))
24 Option
101111
09 Option
100111
13 Option
100011
CONTROL
R/W
Register Address: 02
08, 09, 18 Options
When the regulator is disabled, VOUT is not discharged.
0
7
OUTPUT_DISCHARGE
00, 01, 03, 04,
05,13,24, Options
When the regulator is disabled, VOUT discharges through an internal pull-down.
1
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
20
Bit Definitions
The following table defines the operation of each register bit. Bold indicates power-on default values.
Bit
Name
Value
000 –111
011
Description
Sets the slew rate for positive voltage transitions (see Table 6).
Default value for 13 option
6:4
SLEW
3
2
Reserved
0
Always reads back 0
04, 09, 24 Options
RESET
Setting to 1 resets all registers to default values.
0
All other options
Reserved
Always reads back 0
Always reads back 00
0
1:0
ID1
7:5
4
Reserved
R
00
Register Address: 03
VENDOR
Reserved
100
0
Signifies Fairchild as the IC vendor
Always reads back 0
0000
0001
0011
0100
0100
0101
1000
IC Type = 00 Option (FAN53555UC00X / FAN53555BUC24X)
IC Type = 01 Option (FAN53555UC01X)
IC Type = 03 Option (FAN53555UC03X)
IC Type = 04 Option (FAN53555UC04X)
IC Type = 042 Option (FAN53555UC042X)
IC Type = 05 Option (FAN53555UC05X / FAN53555BUC05X)
3:0
DIE_ID
IC Type = 08, 18 Options (FAN53555UC08X / FAN53555BUC08X, FAN53555UC18X /
FAN53555BUC18X)
1100
0000
IC Type = 09 Option (FAN53555UC09X / FAN53555BUC09X)
IC Type = 13 Option (FAN53555UC13X / FAN53555BUC13X)
ID2
R
Register Address: 04
7:4
Reserved
0000
Always reads back 0000
00 Option
0011
01 Option
0011
03 Option
0011
04 Option
1111
24-Option
0100
042 Option
3:0
DIE_REV
IC mask revision
1111
05 Option
0011
08, 18 Options
0001
BUC08, BUC18
Options
1111
09 Option
1111
13 Option
1111
MONITOR
R
PGOOD
Not used
Register Address: 05
7
0
1: buck is enabled and soft-start is completed
Always reads back 000 0000
6:0
000 0000
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
21
Application Information
Selecting the Inductor
The output inductor must meet both the required inductance
and the energy-handling capability of the application. The
inductor value affects the average current limit, the output
voltage ripple, and the efficiency.
Increasing COUT has negligible effect on loop stability and
can be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, ∆VOUT, is
calculated by:
2
f
C
2D
ESR
1
SW
OUT
V
I
(9)
OUT
L
The ripple current (∆I) of the regulator is:
1D
8 f
C
SW OUT
where COUT is the effective output capacitance.
VOUT V VOUT
IN
I
(6)
V
LfSW
IN
The capacitance of COUT decreases at higher output voltages,
which results in higher ∆VOUT. Equation (9) is only valid for
Continuous Current Mode (CCM) operation, which occurs
when the regulator is in PWM Mode.
The maximum average load current, IMAX(LOAD), is related to
the peak current limit, ILIM(PK), by the ripple current such that:
I
2
For large COUT values, the regulator may fail to start under
a load. If an inductor value greater than 1.0 H is used, at
least 30 F of COUT should be used to ensure stability.
(7)
I
I
MAX(LOAD)
LIM(PK )
The FAN53555 is optimized for operation with L=330 nH, but
is stable with inductances up to 1.0 H (nominal). The
inductor should be rated to maintain at least 80% of its value
at ILIM(PK). Failure to do so lowers the amount of DC current
the IC can deliver.
The lowest ∆VOUT is obtained when the IC is in PWM Mode
and, therefore, operating at 2.4 MHz. In PFM Mode, fSW is
reduced, causing ∆VOUT to increase.
ESL Effects
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since ∆I increases, the
RMS current increases, as do core and skin-effect losses.
The Equivalent Series Inductance (ESL) of the output
capacitor network should be kept low to minimize the square-
wave component of output ripple that results from the division
ratio COUT ESL and the output inductor (LOUT). The square-
wave component due to the ESL can be estimated as:
2
I
2
(8)
I
I
RMS
OUT(DC)
ESLCOUT
12
(10)
VOUT(SQ) VIN
L1
The increased RMS current produces higher losses through
the RDS(ON) of the IC MOSFETs as well as the inductor ESR.
A good practice to minimize this ripple is to use multiple output
capacitors to achieve the desired COUT value. For example, to
obtain COUT=20 F, a single 22 F 0805 would produce twice
the square wave ripple as two x 10 F 0805.
Increasing the inductor value produces lower RMS currents,
but degrades transient response. For a given physical inductor
size, increased inductance usually results in an inductor with
lower saturation current.
To minimize ESL, try to use capacitors with the lowest ratio of
length to width. 0805s have lower ESL than 1206s. If low
output ripple is a chief concern, some vendors produce 0508
or 0612 capacitors with ultra-low ESL. Placing additional
small-value capacitors near the load also reduces the high-
frequency ripple components.
Table 10. Effects of Inductor Value (from 330 nH
Recommended) on Regulator Performance
(Eq.(10))
IMAX(LOAD)
∆VOUT
Transient Response
Increase
Decrease
Degraded
Input Capacitor
Inductor Current Rating
The ceramic input capacitors should be placed as close as
possible between the VIN pin and PGND to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or tantalum)
should be placed between CIN and the power source lead to
reduce under-damped ringing that can occur between the
inductance of the power source leads and CIN.
The current limit circuit can allow substantial peak currents to
flow through L1 under worst-case conditions. If it is possible
for the load to draw such currents, the inductor should be
capable of sustaining the current or failing in a safe manner.
For space-constrained applications, a lower current rating for
L1 can be used. The FAN53555 may still protect these
inductors in the event of a short circuit, but may not be able to
protect the inductor from failure if the load is able to draw
higher currents than the DC rating of the inductor.
The effective CIN capacitance value decreases as VIN
increases due to DC bias effects. This has no significant
impact on regulator performance.
Output Capacitor and VOUT Ripple
Table 1 suggests 0805 capacitors, but 0603 capacitors may
be used if space is at a premium. Due to voltage effects, the
0603 capacitors have a lower in-circuit capacitance than the
0805 package, which can degrade transient response and
output ripple.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
22
4. Determine IC losses by removing inductor losses (step 3)
from total dissipation:
Thermal Considerations
Heat is removed from the IC through the solder bumps to the
PCB copper. The junction-to-ambient thermal resistance (JA)
is largely a function of the PCB layout (size, copper weight,
and trace width) and the temperature rise from junction to
ambient (T).
P
P PL
(13)
IC
T
5. Determine device operating temperature:
T P JA
IC
For the FAN53555UC, JA is 38°C/W when mounted on its
four-layer evaluation board in still air with two-ounce outer
layer copper weight and one-ounce inner layers. Halving the
copper thickness results in an increased JA of 48°C/W.
and
(14)
TIC TA T
It is important to note that the RDS(ON) of the IC’s power
MOSFETs increases linearly with temperature at about
1.21%/°C. This causes the efficiency () to degrade with
increasing die temperature.
For long-term reliable operation, the IC’s junction temperature
(TJ) should be maintained below 125°C.
To calculate maximum operating temperature (<125°C) for a
specific application:
Layout Recommendations
1. Use efficiency graphs to determine efficiency for the
desired VIN, VOUT, and load conditions.
1. The input capacitor (CIN) should be connected as close
as possible to VIN and GND. Connect to VIN and GND
using only top metal. Do not route through vias.
2. Calculate total power dissipation using:
2. Place the inductor (L) as close as possible to the IC.
Use short wide traces for the main current paths.
Connect to SW using only top metal.
1
1
P VOUT ILOAD
T
(11)
3. The output capacitor (COUT) should be as close as
possible to the IC. Connection to GND should only be
on top metal. Feedback signal connection to VOUT
should be routed away from noisy components and
traces (e.g. SW line).
where η is efficiency from Figure 7 through Figure 12.
3. Estimate inductor copper losses using:
P ILOAD2 DCRL
(12)
L
4. Do not use remote sensing; the IC was not designed
for this.
Figure 40. WLCSP 5 A Recommended Layout
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
23
Physical Dimensions
F
BALL A1
E
A
INDEX AREA
1.20
1.20
B
Ø0.215
Cu Pad
Ø0.20
Cu Pad
0.03 C
2X
A1
A1
1.60
D
0.40
Ø0.315 Solder
Mask Opening
Ø0.30 Solder
Mask Opening
0.40
0.40
0.03 C
2X
option 1
option 2
TOP VIEW
RECOMMENDED LAND PATTERN
(NSMD TYPE)
0.06
0.625
0.547
C
0.378±0.018
0.208±0.021
E
0.05
C
C
D
SEATING PLANE
SIDE VIEWS
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
0.005
C A B
1.20
Ø0.260±0.02
20X
0.40
0.40
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
E
D
C
B
1.60
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
(Y) ±0.018
F
A
E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
2
3
4
1
(X) ±0.018
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
BOTTOM VIEW
G. DRAWING FILNAME: MKT-UC020AArev3.
Figure 41. 20-Ball, Wafer-Level Chip-Scale Package (WLCSP), 4x5 Array, 0.4 mm Pitch, 250 µm Ball
Product-Specific Dimensions
Product
D
E
X
Y
Land Pattern
FAN53555UC00 to FAN53555UC08X, FAN53555BUC05X 2.000 ±0.03 1.600 ±0.03
0.200
0.200
Option 1
FAN53555UC24X, FAN53555BUC24X,
FAN53555BUC08X, FAN53555BUC09X,
FAN53555UC09X, FAN53555UC13X, FAN53555BUC13X,
F FAN53555UC18X, FAN53555BUC18X
2.015 ±0.03 1.615 ±0.03 0.2075 0.2075
Option 2
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/UC/UC020AA.pdf.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
24
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53555 • Rev. 1.1.7
25
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