FAN5365UC00X_技术文档

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August 2011

FAN5365

1A / 0.8A, 6MHz Digitally Programmable Regulator

Features

Description

The FAN5365 is a high-frequency, ultra-fast transient

response, synchronous step-down, DC-DC converter

optimized for low-power applications using small, low-cost

inductors and capacitors. The FAN5365 supports up to

800mA or 1A load current.

. High Efficiency (>88%) at 6MHz

. 800mA or 1A Output Current

. Regulation Maintained with V_INfrom 2.3V to 5.5V

. 6-Bit V_OUTProgrammable from 0.75 to 1.975V

. 6MHz Fixed-Frequency Operation (PWM Mode)

. Excellent Load and Line Transient Response

. Small Size, 470nH Inductor Solution

The FAN5365 is ideal for mobile phones and similar portable

applications powered by a single-cell Lithium-Ion battery.

With an output voltage range adjustable via I²C™ interface

from 0.75V to 1.975V, it supports low-voltage DSPs and

processors, core power supplies, and memory modules in

smart phones, data cards, and hand-held computers.

. ±2% DC Voltage Accuracy in PWM Mode

. 25ns Minimum On-Time

The FAN5365 operates at 6MHz (nominal) fixed switching

frequency in PWM mode.

. High-Efficiency, Low-Ripple, Light-Load PFM

. Smooth Transition between PWM and PFM

. 40A Operating PFM Quiescent Current

. I²C™-Compatible Interface up to 3.4Mbps

. Pin-Selectable or I²C™ Programmable Output Voltage

. 9-Bump, 1.27 x 1.29mm, 0.4mm Pitch WLCSP Package

During light-load conditions, the regulator includes a PFM

mode to enhance light-load efficiency. The regulator

transitions smoothly between PWM and PFM modes with no

glitches on V_OUT. In hardware shutdown, the current

consumption is reduced to less than 200nA.

The serial interface is compatible with fast / standard mode,

fast mode plus, and high-speed mode I²C specifications,

allowing transfers up to 3.4Mbps. This interface is used for

dynamic voltage scaling with 12.5mV voltage steps, for

reprogramming the mode of operation (PFM or forced

PWM), or to disable/enable the output voltage.

Applications

. 3G, WiFi^®, WiMAX™, and WiBro^®Data Cards

. Netbooks^®, Ultra-Mobile PCs

The chip's advanced protection features include short-circuit

protection and current and temperature limits. During a

sustained over-current event, the IC shuts down and restarts

after a delay to reduce average power dissipation into a

fault.

. SmartReflex™-Compliant Power Supply

. Split Supply DSPs and P Solutions OMAP™, XSCALE™

. Handset Graphic Processors (NVIDIA^®, ATI)

During startup, the IC controls the output slew rate to

minimize input current and output overshoot at the end of

soft-start. The IC maintains a consistent soft-start ramp,

regardless of output load during startup.

The FAN5365 is available in a 1.27 x 1.29mm, 9-bump

WLCSP package.

All trademarks are the property of their respective owners

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

Ordering Information

Output

Current

Power-up

Defaults

Slave Address LSB

V_OUTProgramming

Part Number⁽¹⁾Option

Package

A2

0

A1

1

A0

0

mA

800

Min.

Max.

1.4375⁽³⁾

1.4375⁽³

VSEL0 VSEL1

FAN5365UC00X

FAN5365UC02X

FAN5365UC03X⁽²⁾

FAN5355UC06X⁽²⁾

Notes:

00

02

03

06

0.7500

1.1875

1.05

0.95

1.00

1.80

1.20

1.10

1.20

1.80

WLCSP-09

)

1

0

800

0

1000

1.5375

1.9750

0

1. The “X” designator on the part number indicates tape and reel packaging.

2. Preliminary; not full production release at this time. Contact a Fairchild representative for information.

3. V_OUTis limited to the maximum voltage for all VSEL codes greater than the maximum V_OUTlisted.

Typical Application

VIN

Q1

C_IN

EN

VSEL

VOUT

SW

Q2

L

MODULATOR

C_OUT

SDA

SCL

PGND

VOUT

AGND

Figure 1. Typical Application

Table 1. Recommended External Components

Component

Description

Vendor

Parameter

Min. Typ. Max. Units

L⁽⁴⁾

390

470

80

600

nH

m

F

L (L_OUT

)

470nH Nominal

Murata, TDK, FDK

DCR (Series R)

C⁽⁶⁾

(5)

C_OUT

Various

2.2

1.6

10.0

4.7

15.0

0603 (1.6x0.8x0.8), 10F X5R

0402 (1x0.5x0.25), 4.7F X5R

C_IN

Taiyo-Yuden

F

Notes:

4. Minimum L incorporates tolerance, temperature, and partial saturation effects (L decreases when increasing current).

5. A capacitor similar to C_INcan be used for C_OUT. With 1.4V of bias, a 4.7F 0402 capacitor minimum value is 2.5F.

The regulator is stable, but transient response degraded due to large signal effects.

6. Minimum C is a function of initial tolerance, maximum temperature, and the effective capacitance being reduced due to

frequency, dielectric, and voltage bias effects. C_INis biased with a higher voltage which reduces its effective capacitance

by a larger amount.

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

2

Pin Configuration

A1

A2

B2

C2

A3

B3

C3

A3

B3

C3

A2

B2

C2

A1

B1

C1

B1

C1

Bumps Facing Down

Bumps Facing Up

Figure 2. WLCSP-09, 0.4mm Pitch

Pin Definitions

Pin # Name

Description

Voltage Select. When HIGH, V_OUTis set by VSEL1. When LOW, V_OUTis set by VSEL0. This behavior

A1

A2

VSEL

VIN

can be overridden through I²C register settings. This pin should not be left floating.

Input Voltage. Connect to input power source. The connection from this pin to C_INshould be as short as

possible.

A3

B1

B2

SDA

SW

SDA. I²C interface serial data. This pin should not be left floating.

Switching Node. Connect to output inductor.

SCL

SCL. I²C interface serial clock. This pin should not be left floating.

Enable. When this pin is HIGH, the circuit is enabled. When LOW, part enters shutdown mode and

input current is minimized. This pin should not be left floating.

B3

C1

C2

C3

EN

Output Voltage Monitor. Tie this pin to the output voltage at C_OUT. This is a signal input pin to the

control circuit and does not carry DC current.

VOUT

PGND

AGND

Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB. The

connection from this pin to the bottom of C_INshould be as short as possible.

Analog GND. This is the signal ground reference for the IC. All voltage levels are measured with

respect to this pin. AGND should be connected to PGND at a single point.

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable

above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,

extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute

maximum ratings are stress ratings only.

Symbol

Parameter

Min.

–0.3

Max.

6.5

Units

VIN, SW Pins

V_OUT

V_CC

2.5

V_IN+ 0.3⁽⁷⁾

V

Other Pins

Human Body Model, JESD22-A114

Charged Device Model, JESD22-C101

3

1

ESD

Electrostatic Discharge Protection

KV

T_J

T_STG

T_L

Junction Temperature

Storage Temperature

–40

–65

+150

+260

°C

Lead Soldering Temperature, 10 Seconds

Note:

7. Lesser of 6.5V or V_CC+0.3V.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating

conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend

exceeding them or designing to absolute maximum ratings.

Symbol

Parameter

Min.

2.3

Max.

5.5

Units

V

V_IN

V_CCIO

T_A

Supply Voltage

SDA and SCL Voltage Swing⁽⁸⁾

Ambient Temperature

Junction Temperature

1.2

2.0

V

–40

+85

+125

°C

T_J

°C

Note:

8. The I²C interface operates with t_HD;DAT= 0 as long as the pull-up voltage for SDA and SCL is less than 2.5V. If voltage

swings greater than 2.5V are required (for example, if the I²C bus is pulled up to V_IN), the minimum t_HD;DATmust be

increased to 80ns. Most I²C masters change SDA near the midpoint between the falling and rising edges of SCL, which

provides ample t_HD;DAT

.

Dissipation Ratings⁽⁹⁾

Power Rating

at T_A≤ 25°C

Derating Factor

> T_A= 25ºC

(10₎

Package

R_θJA

Wafer-Level Chip-Scale Package (WLCSP)

110ºC/W

900mW

9mW/ºC

Notes:

9. Maximum power dissipation is a function of T_J(max), θ_JA, and T_A. The maximum allowable power dissipation at any

allowable ambient temperature is P_D= [T_J(max)- T_A] / θ_JA.

10. This thermal data is measured with a high-K board (four-layer board, according to the JESD51-7 JEDEC standard).

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

4

Electrical Specifications

Unless otherwise noted, over the recommended operating range for V_INand T_A, EN = VSEL = SCL = SDA = 1.8V, and register

VSEL0[6] bit = 1. Typical values are at V_IN= 3.6V, T_A= 25°C. Circuit and components according to Figure 1.

Symbol Parameter

Power Supplies

Conditions

Min.

Typ.

Max. Units

I_O= 0mA, PFM Mode, 2.3V<=V_IN<=4.5V

I_O= 0mA, PFM Mode, 2.3V<=V_IN<=5.5V

I_O= 0mA, 6MHz PWM Mode

40

55

A

65

I_Q

Quiescent Current

6.3

mA

EN = GND

0.1

1.0

I_SD

Shutdown Supply Current

A

EN = V_IN, EN_DCDC bit = 0,

SDA = SCL = 1.8V (Software Shutdown)

N/A

V_INRising

V_INFalling

2.18

2.02

160

2.25

V

mV

V_UVLOUnder-Voltage Lockout Threshold

1.95

1.05

V_UVHYSTUnder-Voltage Lockout Hysteresis

ENABLE, VSEL, SDA, SCL

V_IH

V_IL

I_IN

HIGH-Level Input Voltage

LOW-Level Input Voltage

Input Bias Current

V

0.4

Input Tied to GND or V_IN

0.01

1.00

A

Power Switch and Protection

P-Channel MOSFET On

Resistance

R_DS(ON)P

V_IN= 3.6V

V_DS= 5.5V

V_IN= 3.6V

300

0.2

mΩ

A

mΩ

A

I_LKGP

R_DS(ON)N

I_LKGN

P-Channel Leakage Current

1.0

N-Channel MOSFET On

Resistance

200

N-Channel Leakage Current

V_DS= 5.5V

0.3

1350

1550

150

20

1.0

Options 00, 02

Options 03, 06

1150

1300

1600

1840

I_LIMPK

P-MOS Current Limit

mA

T_LIMITThermal Shutdown

T_HYSTThermal Shutdown Hysteresis

Frequency Control

°C

f_SW

Output Regulation

Switching Frequency⁽¹¹⁾

PWM Operation

5.4

6.0

6.6

MHz

I_OUT(DC)= 0, Forced PWM, V_OUT= VSEL1

Default Value

–1.5

–2.0

1.5

2.0

%

2.3V ≤ V_IN≤ 5.5V, V_OUTfrom Minimum to

Maximum, I_OUT(DC)= 0 to 1A, Forced PWM

V_OUT

V_OUTAccuracy

2.3V ≤ V_IN≤ 5.5V, V_OUTfrom Minimum to

Maximum, I_OUT(DC)= 0 to 1A, Auto

PWM/PFM

–2.0

3.5

%

V_OUT

I_LOAD

Load Regulation

Line Regulation

I_OUT(DC)= 0 to 1A, Forced PWM

–0.2

0

%/A

%/V

V_OUT

V_IN

2.3V ≤ V_IN≤ 5.5V, I_OUT(DC)= 300mA,

Forced PWM

PWM Mode, V_OUT= 1.2V

4

mV_P-P

V_RIPPLEOutput Ripple Voltage

PFM Mode, I_OUT(DC)= 10mA

16

Continued on the following page…

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

5

Electrical Specifications (Continued)

Unless otherwise noted, over the recommended operating range for V_INand T_A, EN = VSEL = SCL = SDA = 1.8V, and register

VSEL0[6] bit = 1. Typical values are at V_IN= 3.6V, T_A= 25°C. Circuit and components according to Figure 1.

Symbol Parameter

DAC

Conditions

Min. Typ. Max. Units

Resolution

6

Bits

Differential Nonlinearity

Monotonicity Assured by Design

0.8

LSB

Timing

I²C_EN

EN HIGH to I²C Start

250

s

Transition from 0.75V to 1.438V

t_V(L-H)

V_OUTLOW to HIGH Settling

7

V

_OUTSettled to within 2% of Setpoint

Soft-Start

t_SS

Regulator Enable to Regulated V_OUT

140

180

R_LOAD> 5, to V_OUT= Power-up Default

s

Notes:

11. Limited by the effect of t_OFFminimum (see Figure 14 in Typical Performance Characteristics).

Block Diagram

VIN

Q1

Q2

C_IN

REF

DAC

EN

VOUT

VSEL

SW

I²C

SOFT START

FPWM

L

INTERFACE

AND LOGIC

C_OUT

SDA

SCL

MODULATOR

EN_REG

CLK

PGND

VOUT

AGND

6 Mhz Osc

Figure 3 Block Diagram

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

6

I²C Timing Specifications

Guaranteed by design.

Symbol

Parameter

Conditions

Min.

Typ. Max.

Units

Standard Mode

100

400

Fast Mode

f_SCL

SCL Clock Frequency

Fast Mode Plus

1000

3400

1700

4.7

kHz

High-Speed Mode, C_B< 100pF

High-Speed Mode, C_B< 400pF

Standard Mode

Bus-free Time between STOP and

START Conditions

t_BUF

Fast Mode

1.3

s

Fast Mode Plus

0.5

Standard Mode

4

s

ns

s

ns

s

ns

s

ns

Fast Mode

600

START or Repeated START Hold

Time

t_HD;STA

Fast Mode Plus

260

High-Speed Mode

Standard Mode

160

4.7

Fast Mode

1.3

t_LOW

SCL LOW Period

SCL HIGH Period

Fast Mode Plus

0.5

High-Speed Mode, C_B< 100pF

High-Speed Mode, C_B< 400pF

Standard Mode

160.0

320.0

4

Fast Mode

600

t_HIGH

Fast Mode Plus

260

High-Speed Mode, C_B< 100pF

High-Speed Mode, C_B< 400pF

Standard Mode

60

120

4.7

Fast Mode

600.0

260.0

160.0

250

t_SU;STA

Repeated START Setup Time

Data Setup Time

Fast Mode Plus

High-Speed Mode

Standard Mode

Fast Mode

100

t_SU;DAT

ns

Fast Mode Plus

50

High-Speed Mode

Standard Mode

10

0

3.45

900.00

450.00

70.00

150.00

s

ns

Fast Mode

t_HD;DAT

Data Hold Time⁽⁸⁾

SCL Rise Time

Fast Mode Plus

High-Speed Mode, C_B< 100pF

High-Speed Mode, C_B< 400pF

Standard Mode

20+0.1C_B

10

20

1000

300

120

80

Fast Mode

t_RCL

Fast Mode Plus

ns

High-Speed Mode, C_B< 100pF

High-Speed Mode, C_B< 400pF

160

Continued on the following page…

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

7

I²C Timing Specifications (Continued)

Guaranteed by design.

Symbol

Parameter

Conditions

Min.

Typ. Max.

Units

Standard Mode

20+0.1C_B

10

300

120

40

Fast Mode

t_FCL

SCL Fall Time

Fast Mode Plus

ns

High-Speed Mode, C_B< 100pF

High-Speed Mode, C_B< 400pF

High-Speed Mode, C_B< 100pF

High-Speed Mode, C_B< 400pF

Standard Mode

20

10

20

80

Rise Time of SCL after a Repeated

START Condition and after ACK Bit

t_RCL1

ns

160

1000

300

120

80

20+0.1C_B

Fast Mode

20+0.1C_B

t_RDA

SDA Rise Time

SDA Fall Time

Fast Mode Plus

High-Speed Mode, C_B< 100pF

High-Speed Mode, C_B< 400pF

Standard Mode

10

20

20+0.1C_B

160

300

120

80

Fast Mode

20+0.1C_B

t_FDA

Fast Mode Plus

ns

High-Speed Mode, C_B< 100pF

High-Speed Mode, C_B< 400pF

Standard Mode

10

20

4

160

s

ns

pF

Fast Mode

600

120

160

t_SU;STO

Stop Condition Setup Time

Fast Mode Plus

High-Speed Mode

C_B

Capacitive Load for SDA and SCL

400

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

8

Timing Diagrams

t_F

t_SU;STA

t_BUF

SDA

t_R

T_SU;DAT

t_HD;STO

t_HIGH

t_HD;DAT

SCL

t_LOW

t_HD;STA

REPEATED

START

STOP

START

Figure 4. I²C Interface Timing for Fast Plus, Fast, and Slow Modes

REPEATED

START

STOP

t_FDA

t_RDA

t_SU;DAT

SDAH

t_SU;STA

t_RCL1

t_FCL

t_HIGH

t_HD;DAT

note A

t_RCL

t_SU;STO

SCLH

t_LOW

t_HD;STA

REPEATED

START

= MCS Current Source Pull-up

= R_PResistor Pull-up

Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.

Figure 5. I²C Interface Timing for High-Speed Mode

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

9

Typical Characteristics

Unless otherwise specified, Auto PWM/PFM, V_IN= 3.6V, SCL = SCA = VSEL = EN = 1.8V, T_A= 25°C; circuit and components

according to Figure 1.

100%

90%

80%

70%

60%

50%

40%

100%

90%

80%

70%

60%

50%

40%

2.3V Auto PFM/PWM

2.7V Auto PFM/PWM

3.6V Auto PFM/PWM

4.2V Auto PFM/PWM

5.5V Auto PFM/PWM

3.6V Forced PWM

2.3V Auto PFM/PWM

2.7V Auto PFM/PWM

3.6V Auto PFM/PWM

4.2V Auto PFM/PWM

5.5V Auto PFM/PWM

3.6V Forced PWM

1

10

100

1000

1

10

100

1000

Output Current (mA)

Figure 6. Efficiency vs. Load and Input Supply

at V_OUT= 1.1V

Figure 7. Efficiency vs. Load and Input Supply

at V_OUT= 1.2V

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

Auto PFM/PWM

Forced PWM

Auto PFM/PWM

Forced PWM

V_IN=3.6V

_OUT=1.4375V

V_IN=3.6V

V_out=0.75V

V

1

10

100

1000

1

10

100

1000

Output Current (mA)

Figure 8. Efficiency, Auto PWM/PFM vs. Forced PWM

at V_OUT= 0.75V

Figure 9. Efficiency, Auto PWM/PFM vs. Forced PWM

at V_OUT= 1.4375V

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

10

Typical Characteristics

Unless otherwise specified, Auto PWM/PFM, V_IN= 3.6V, SCL = SCA = VSEL = EN = 1.8V, T_A= 25°C; circuit and components

according to Figure 1.

1.112

1.110

1.108

1.106

1.104

1.102

1.100

1.098

1.096

1.094

1.092

1.212

1.210

1.208

1.206

1.204

1.202

1.200

1.198

1.196

1.194

1.192

Auto PFM/PWM

Forced PWM

Auto PFM/PWM

Forced PWM

1

10

100

Output Current(mA)

1000

1

10

100

Output Current(mA)

1000

Figure 10. Load Regulation, Auto PFM / PWM and

Forced PWM at V_OUT= 1.1V

Figure 11. Load Regulation, Auto PFM / PWM and

Forced PWM at V_OUT= 1.2V

0.760

1.450

1.448

1.446

1.444

1.442

1.440

1.438

1.436

1.434

1.432

1.430

0.758

0.756

0.754

0.752

0.750

0.748

0.746

Auto PFM/PWM

Forced PWM

Auto PFM/PWM

Forced PWM

1

10

100

Output Current(mA)

1000

1

10

100

1000

Output Current(mA)

Figure 12. Load Regulation, Auto PFM / PWM and

Forced PWM at V_OUT= 0.75V

Figure 13. Load Regulation, Auto PFM / PWM and

Forced PWM at V_OUT= 1.4375V

7.0

6.0

5.0

4.0

3.0

V =1.4375V

o

V =1.36V

o

2.0

1.0

V =1.3V

o

V =1.2V

o

0

200

400

600

800

1000

1200

I_OUT(mA)

Figure 14. Effect of t_OFF(MIN)on Reducing the PWM

Switching Frequency, V_IN=2.3V

FAN5365 • Rev. 1.0.6

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11

Typical Characteristics

Unless otherwise specified, Auto PWM/PFM, V_IN= 3.6V, SCL = SCA = VSEL = EN = 1.8V, T_A= 25°C; circuit and components

according to Figure 1.

15

12

9

60

55

50

45

40

-40°C

25°C

85°C

-40°C

25°C

85°C

6

35

30

3

2.3

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

2.3

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

V_IN(V)

Figure 15. Quiescent Current in PFM Mode vs. Input

Voltage and Temperature

Figure 16. Quiescent Current in PWM Mode vs. Input

Voltage and Temperature

80

1.0

-40°C

V_OUT=1.2V

70

25°C

V_OUT=1.05V

85°C

0.8

60

50

40

30

20

10

0

0.6

0.4

0.2

0.0

0.1

1

10

100

1000

2.3

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

V_IN(V)

Frequency (KHz)

Figure 17. Shutdown Current (EN = 0) vs. Input Voltage

and Temperature

Figure 18. V_INRipple Rejection (PSRR) in Forced PWM

at 200mA

FAN5365 • Rev. 1.0.6

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12

Typical Characteristics

Unless otherwise specified, Auto PWM/PFM, V_IN= 3.6V, SCL = SCA = VSEL = EN = 1.8V, T_A= 25°C; circuit and components

according to Figure 1.

Figure 19. Combined Line/Load Transient 3.0 to 3.6V_IN

Combined with 500 to 50mA Load Transient

Figure 20. Combined Line/Load Transient 3.6 to 3.0V_IN

Combined with 50 to 500mA Load Transient

Figure 21. Combined Line/Load Transient 3.0 to 3.6V_IN

Combined with 800 to 200mA Load Transient

Figure 22. Combined Line/Load Transient 3.6 to 3.0V_IN

Combined with 200 to 800mA Load Transient

FAN5365 • Rev. 1.0.6

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Typical Characteristics

Unless otherwise specified, Auto PWM/PFM, V_IN= 3.6V, SCL = SCA = VSEL = EN = 1.8V, T_A= 25°C; circuit and components

according to Figure 1.

Figure 23. VSEL Transition, Single Step (DefSlew = 7),

_LOAD= 24Ω

Figure 24. VSEL Transition, Single Step (DefSlew = 7),

R

R_LOAD= 4Ω

Figure 25. VSEL Transition, DefSlew = 0, R_LOAD= 24Ω

Figure 26. VSEL Transition, DefSlew = 0, R_LOAD= 4Ω

FAN5365 • Rev. 1.0.6

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Typical Characteristics

Unless otherwise specified, Auto PWM/PFM, V_IN= 3.6V, SCL = SCA = VSEL = EN = 1.8V, T_A= 25°C; circuit and components

according to Figure 1.

Figure 27. VSEL Transition, VSEL 1 to 0, R_LOAD= 24Ω

Figure 28. VSEL Transition, VSEL 1 to 0, R_LOAD= 4Ω

Figure 29. Shutdown, Output Discharge On

Figure 30. Shutdown, Output Discharge Off

FAN5365 • Rev. 1.0.6

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Typical Characteristics

Unless otherwise specified, Auto PWM/PFM, V_IN= 3.6V, SCL = SCA = VSEL = EN = 1.8V, T_A= 25°C; circuit and components

according to Figure 1.

Figure 31. Metallic Short Applied at V_OUT

Figure 32. Over-Current Fault Response, R_LOAD= 500mΩ

Figure 33. Soft Start, No Load

Figure 34. Soft Start, R_LOAD= 1.5Ω

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Circuit Description

The FAN5365 is a synchronous buck regulator that typically

operates at 6MHz with moderate to heavy load currents. At

light load currents, the converter operates in power-saving

PFM mode. The regulator automatically transitions between

fixed-frequency PWM mode and variable-frequency PFM

mode to maintain the highest possible efficiency over the full

range of load current.

Table 2. V_SELvs. V_OUT

VSEL Value

Dec (NVSEL) Binary Hex

VOUT

03

00, 02

0.7500

0.7625

0.7750

0.7875

0.8000

0.8125

0.8250

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

06

0

1

2

3

4

5

6

7

000000 00

000001 01

000010 02

000011 03

000100 04

000101 05

000110 06

000111 07

001000 08

001001 09

001010 0A

001011 0B

001100 0C

001101 0D

001110 0E

001111 0F

010000 10

010001 11

010010 12

010011 13

010100 14

010101 15

010110 16

010111 17

011000 18

011001 19

011010 1A

011011 1B

011100 1C

011101 1D

011110 1E

011111 1F

100000 20

100001 21

100010 22

100011 23

100100 24

100101 25

100110 26

100111 27

101000 28

101001 29

101010 2A

101011 2B

101100 2C

101101 2D

101110 2E

101111 2F

110000 30

110001 31

110010 32

110011 33

110100 34

110101 35

110110 36

110111 37

111000 38

111001 39

111010 3A

111011 3B

111100 3C

111101 3D

111110 3E

111111 3F

0.7500

0.7625

0.7750

0.7875

0.8000

0.8125

0.8250

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

1.6125

1.6250

1.6375

1.6500

1.6625

1.6750

1.6875

1.7000

1.7125

1.7250

1.7375

1.7500

1.7625

1.7750

1.7875

1.8000

1.8125

1.8250

1.8375

1.8500

1.8625

1.8750

1.8875

1.9000

1.9125

1.9250

1.9375

1.9500

1.9625

1.9750

The FAN5365 uses

a

very fast, non-linear control

architecture to achieve excellent transient response with

minimum-sized external components.

The FAN5365 integrates an I²C-compatible interface,

allowing transfers up to 3.4Mbps. This communication

interface can be used to:

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

.

Dynamically re-program the output voltage in 12.5mV

increments

.

Reprogram the mode of operation to enable or disable

PFM mode

.

Control voltage transition slew rate

Enable / disable the regulator.

For more details, refer to the I²C Interface and Register

Description sections.

Output Voltage Programming

V_OUTis programmed according to the following equations:

Option⁽¹²⁾

V_OUTEquation

V_OUT 0.75  N_VSEL12.5mV

00, 02, 03

(1)

(2)

V_OUT 1.1875  N_VSEL12.5mV

06

Note:

12. For option 00 and 02, the maximum voltage is 1.4375V.

FAN5365 • Rev. 1.0.6

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17

Software Enable

Power-Up, EN, and Soft-Start

The EN_DCDC bit, VSELx[7], can be used to enable the

regulator in conjunction with the EN pin. Setting EN_DCDC with

EN HIGH begins the soft-start sequence described above.

All internal circuits remain de-biased and the IC is in a very

low quiescent current state until the following are true:

.

V_INis above its rising UVLO threshold, and

Light-Load (PFM) Operation

.

EN is HIGH.

The FAN5365 provides a low ripple, single-pulse, PFM mode

that ensures:

At that point, the IC begins a soft-start cycle, its I²C interface is

enabled, and its registers are loaded with their default values.

. Smooth transitions between PFM and PWM modes

. Single-pulse operation for low ripple

. Predictable PFM entry and exit currents.

PFM begins after the inductor current has become

discontinuous, crossing zero during the PWM cycle for 32

consecutive cycles. PFM exit occurs when discontinuous

current mode (DCM) operation cannot supply sufficient

current to maintain regulation. During PFM mode, the

inductor current ripple is about 40% higher than in PWM

mode. The load current required to exit PFM mode is

thereby about 20% higher than the load current required to

enter PFM mode, providing sufficient hysteresis to prevent

“mode chatter.”

During the initial soft-start, V_OUTramps linearly to the

setpoint programmed in the VSEL register selected by the

VSEL pin. The soft-start features a fixed output voltage slew

rate of 20V/ms and achieves regulation approximately 90s

after EN rises. PFM mode is enabled during soft-start until

the output is in regulation, regardless of the MODE bit

settings. This allows the regulator to start into a partially

charged output without discharging it; in other words, the

regulator does not allow current to flow from the load back to

the battery.

As soon as the output has reached its setpoint, the control

forces PWM mode for about 85s to allow all internal control

circuits to calibrate.

While PWM ripple voltage is typically less than 4mV_P-P, PFM

ripple voltage can be up to 30mV_P-Pduring very light load. To

prevent significant undershoot when a load transient occurs,

the initial DC setpoint for the regulator in PFM mode is set

10mV higher than in PWM mode. This offset decays to about

5mV after the regulator has been in PFM mode for ~100s.

The maximum instantaneous voltage in PFM is 30mV above

the setpoint.

Table 3. Soft-Start Timing

Symbol

Description

Value (s)

Time from EN to start of soft-

start ramp

t_SSDLY

100

t_REG

t_POK

V_OUTramp start to regulation

(VSEL–0.1) X 53

PFM mode can be disabled by writing to the mode control

bits: CONTROL1[3:0] (see Table 5)

PWROK (CONTROL2[5])

rising from t_REG

11

10

Regulator stays in PWM

mode during this time

t_CAL

Output Voltage Transitions

The IC regulates V_OUTto one of two setpoint voltages, as

determined by the VSEL pin and the HW_nSW bit.

EN

t _REG

VSEL

Table 5. V_OUTSetpoint and Mode Control

MODE_CTRL, CONTROL1[3:2] = 00

t_SSD

LY

V_OUT

t_{CA L}(FPWM)

VSEL Pin HW_nSW Bit V_OUTSetpoint

PFM

0

t_POK

0

1

x

1

0

VSEL0

VSEL1

Allowed

PWROK

Per MODE1

Figure 35. Soft-Start Timing

Table 4. EN_DCDC Behavior

EN_DCDC Bit EN Pin

If HW_nSW = 0, V_OUTtransitions are initiated through the

following sequence:

I²C

OFF

ON

REGULATOR

0

1

0

1

0

1

OFF

ON

1. Write the new setpoint in VSEL1.

2. Write desired transition rate in DEFSLEW,

CONTROL2[2:0], and set the GO bit in CONTROL2[7].

OFF

ON

OFF

If HW_nSW = 1, V_OUTtransitions are initiated either by

changing the state of the VSEL pin or by writing to the VSEL

register selected by the VSEL pin.

FAN5365 • Rev. 1.0.6

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18

All positive V_OUTtransitions inhibit PFM until the transition is

Positive Transitions

When transitioning to a higher V_OUT, the regulator can

perform the transition using multi-step or single-step mode.

complete, which occurs at the end of t_POK(L-H)

.

Negative Transitions

When moving from V_SEL= 1 to V_SEL= 0, the regulator enters

PFM mode, regardless of the condition of the MODE bits,

and remains in PFM until the transition is complete. Reverse

current through the inductor is blocked, and the PFM

minimum frequency control inhibited, until the new setpoint is

reached; at which time, the regulator resumes control using

the mode established by MODE_CTRL. The transition time

from V_HIGHto V_LOWis controlled by load current and output

capacitance as:

Multi-Step Mode:

The internal DAC is stepped at a rate defined by DEFSLEW,

CONTROL2[2:0], ranging from 000 to 110. This mode

minimizes the current required to charge C_OUTand thereby

minimizes the current drain from the battery when

transitioning. The PWROK bit, CONTROL2[5], remains LOW

until about 1.5s after the DAC completes its ramp.

V

HIGH

V_HIGH V_LOW

t_V(HL) C_OUT



(3)

I_LOAD

V_OUT

V

HIGH

V

LOW

V_SEL

t_POK(L-H)

PWROK

V_OUT

V

LOW

Figure 36. Multi-Step V_OUTTransition

t_V(L-H)

V_SEL

PWROK

Single-Step Mode:

t_POK(L-H)

Used if DEFSLEW, CONTROL2[2:0] = 111. The internal

DAC is immediately set to the higher voltage and the

regulator performs the transition as quickly as its current limit

circuit allows, while avoiding excessive overshoot.

Figure 38. Negative V_OUTTransition

Figure 37 shows single-step transition timing. t_V(L-H)is the

time it takes the regulator to settle to within 2% of the new

setpoint, typically 7s for a full-range transition. The PWROK

bit, CONTROL2[5], goes LOW until the transition is complete

Protection Features

Current Limit / Auto-Restart

The regulator includes cycle-by-cycle current limiting, which

prevents the instantaneous inductor current from exceeding

the “PMOS Current Limit” threshold.

and V_OUTsettled. This typically occurs ~2s after t_V(L-H)

.

It is good practice to reduce the load current before making

positive V_SELtransitions. This reduces the time required to

make positive load transitions and avoids current–limit-

induced overshoot.

The IC enters “fault” mode after sustained over-current. If

current limit is asserted for more than 32 consecutive cycles

(about 20s), the IC returns to shutdown state and remains

in that condition for ~80s. After that time, the regulator

attempts to restart with a normal soft-start cycle. If the fault

has not cleared, it shuts down ~20s later.

t_V(L-H)

V

HIGH

98% V

HIGH

If the fault is a short circuit, the initial current limit is ~30% of

the normal current limit, which produces a very small drain

on the system power source.

V_OUT

V

Thermal Protection

LOW

When the junction temperature of the IC exceeds 150°C, the

device turns off all output MOSFETs and remains in a low

quiescent current state until the die cools to 130°C before

starting a normal soft-start cycle.

V_SEL

t_POK(L-H)

PWROK

Figure 37. Single-Step V_OUTTransition

FAN5365 • Rev. 1.0.6

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19

Data change allowed

Under-Voltage Lockout (UVLO)

The IC turns off all MOSFETs and remains in a low

quiescent current state until V_INrises above the UVLO

threshold.

SDA

SCL

t_H

I²C Interface

t_SU

The FAN5365’s serial interface is compatible with standard,

fast, fast plus, and high-speed mode I²C bus specifications.

The FAN5365’s SCL line is an input and its SDA line is a bi-

directional open-drain output; it can only pull down the bus

when active. The SDA line only pulls LOW during data reads

and when signaling ACK. All data is shifted in MSB (bit 7) first.

Figure 39. Data Transfer Timing

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a “START” condition, which

is defined as SDA transitioning from 1 to 0 with SCL HIGH,

as shown in Figure 40.

Slave Address

In Table 6, A1 and A0 are according to the Ordering

Information table on page 2.

t_HD;STA

Slave Address

MS Bit

SDA

SCL

Table 6. I²C Slave Address

7

6

5

4

3

2

1

0

1

0

1

A2

A1

A0

R/W

Figure 40. Start Bit

In Hex notation, the slave address assumes a 0 LSB. For

example, the hex slave address of option 00 is 94H.

A transaction ends with a “STOP” condition, which is defined

as SDA transitioning from 0 to 1 with SCL HIGH, shown in

Figure 41.

Register Addressing

FAN5365 has four user-accessible registers:

Slave Releases

Master Drives

t_HD;STO

Table 7. I²C Register Address

Address

ACK(0) or

NACK(1)

SDA

SCL

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

0

1

0

1

VSEL0

VSEL1

Figure 41. Stop Bit

CONTROL1

CONTROL2

During a read from the FAN5365 (Figure 44), the master

issues a “Repeated Start” command after sending the

register address and before resending the slave address.

The “Repeated Start” is a 1-to-0 transition on SDA while SCL

is HIGH, as shown in Figure 42.

Bus Timing

As shown in Figure 39, data is normally transferred when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

Slave Releases

t_SU;STA

t_HD;STA

ACK(0) or

NACK(1)

SLADDR

MS Bit

SDA

SCL

Figure 42. Repeated Start Timing

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20

High-Speed (HS) Mode

Read and Write Transactions

The protocols for High-Speed (HS), Low-Speed (LS), and

Fast-Speed (FS) modes are identical, except the bus speed

for HS mode is 3.4MHz. HS mode is entered when the bus

master sends the HS master code 00001XXX after a start

condition. The master code is sent in Fast or Fast Plus mode

(less than 1MHz clock) and slaves do not acknowledge

(ACK) this transmission.

The following figures outline the sequences for data read

and write. Bus control is signified by the shading of the

Master Drives Bus

Slave Drives Bus

packet, defined as

All addresses and data are MSB first.

and

.

Table 8. I²C Bit Definitions for Figure 43 and Figure 44

Symbol

Definition

The master then generates a repeated start condition

(Figure 42) that causes all slaves on the bus to switch to HS

mode. The master then sends I²C packets, as described

above, using the HS mode clock rate and timing.

S

START, Figure 40.

ACK. The slave drives SDA to 0 to acknowledge

the preceding packet.

A

NACK. The slave sends a 1 to NACK the

preceding packet.

The bus remains in HS mode until a stop bit (Figure 41) is

sent by the master. While in HS mode, packets are

separated by repeated start conditions.

R

P

Repeated START, see Figure 42.

STOP, see Figure 41.

0

7 bits

8 bits

Data

S

Slave Address

0

A

Reg Addr

A

P

Figure 43. Write Transaction

0

1

7 bits

Slave Address

8 bits

7 bits

8 bits

Data

S

0

A

Reg Addr

A

R

Slave Address

1

A

P

Figure 44. Read Transaction

Register Descriptions

Default Values

both the default values and the bit’s type (as defined in Table

10) for each available option.

Each option of the FAN5365 (see Table 9) has different

default values for the some of the register bits. Table 9 defines

Table 9. Default Values and Bit Types for V_SELand CONTROL Registers

VSEL0

VSEL1

Option

00

7

1

6

1

5

0

1

4

1

3

1

0

2

0

1

0

1

0

1

V_OUT

1.05

0.95

1.00

1.80

Option

00

7

1

6

1

5

1

0

1

4

0

1

0

1

3

0

1

0

2

1

0

1

0

1

V_OUT

1.20

1.10

1.20

1.80

02

03

06

CONTROL1

CONTROL2

Option

00, 02

03, 06

7

1

6

0

5

0

4

1

3

0

2

0

1

0

Option

00, 02

03, 06

7

0

6

1

0

5

0

4

0

3

0

2

1

0

1

Table 10. Bit Type Definitions for Table 9

#

Active Bit Changing this bit changes the behavior of the converter, as described below.

Disabled Converter logic ignores changes made to this bit. Bit can be written and read-back.

Read-Only Writing to this bit through I²C does not change the read-back value, nor does it change converter behavior.

FAN5365 • Rev. 1.0.6

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21

Bit Definitions

Table 11 defines the operation of each register bit.

Superscript characters define the default state for each

option. Superscripts

A

options 00, 02, 03, and 06, respectively.

default for all options.

signifies the

0,2,3,6

signify the default values for

Table 11. Bit Definitions

Bit

Name

Value

Description

VSEL0

Register Address: 00

Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write

to bit 7 in either register establishes the EN_DCDC value.

0

7

EN_DCDC

1^A

Device enabled when EN pin is HIGH, disabled when EN is LOW.

6

Reserved

DAC[5:0]

5:0

Table 9^A6-bit DAC value to set V_OUT

.

VSEL1

Register Address: 01

Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write

to bit 7 in either register establishes the EN_DCDC value.

0

7

EN_DCDC

1^A

Device enabled when EN pin is HIGH, disabled when EN is LOW.

6

Reserved

DAC[5:0]

5:0

Table 9^A6-bit DAC value to set V_OUT

.

CONTROL1

Register Address: 02

Vendor ID bits. Writing to these bits has no effect on regulator operation. These bits can be

used to distinguish between vendors via I²C.

7:6

5

Reserved

10^A

1^A

0

Reserved

V

_OUTis controlled by VSEL1. Voltage transitions occur by writing to the VSEL1, then setting

the GO bit.

4

HW_nSW

V_OUTis programmed by the VSEL pin. V_OUT= VSEL1 when VSEL is HIGH and V_OUT= VSEL0

when VSEL is LOW.

1^A

00^A

01

10

11

0^A

1

Operation follows MODE0, MODE1.

PFM with automatic transitions to PWM, regardless of VSEL.

PFM disabled (forced PWM), regardless of VSEL.

3:2 MODE_CTRL

PFM with automatic transitions to PWM, regardless of VSEL.

PFM disabled (forced PWM) when regulator output is controlled by VSEL1.

PFM with automatic transitions to PWM when regulator output is controlled by VSEL1.

1

0

MODE1

MODE0

0^A

1

PFM with automatic transitions to PWM when VSEL is LOW. Changing this bit has no effect on

the operation of the regulator.

CONTROL2

Register Address: 03

0^A

1

0 ^3,6

1 ^0,2

0

This bit has no effect when HW_nSW = 1. At the end of a V_OUTtransition, this bit is reset to 0.

Starts a V_OUTtransition if HW_nSW = 0.

7

6

GO

When the regulator is disabled, V_OUTis not discharged.

When the regulator is disabled, V_OUTdischarges through an internal pull-down.

V_OUTis not in regulation or is in current limit.

OUTPUT_

DISCHARGE

PWROK

(read only)

5

1

V_OUTis in regulation.

4:3

Reserved

00^A

000

001

010

011

100

101

110

111^A

V_OUTslews at 0.15mV/s during positive V_OUTtransitions.

V_OUTslews at 0.30mV/s during positive V_OUTtransitions.

V_OUTslews at 0.60mV/s during positive V_OUTtransitions.

V_OUTslews at 1.20mV/s during positive V_OUTtransitions.

V_OUTslews at 2.40mV/s during positive V_OUTtransitions.

V_OUTslews at 4.80mV/s during positive V_OUTtransitions.

V_OUTslews at 9.60mV/s during positive V_OUTtransitions.

Positive V_OUTtransitions use single-step mode (see Figure 37).

2:0 DEFSLEW

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

22

Layout Recommendations

FAN5365 switches at a relatively high frequency of 6MHz;

thus the recommended layout should be followed carefully as

additional parasitic effects caused by moving components

further away or routing through internal layers can cause

issues. In addition, possible detrimental effects to regulator

performance EMI issues can be generated by introducing

unintentional coupling paths in the layout.

next to the IC with routing on the top layer, as shown in Figure

45 and Figure 46.

Switching current paths through C_INand C_OUTshould be

returned directly to the GND bumps of the IC on the top layer

of the printed circuit board (PCB).

The SW node should be treated as a noisy signal and

separated by the ground plane or “keepout region” from any

sensitive signals in the system. Routing sensitive high-

impedance voltage reference signals should be avoided on

the layer directly beneath the SW node.

To minimize VIN and SW spikes and thereby reduce voltage

stress on the IC power switches; it is critical to minimize the

loop length for the VIN bypass capacitor. C_INmust be placed

Figure 45. Simplified Layout Drawing

Figure 46. Fairchild Reference Board Layout

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

23

Physical Dimensions

F

0.03 C

A

E

2X

0.40

A1

B

D

Ø0.20

Cu Pad

0.40

PIN A1

INDEX AREA

Ø0.30

Solder Mask

0.03 C

2X

LAND PATTERN RECOMMENDATION

(NSMD PAD TYPE)

TOP VIEW

0.06 C

0.378±0.018

0.208±0.021

0.625

0.547

0.05 C

E

C

SEATING PLANE

D

SIDE VIEWS

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

Ø0.260±0.020

9X

0.40

C. DIMENSIONS AND TOLERANCE

PER ASMEY14.5M, 1994.

C

B

A

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

(Y)±0.018

0.40

E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS

±39 MICRONS (547-625 MICRONS).

F

1

2 3

(X)±0.018

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

BOTTOM VIEW

G. DRAWING FILNAME: MKT-UC009ABrev2

Figure 47. 9-Ball WLCSP, 3X3 Array, 0.4mm Pitch, 250µm Ball

Product-Specific Dimensions

Product

D

E

X

Y

FAN5365UC

1.290 +/-0.030

1.270 +/-0.030

0.250

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without

notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most

recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty

therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

24

FAN5365 • Rev. 1.0.6

www.fairchildsemi.com

25

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1


型号：	FAN5365UC00X
厂家：	ONSEMI
描述：	1A/0.8A 6MHz数字化可编程稳压器开关稳压器
文件：	总28页 (文件大小：1476K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN5365UC00X [ONSEMI]

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