FAN54005UCX_技术文档

USB-Compliant Single-Cell

Li-Ion Switching Charger

with USB-OTG Boost for

200 mA to 1.45 A Systems

FAN54005

Description

The FAN54005 is a highly integrated switch−mode

charger, configurable for 200 mA to 1.45 A systems using

a single external resistor.

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The charging parameters and operating modes are program−

2

mable through an I C Interface that operates up to 3.4 Mbps.

1

The charger and boost regulator circuits switch at 3 MHz

to minimize the size of external passive components.

The FAN54005 provides battery charging in three phases:

conditioning, constant current and constant voltage.

To ensure USB compliance and minimize charging time, the

WLCSP

20 BALL

CASE 567SL

2

input current limit can be changed through the I C interface

• Charge Parameters Programmable through High−Speed

by the host processor. Charge termination is determined by

a programmable minimum current level. A safety timer with

2

I C Interface (3.4 Mb/s) with Fast Mode Plus

Compatibility

♦ Input Current

2

reset control provides a safety backup for the I C host.

2

Charge status is reported to the host through the I C port.

♦ Fast−Charge / Termination Current

♦ Charger Voltage

The integrated circuit (IC) automatically restarts the charge

cycle when the battery falls below an internal threshold. If

the input source is removed, the IC enters a high−impedance

mode, preventing leakage from the battery to the input.

Charge current is reduced when the die temperature reaches

120°C, protecting the device and PCB from damage.

The FAN54005 can operate as a boost regulator on

command from the system. The boost regulator includes a

soft−start that limits inrush current from the battery and uses

the same external components used for charging the battery.

♦ Termination Enable

• 3 MHz Synchronous Buck PWM Controller with Wide

Duty Cycle Range

• Small Footprint 1 mH External Inductor

• Safety Timer with Reset Control

• 1.8 V Regulated Output from VBUS for Auxiliary Circuits

• Dynamic Input Voltage Control Automatically Reduces

Charging Current with Weak Input Sources

• Low Reverse Leakage to Prevent Battery Drain to VBUS

• 5 V, 500 mA Boost Mode for USB OTG for 3.0 V to

4.5 V Battery Input

Features

• Fully Integrated, High−Efficiency Charger for

Single−Cell Li−Ion and Li−Polymer Battery Packs

• Charge Voltage Accuracy: 0.5% at 25°C

Charge Voltage Accuracy: 1% from 0 to 125°C

• Available in a 1.96 x 1.87 mm, 20−bump, 0.4 mm Pitch

WLCSP Package

• Supports 200 mA to 1.45 A Systems

95% Efficiency for 200 mA−Hour Batteries

94% Efficiency for 500 mA−Hour Batteries

90% Efficiency for 1.0 A−Hour Batteries

Applications

• Wireless Speakers, Headphones

• Cell Phones, Gaming Devices

• Toys, Drones, Digital Cameras

• IoT Devices

•

5% Input Current Regulation Accuracy

5% Charge Current Regulation Accuracy

• 20 V Absolute Maximum Input Voltage

• 6 V Maximum Input Operating Voltage

• E−Cigs, Vapes

ORDERING INFORMATION

†

Part Number

Temperature Range

Package

PN Bits: IC_INFO[4:2]

Packing

FAN54005UCX

−40°C to +85°C

20−Bump, Wafer−Level Chip−Scale Package

(WLCSP), 0.4 mm Pitch, 1.96 x 1.87 mm

101

Tape and Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

1

Publication Order Number:

November, 2019 − Rev. 4

FAN54005/D

FAN54005

L1

SW

VBUS

C_BUS

1mH

C_OUT

1mF

0.1mF

PMID

C_MID

CSIN

4.7mF

SDA

R_SNS

FAN54005

SCL

VBAT

Battery

DISABLE

OTG/USB#

STAT

+

C_BAT

VREG

C_REG

SYSTEM

LOAD

10 mF

1mF

Figure 1. Typical Application

Block Diagram

PMID

Q1A

ON

Q1B

OFF

ON

VREG

1.8V / PMID REG

> V

BAT

C_REG

1mF

PMID

< V

OFF

Q1

Q3

C_MID

Q1A

Q1B

4.7mF

VBUS

CHARGE

PUMP

C_BUS

1mF

L1

1mH

SW

Q2

PWM

MODULATOR

I_IN

CONTROL

VBUS

OVP

PGND

CSIN

C_OUT

0.1mF

R_SNS

DAC

VREF

+

C_{SYS_DISTRIBUTED}

47mF

C_BAT

10 mF

SDA

SCL

PMID

Battery

I2C

INTERFACE

STAT

30 mA

SYSTEM

LOAD

OSC

DISABLE

OTG

LOGIC

AND

CONTROL

Figure 2. IC and System Block Diagram

Table 1. RECOMMENDED EXTERNAL COMPONENTS

Component

Description

Vendor

Parameter

Typ

1.0

Unit

mH

L1

1 mH 20%, 4.0 A, 33 mW, 2016

10 mF, 20%, 6.3 V, X5R, 0603

Semco CIGT201610EH1R0M

L

C

Murata: GRM188R60J106M

TDK: C1608X5R0J106M

C

10

4.7

1.0

0.1

47

mF

BAT

C

4.7 mF, 10%, 10 V, X5R, 0603

1.0 mF, 10%, 25 V, X5R, 0603

1.0 mF, 10%, 10 V, X5R, 0402

0.1 mF, 10%, 16 V, X7R, 0402

n/a

Murata: GRM188R61A475K

TDK: C1608X5R1A475K

C (Note 1)

mF

MID

C

Murata: GRM188R61E105K

TDK: C1608X5R1E105M

C

BUS

REG

OUT

C

Murata: GRM155R61A105K

TDK: C1005X5R1A105K

Murata: GRM155R71C104K

TDK: C1005X7R1C104K

C

(Note 2)

n/a

SYS_DISTRIBUTED

1. A 10 V rating is sufficient for CMID because PMID is protected from over−voltage surges on VBUS by Q3 (Figure 2).

2. A minimum 47 mF of distributed capacitance on SYS is required for proper operation of the FAN54005.

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2

FAN54005

Pin Configuration

A1

B1

C1

D1

E1

A2

B2

C2

D2

E2

A3

B3

C3

D3

E3

A4

B4

C4

D4

E4

A3

B3

C3

D3

E3

A2

B2

C2

D2

E2

A1

B1

C1

D1

E1

B4

C4

D4

E4

Top View

Bottom View

Figure 3. WLCSP−20 Pin Assignments

Table 2. PIN DEFINITIONS

Pin #

A1, A2

A3

Name

VBUS

NC

Description

Charger Input Voltage and USB−OTG output voltage. Bypass with a 1 mF capacitor to PGND.

No Connect. No external connection is made between this pin and the IC’s internal circuitry.

2

A4

SCL

I C Interface Serial Clock. This pin should not be left floating.

B1−B3

PMID

Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense, and

high−voltage input switch. Bypass with a minimum of 4.7 mF, 6.3 V capacitor to PGND.

2

B4

SDA

I C Interface Serial Data. This pin should not be left floating.

C1−C3

C4

SW

Switching Node. Connect to output inductor.

STAT

PGND

Status. Open−drain output indicating charge status. The IC pulls this pin LOW when charging.

D1−D3

Power Ground. Power return for gate drive and power transistors. The connection from this pin to the bottom

of C

should be as short as possible.

MID

D4

E1

E2

E3

E4

OTG

CSIN

On−The−Go. On VBUS Power−On Reset (POR), this pin sets the input current limit for t

charging. Also,

15MIN

the OTG pin enables the boost regulator in conjunction with OTG_EN and OTG_PL bits (See Table 21)

Current−Sense Input. Connect to the sense resistor in series with the battery. The IC uses this node to

sense current into the battery. Bypass this pin close to R

with a 0.1 mF capacitor to PGND.

SNS

2

DISABLE

VREG

VBAT

Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is controlled by the I C regis-

ters. When this pin is HIGH, the 15−minute timer is reset. This pin does not affect the 32−second timer.

Regulator Output. Connect to a 1 mF capacitor to PGND. This pin provides regulated 1.8 V and can supply

up to 2 mA of DC load current.

Battery Voltage. Connect to the positive (+) terminal of the battery pack and close to R

.

SNS

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3

FAN54005

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Continuous

Pulsed, 100 ms Maximum Non−Repetitive

Min

−0.7

−1.0

−0.3

Max

Unit

V

BUS

VBUS Voltage

20.0

V

STAT Voltage

PMID Voltage

16.0

V

STAT

V

I

7.0

SW, CSIN, VBAT, DISABLE Voltage

Voltage on Other Pins

−0.3 (Note 3)

−0.3

7.0

V

O

6.5 (Note 4)

V

dV

/ dt Maximum V

Slope above 5.5 V when Boost or Charger are Active

4

2

V/ms

BUS

−dV

/ dt Negative VBUS Slew Rate during VBUS Short Circuit,

T

≤ 60°C

≥ 60°C

BUS

A

C

≤ 4.7 mF (See VBUS Short While Charging)

MID

T

A

Human Body Model

2000

1000

ESD

Electrostatic Discharge Protection Level

V

per JESD22−A114

Charged Device Model

per JESD22−C101

T

Junction Temperature

−40

−65

+150

+260

°C

J

T

Storage Temperature

STG

T

L

Lead Soldering Temperature, 10 Seconds

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

3. SW only: Switching transients of −0.7 V, minimum, with duration <20 nsec, are acceptable.

4. Lesser of 6.5 V or V + 0.3 V

I

Table 4. RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

6

Unit

V

Supply Voltage

4

BUS

BAT(MAX)

V

Maximum Battery Voltage when Boost enabled

Ambient Temperature

4.5

V

T

A

−30

+85

+120

°C

T

J

Junction Temperature (See Thermal Regulation and Protection section)

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 5. THERMAL PROPERTIES

Symbol

Parameter

Typical

60

Unit

°C/W

q

Junction−to−Ambient Thermal Resistance

Junction−to−PCB Thermal Resistance

JA

JB

20

NOTE: Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p

boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature T at a

J(max)

given ambient temperature T . For measured data, see Thermal Regulation and Protection.

A

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4

FAN54005

Table 6. ELECTRICAL SPECIFICATIONS

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T and T ;

J

A

V

BUS

= 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for T = 25°C.

J

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

POWER SUPPLIES

I

VBUS Current

V

> V

, PWM Switching

; PWM Enabled,

10

mA

VBUS

BUS

IN(MIN)1

2.5

BUS

IN(MIN)1

Not Switching (Battery OVP Condition);

I_IN Setting = 100 mA

0°C < T < 85°C, HZ_MODE = 1, 32S Mode

63

90

mA

J

I

VBAT to VBUS Leakage Current

0°C < T < 85°C, HZ_MODE = 1,

0.2

5.0

LKG

J

V

BAT

= 4.2 V, V

= 0 V

BUS

I

Battery Discharge Current in High−

Impedance Mode

0°C < T < 85°C, HZ_MODE = 1,

BAT

10

mA

BAT

J

V

= 4.2 V

DISABLE = 1, 0°C < T < 85°C,

J

V

BAT

= 4.2 V

CHARGER VOLTAGE REGULATION

V

OREG

Charge Voltage Range

3.5

−0.5%

−1%

4.4

V

Charge Voltage Accuracy

T = 25°C

+0.5%

+1%

A

T = 0 to 125°C

J

CHARGING CURRENT REGULATION

I

Output Charge Current Range

V

< V

SNS

< V

,

200

1450

mA

OCHARGE

SHORT

BAT

OREG

68 < R

< 180 mW

Charge Current Accuracy Across

SNS

20 mV ≤ [V

– V

] ≤ 40 mV

92

94

97

102

100

%

CSIN

BAT

R

[V

CSIN

– V

] > 40 mV

BAT

WEAK BATTERY DETECTION

V

LOWV

Weak Battery Threshold Range

Weak Battery Threshold Accuracy

Weak Battery Deglitch Time

3.4

3.7

+5

V

%

−5

Rising Voltage

30

ms

LOGIC LEVELS: DISABLE, SDA, SCL, OTG

V

High−Level Input Voltage

Low−Level Input Voltage

Input Bias Current

1.05

V

IH

V

0.4

IL

I

IN

Input Tied to GND or V

0.01

1.00

mA

BUS

CHARGE TERMINATION DETECTION

I

Termination Current Range

V

> V

– V ,

RCH

20

400

mA

%

TERM

BAT

OREG

68 < R

< 180 mW

SNS

– V

Termination Current Accuracy

[V

] from 3 mV to 20 mV

] from 20 mV to 40 mV

−25

−5

+25

+5

CSIN

BAT

Termination Current Deglitch Time

30

ms

V

1.8 V LINEAR REGULATOR

1.8 V Regulator Output

INPUT POWER SOURCE DETECTION

V

REG

I

from 0 to 2 mA

1.7

1.8

1.9

REG

V

VBUS Input Voltage Rising

Minimum VBUS During Charge

VBUS Validation Time

To Initiate and Pass VBUS Validation

During Charging

4.29

3.71

30

4.42

3.94

V

IN(MIN)1

IN(MIN)2

V

t

ms

VBUS_VALID

DYNAMIC INPUT VOLTAGE CONTROL (V

)

BUS

V

SP

DIVC Accuracy

−3

+3

%

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5

FAN54005

Table 6. ELECTRICAL SPECIFICATIONS

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T and T ;

J

A

V

BUS

= 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for T = 25°C.

J

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

INPUT CURRENT LIMIT

I

Input Current Limit Threshold

I

Set to 100 mA

88

93

98

mA

INLIM

Set to 500 mA

450

475

500

INLIM

BATTERY RECHARGE THRESHOLD

V

RCH

Recharge Threshold

Deglitch Time

Below V

100

120

130

150

mV

ms

OREG

V

BAT

Falling Below V

Threshold

RCH

STAT OUTPUT

V

STAT Output Low

I

= 10 mA

0.4

1

V

STAT(OL)

STAT(OH)

STAT

I

STAT High Leakage Current

V

= 5 V

mA

STAT

BATTERY DETECTION

I

Battery Detection Current before

Begins after Termination Detected and

V ≤ V –V

BAT

−0.80

mA

ms

DETECT

Charge Done (Sink Current) (Note 5)

OREG

RCH

t

Battery Detection Time

262

DETECT

SLEEP COMPARATOR

Sleep−Mode Entry Threshold,

V

SLP

2.3 V ≤ V

≤ V , V Falling

OREG BUS

0

0.04

30

0.10

V

BAT

V

– V

BUS

BAT

t

Deglitch Time for VBUS Rising

Above V by V

Rising Voltage

ms

SLP_EXIT

BAT

SLP

POWER SWITCHES (See Figure 2)

R

Q3 On Resistance (VBUS to PMID)

Q1 On Resistance (PMID to SW)

Q2 On Resistance (SW to GND)

I

= 500 mA

180

130

150

250

225

mW

DS(ON)

INLIM

CHARGER PWM MODULATOR

f

Oscillator Frequency

Maximum Duty Cycle

Minimum Duty Cycle

2.7

3.0

3.3

MHz

%

SW

D

100

MAX

D

0

%

MIN

I

Synchronous to Non−Synchronous

Current Cut−Off Threshold (Note 6)

Low−Side MOSFET (Q2) Cycle−by−Cycle

Current Limit

140

mA

SYNC

BOOST MODE OPERATION (OPA_MODE = 1, HZ_MODE = 0)

V

Boost Output Voltage at VBUS

2.5 V < V

< 4.5 V, I

from 0 to 200 mA

from 0 to 500 mA

4.80

4.77

5.07

140

5.17

300

V

BOOST

BAT

LOAD

3.0 V < V

LOAD

I

Boost Mode Quiescent Current

Q2 Peak Current Limit

PFM Mode, V

= 3.6 V, I = 0

OUT

mA

V

BAT(BOOST)

BAT

I

1440

1700

2.30

2.50

1960

LIMPK(BST)

UVLO

Minimum Battery Voltage for Boost

Operation

While Boost Active

BST

To Start Boost Regulator

2.70

VBUS LOAD RESISTANCE

VBUS to PGND Resistance

R

Normal Operation

Charger Validation

1500

100

kW

VBUS

W

PROTECTION AND TIMERS

VBUS

VBUS Over−Voltage Shutdown

V

Rising

Falling

6.09

6.29

100

6.49

V

OVP

BUS

Hysteresis

mV

BUS

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6

FAN54005

Table 6. ELECTRICAL SPECIFICATIONS

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T and T ;

J

A

V

BUS

= 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for T = 25°C.

J

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

PROTECTION AND TIMERS

I

Q1 Cycle−by−Cycle Peak Current

Limit

Charge Mode

2.3

A

LIMPK(CHG)

V

Battery Short−Circuit Threshold

Hysteresis

V

Rising

Falling

1.95

20

2.00

100

30

2.05

40

V

SHORT

BAT

mV

mA

°C

I

Linear Charging Current

< V

SHORT

T

Thermal Shutdown Threshold

(Note 7)

T Rising

J

145

SHUTDWN

Hysteresis (Note 7)

T Falling

J

10

T

CF

Thermal Regulation Threshold

(Note 7)

Charge Current Reduction Begins

120

°C

t

Detection Interval

2.1

s

INT

t

32−Second Timer (Note 8)

Charger Enabled

Charger Disabled

15−Minute Mode

Charger Inactive

20.5

18.0

12.0

−25

25.2

13.5

28.0

34.0

15.0

25

32S

t

15−Minute Timer

min

%

15MIN

Dt

Low−Frequency Timer Accuracy

LF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Negative current is current flowing from the battery to GND (discharging the battery).

6. Q2 always turns on for 60 ns, then turns off if current is below I

7. Guaranteed by design; not tested in production.

.

SYNC

8. This tolerance (%) applies to all timers on the IC, including soft−start and deglitching timers.

Table 7. I²C TIMING SPECIFICATIONS Guaranteed by design, V

≥ 2.5 V if valid VBUS not present.

BAT

Symbol

Parameter

Conditions

Min

Typ

Max

100

Unit

f

SCL Clock Frequency

Standard Mode

Fast Mode

kHz

SCL

400

High−Speed Mode, C ≤ 100 pF

3400

1700

B

High−Speed Mode, C ≤ 400 pF

B

t

Bus−Free Time between STOP and Standard Mode

4.7

1.3

4

ms

BUF

START Conditions

Fast Mode

t

START or Repeated START Hold

Time

Standard Mode

Fast Mode

ms

ns

ms

ns

ms

ns

ms

ns

HD;STA

600

160

4.7

1.3

160

320

4

High−Speed Mode

Standard Mode

Fast Mode

t

SCL LOW Period

LOW

High−Speed Mode, C ≤ 100 pF

B

High−Speed Mode, C ≤ 400 pF

B

t

SCL HIGH Period

Standard Mode

Fast Mode

HIGH

600

60

High−Speed Mode, C ≤ 100 pF

B

High−Speed Mode, C ≤ 400 pF

120

4.7

600

160

B

t

Repeated START Setup Time

Standard Mode

Fast Mode

SU;STA

High−Speed Mode

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7

FAN54005

Table 7. I²C TIMING SPECIFICATIONS Guaranteed by design, V

≥ 2.5 V if valid VBUS not present.

BAT

Symbol

Parameter

Data Setup Time

Conditions

Min

Typ

250

100

10

Max

Unit

t

Standard Mode

Fast Mode

ns

SU;DAT

High−Speed Mode

Standard Mode

Fast Mode

t

Data Hold Time

SCL Rise Time

SCL Fall Time

0

3.45

900

70

ms

ns

HD;DAT

High−Speed Mode, C ≤ 100 pF

B

High−Speed Mode, C ≤ 400 pF

150

1000

300

80

B

t

Standard Mode

Fast Mode

20+0.1C

RCL

B

20+0.1C

B

High−Speed Mode, C ≤ 100 pF

10

B

High−Speed Mode, C ≤ 400 pF

20

160

300

40

B

t

Standard Mode

Fast Mode

20+0.1C

ns

FCL

B

High−Speed Mode, C ≤ 100 pF

10

B

High−Speed Mode, C ≤ 400 pF

20

80

B

t

SDA Rise Time

Rise Time of SCL after a Repeated

START Condition and after ACK Bit

Standard Mode

Fast Mode

20+0.1C

1000

300

80

RDA

B

t

RCL1

B

High−Speed Mode, C ≤ 100 pF

10

B

High−Speed Mode, C ≤ 400 pF

20

160

300

80

B

t

SDA Fall Time

Standard Mode

Fast Mode

20+0.1C

FDA

B

High−Speed Mode, C ≤ 100 pF

10

B

High−Speed Mode, C ≤ 400 pF

20

4

160

B

t

Stop Condition Setup Time

Standard Mode

Fast Mode

ms

ns

pF

SU;STO

600

160

High−Speed Mode

C

Capacitive Load for SDA, SCL

400

B

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8

FAN54005

Timing Diagrams

t_F

t_SU;STA

t_BUF

SDA

SCL

t_R

T_SU;DAT

t_HD;STO

t_HIGH

t_HD;DAT

t_LOW

t_HD;STA

REPEATED

START

STOP

START

Figure 4. I²C Interface Timing for Fast and Slow Modes

REPEATED

START

STOP

t_FDA

t_RDA

t_SU;DAT

SDAH

t_SU;STA

t_RCL1

t_FCL

t_HIGH

t_HD;DAT

note A

t_RCL

t_SU;STO

SCLH

t_LOW

t_HD;STA

REPEATED

START

= MCS Current Source Pull−up

= R_PResistor Pull−up

Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.

Figure 5. I²C Interface Timing for High−Speed Mode

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FAN54005

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, R

= 68 mW, V

= 4.2 V, V

= 5.0 V, and T = 25°C.

BUS A

SNS

OREG

180

160

140

120

100

80

900

800

700

600

500

400

300

5.5 VBUS

5.0 VBUS

4.7 VBUS

5.0 VBUS

4.7 VBUS

60

2.5

3.0

3.5

4.0

4.5

2.5

3.0

3.5

Battery Voltage, VBAT (V)

4.0

4.5

Battery Voltage, VBAT (V)

Figure 6. Battery Charge Current vs. V_BUSwith

_INLIM=100 mA, V_OREG=4.35V

Figure 7. Battery Charge Current vs. V_BUSwith

_INLIM=500 mA, V_OREG=4.35V

I

97%

94%

91%

88%

85%

82%

94%

4.3 VBAT, 5.0 VBUS

3.8 VBAT, 5.0 VBUS

4.3 VBAT, 5.5 VBUS

3.8 VBAT, 5.5 VBUS

92%

90%

88%

86%

84%

4.7 VBUS

5.0 VBUS

5.5 VBUS

100

300

500

700

900

1100

1300

1500

2.5

3.0

3.5

4.0

4.5

Battery Charge Current (mA)

Battery Voltage, VBAT (V)

Figure 8. Charger Efficiency, No

_INLIM,I_OCHARGE=1450 mA

Figure 9. Charger Efficiency vs. V_BUS

_INLIM=500 mA, V_OREG=4.35

,

I

Figure 10. Auto−Charge Startup at VBUS Plug−in,

Figure 11. Auto−Charge Startup at VBUS Plug−in,

OTG=0, V_BAT=3.4 V

OTG=1, V_BAT=3.4 V

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10

FAN54005

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, R

= 68 mW, V

= 4.2 V, V

= 5.0 V, and T = 25°C.

BUS A

SNS

OREG

Figure 12. Auto−Charge Startup with 300 mA

Limited Charger / Adaptor, OTG=1, V_BAT=3.4 V

Figure 13. Charger Startup with HZ_MODE Bit

Reset, I_INLIM=500 mA, I_OCHARGE=1050 mA,

V

_OREG=4.2 V, V_BAT=3.6 V

Figure 14. Battery Removal / Insertion During

Charging, V_BAT=3.9 V, I_OCHARGE=1050 mA, No

Figure 15. Battery Removal / Insertion During

Charging, V_BAT=3.9 V, I_OCHARGE=1050 mA, No

I_INLIM, TE=0

I_INLIM, TE=1

250

200

150

100

50

1.82

1.81

1.80

1.79

1.78

1.77

−30C

+25C

+85C

−30C, 5.0 VBUS

+25C, 5.0 VBUS

+85C, 5.0 VBUS

0

1

2

3

4

5

4.0

4.5

5.0

5.5

6.0

1.8V Regulator Load Current (mA)

Input Voltage, VBUS (V)

Figure 16. VBUS Current in High−Impedance Mode

Figure 17. V_REG1.8 V Output Regulation

with Battery Open

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11

FAN54005

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, R

= 68 mW, V

= 4.2 V, V

= 5.0 V, and T = 25°C.

BUS A

SNS

OREG

10

8

6

4

2

−30C

+25C

+85C

0

2.5

3.0

3.5

Battery Voltage, VBAT (V)

4.0

4.5

Figure 18. No Battery, TE=0, V_BUSPower Up

Figure 19. Sleep Mode Battery Discharge Current,

SDA=SCL=0 V, VBUS Open

10

8

VBUS open,

SDA=SCL=0V

VBUS open,

SDA=SCL=1.8V

VBUS=5.0V,

SDA=SCL=0V,

DIS or HZ=1

6

4

2

0

2.5

3.0

3.5

4.0

4.5

Battery Voltage, VBAT (V)

Figure 20. Battery Discharge Current vs. Mode

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12

FAN54005

Boost Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, R

= 68 mW, V = 3.6 V, and T = 25°C.

BAT A

SNS

100

95

90

85

80

75

100

95

90

85

80

75

−30C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

3.0 VBAT

3.6 VBAT

4.2 VBAT

0

100

200

300

400

500

0

100

200

300

400

500

VBUSLoad Current (mA)

Figure 21. Efficiency vs. V_BAT

Figure 22. Efficiency Over−Temperature

5.15

5.10

5.05

5.00

4.95

4.90

4.85

3.0 VBAT

−30C, 3.6VBAT

3.6 VBAT

4.2 VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

5.10

5.05

5.00

4.95

4.90

4.85

0

100

200

300

400

500

0

100

200

300

400

500

VBUSLoad Current (mA)

Figure 23. Output Regulation vs. V_BAT

Figure 24. Output Regulation Over−Temperature

300

250

200

150

100

50

−30C

+25C

+85C

2.5

3.0

3.5

4.0

4.5

Battery Voltage, VBAT (V)

Figure 25. Quiescent Current

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13

FAN54005

Boost Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, R

= 68 mW, V = 3.6 V, and T = 25°C.

BAT A

SNS

Figure 26. Boost PWM Waveform

Figure 27. Boost PFM Waveform

50

40

30

20

10

0

−30C, 3.6VBAT

3.0 VBAT

3.6 VBAT

4.2 VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

40

30

20

10

0

100

200

300

400

500

0

100

200

300

400

500

VBUSLoad Current (mA)

Figure 28. Output Ripple vs. V_BAT

Figure 29. Output Ripple vs. Temperature

Figure 30. Startup, 3.6 V_BAT, 44 W Load, Additional

10 mF, X5R Across V_BUS

Figure 31. V_BUSFault Response, 3.6 V_BAT

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14

FAN54005

Boost Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, R

= 68 mW, V = 3.6 V, and T = 25°C.

BAT A

SNS

Figure 32. Load Transient, 5−155−5 mA, t_R=t_F=100 ns

Figure 33. Load Transient, 5−255−5 mA, t_R=t_F=100 ns

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15

FAN54005

Circuit Description / Overview

Battery Charging Curve

If the battery voltage is below V

source pre−charges the battery until V

When charging batteries with a current−limited input source,

such as USB, a switching charger’s high efficiency over a

wide range of output voltages minimizes charging time.

, a linear current

SHORT

reaches V

.

BAT

SHORT

The PWM charging circuit is then started and the battery is

charged with a constant current if sufficient input power is

available. The current slew rate is limited to prevent

overshoot.

The FAN54005 combines

synchronous buck regulator for charging with

a

highly integrated

a

synchronous boost regulator, which can supply 5 V to USB

On−The−Go (OTG) peripherals. The FAN54005 employs

synchronous rectification for both the charger and boost

regulators to maintain high efficiency over a wide range of

battery voltages and charge states.

During the current regulation phase of charging, I

or

INLIM

the programmed charging current limits the amount of

current available to charge the battery and power the system.

The effect of I

on I

can be seen in Figure 35.

INLIM

OCHARGE

The FAN54005 has three operating modes:

1. Charge Mode: Charges a single−cell Li−ion or

Li−polymer battery.

V_OREG

I_CHARGE

2. Boost Mode: Provides 5 V power to USB−OTG

with an integrated synchronous rectification boost

regulator using the battery as input.

3. High−Impedance Mode: Both the boost and

charging circuits are OFF in this mode. Current

flow from VBUS to the battery or from the battery

to VBUS is blocked in this mode. This mode

consumes very little current from VBUS or the

battery.

I_TERM

V_SHVORT

SHORT

I

SHORI_ST_HORT

PRE−

CHARGE

CONSTANT CURRENT

(CC)

CONSTANT

VOLTAGE (CV)

Charge Mode and Registers

Note: Default settings are denoted by bold typeface.

Figure 34. Charge Curve, I_OCHARGENot Limited by

I_INLIM

Charge Mode

In Charge Mode, FAN54005 employs four regulation loops:

1. Input Current: Limits the amount of current drawn

from VBUS. This current is sensed internally and

V

OREG

2

can be programmed through the I C interface.

2. Charging Current: Limits the maximum charging

current, which is sensed using an external R

.

SNS

Choose R

to provide the desired I

and

SNS

OCHARGE

I_TERM

I

currents for your system, relative to the

TERM

V

SHORT

V

levels determined by the I

register settings, as shown in Table 4 and

and

RSNS

OCHARGE

I_SHORT

I

TERM

Table 5, respectively.

3. Charge Voltage: The regulator is restricted from

exceeding this voltage. As the internal battery

voltage rises, the battery’s internal impedance and

PRE−

CHARGE

CURRENT REGULATION

VOLTAGE

REGULATION

R

work in conjunction with the charge voltage

SNS

Figure 35. Charge Curve, I_INLIMLimits I_OCHARGE

regulation to decrease the amount of current

flowing to the battery. Battery charging is

completed when the voltage across R

Assuming that V

is programmed to the cell’s fully

OREG

drops

.

SNS

charged “float” voltage, the current that the battery accepts

with the PWM regulator limiting its output (sensed at

below the threshold determined by I

TERM

4. Temperature: If the IC’s junction temperature

reaches 120°C, charge current is reduced until the

IC’s temperature stabilizes at 120°C.

5. Dynamic Input Voltage Control (DIVC) limits the

amount of drop on VBUS to a programmable

VBAT) to V

declines, and the charger enters the

OREG

voltage regulation phase of charging. When the current

declines to the programmed I value, the charge cycle

is complete. Charge current termination can be disabled by

resetting the TE bit (REG 01[3]).

The charger output or “float” voltage can be programmed

by the OREG bits from 3.5 V to 4.44 V in 20 mV increments

as shown in Table 8.

TERM

voltage (V ) to accommodate incompatible

SP

adapters that limit current to a lower current than

might be available from a “normal” USB adapter.

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16

FAN54005

A new charge cycle begins when one of the following

occurs:

Table 8. OREG BITS (REG 02[7:2]) vs. CHARGER

V_OUT(V_OREG) FLOAT VOLTAGE

• The battery voltage falls below V

• VBUS Power on Reset (POR)

– V

RCH

OREG

Decimal

OREG

0

Hex

V

Decimal

Hex

V

OREG

2

• CE or HZ_MODE is reset through I C write to

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

3.50

3.52

3.54

3.56

3.58

3.60

3.62

3.64

3.66

3.68

3.70

3.72

3.74

3.76

3.78

3.80

3.82

3.84

3.86

3.88

3.90

3.92

3.94

3.96

3.98

4.00

4.02

4.04

4.06

4.08

4.10

4.12

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

4.14

4.16

4.18

4.20

4.22

4.24

4.26

4.28

4.30

4.32

4.34

4.36

4.38

4.40

4.42

4.44

CONTROL1 (REG 01) register.

1

Charge Current Limit (I_OCHARGE

)

2

Charge current limit is established by regulating the

voltage across R (V ) to the value controlled by the

3

SNS

RSNS

4

IOCHARGE bits. Select R

in the range of 68 mW < R

SNS

5

< 180 mW.

Charge current is further limited by the IO_LEVEL (Reg

05[5]) bit by default (IO_LEVEL=1). When IOLEVEL=1,

6

7

the voltage across R

is limited to 34.0 mV. When

SNS

8

IO_LEVEL=0 charge current is limited by the IOCHARGE

bits.

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Table 10. I_OCHARGECURRENT AS FUNCTION OF

I_OCHARGE(REG 04 [6:4]) BITS AND R_SNSVALUE

I

Range (mA)

OCHARGE

180 mW

68 mW

Decimal

HEX

V

RSNS

(mV)

IOCHARGE

0

1

2

3

4

5

6

7

00

01

02

03

04

05

06

07

37.4

208

246

283

321

397

434

510

548

550

650

44.2

51.0

57.8

71.4

78.2

91.8

98.6

750

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

850

1050

1150

1350

1450

Termination Current Limit

Current charge termination is enabled when TE (REG

01[3])=1.

Table 11. I_TERMCURRENT AS FUNCTION OF ITERM

BITS (REG 04[2:0]) AND R_SNSRESISTOR VALUES

I

Range (mA)

TERM

180 mW

68 mW

Decimal

ITERM

HEX

V

RSNS

(mV)

The following charging parameters can be programmed by

the host through I C:

0

1

2

3

4

5

6

7

00

01

02

03

04

05

06

07

3.3

18

37

49

2

6.6

9.9

97

55

146

194

243

291

340

388

Table 9. PROGRAMMABLE CHARGING PARAMETERS

Parameter

Output Voltage Regulation

Battery Charging Current Limit

Input Current Limit

Name

Register

13.2

16.5

19.8

23.1

26.4

73

V

OREG

REG 02[7:2]

REG 04[6:4]

REG 01[7:6]

REG 04[2:0]

REG 01[5:4]

92

I

110

128

147

OCHARGE

I

INLIM

TERM

Charge Termination Limit

Weak Battery Voltage

I

V

LOWV

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17

FAN54005

When the charge current falls below I

, PWM

LOW, and charging resumes using the default values with

the t timer running.

TERM

charging stops and the STAT bits change to READY (00) for

about 500 ms while the IC determines whether the battery

and charging source are still connected. STAT then changes

to CHARGE DONE (10), provided the battery and charger

are still connected.

15MIN

Normal charging is controlled by the host with the t

32S

timer running to ensure that the host is alive. Charging with

the t timer running is used for charging that is

15MIN

unattended by the host. If the t

timer expires; the IC

15MIN

turns off the charger, sets the CE bit, and indicates a timer

fault (110) on the FAULT bits (REG 00[2:0]). This sequence

PWM Controller in Charge Mode

The IC uses a current−mode PWM controller to regulate

the output voltage and battery charge currents. The

synchronous rectifier (Q2) has a current limit that switches

prevents overcharge if the host fails to reset the t timer.

32S

USB−Friendly Boot Sequence

At VBUS POR, the IC operates in accordance with its I C

2

off the FET when the current is more negative than I

.

SYNC

register settings. If no registers have been written (including

Safety, and the TMR_RST bit), typically due to an absence

of host communication, the chargers input current limit is

controlled by the OTG pin (100 mA if OTG is LOW and

500 mA if OTG is HIGH).

Charger Operation

V_BUSPlug In

When the IC detects that V

(4.4 V), the IC applies a 100 W load from VBUS to GND. To

clear the VBUS Power−On−Reset (POR) and begin

charging, VBUS must remain above V

has risen above V

IN(MIN)1

BUS

Once the host processor begins writing to the IC, charging

parameters are set by the host, which must continually reset

and below

IN(MIN)1

the t

timer to continue charging using the programmed

32S

VBUS

for t

(30 ms) before the IC initiates

OVP

VBUS_VALID

charging parameters.

charging.

The VBUS validation sequence always occurs before

charging is initiated or re−initiated (for example, after a

Input Current Limiting

To minimize charging time without overloading VBUS

current limitations, the IC’s input current limit can be

programmed by the IINLIM bits (REG 01[7:6]).

VBUS OVP fault or a V

recharge initiation).

RCH

T

ensures that unfiltered 50 / 60 Hz chargers

VBUS_VALID

and other non−compliant chargers are rejected.

Table 12. INPUT CURRENT LIMIT

Safety Timer

IINLIM REG 01[7:6]

Input Current Limit

100 mA

Section references Figure 39.

At the beginning of charging, the IC starts a 15−minute

00

01

10

11

500 mA

timer (t

). When this times out, charging is terminated.

15MIN

2

Writing to any register through I C stops and resets the

800 mA

t

timer, which in turn starts a 32−second timer (t ).

15MIN

32S

No limit

Setting the TMR_RST bit (REG 00[7]) resets the t timer.

32S

If the t

timer times out; charging is terminated, all

32S

The OTG pin establishes the input current limit when t

is running.

15MIN

registers (except Safety) are set to their default values, the

FAULT bits are set to 110, STAT is pulsed HIGH and returns

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18

FAN54005

Flow Charts

VBUS POR

YES

HZ State

HZ, CE or

DISABLE Pin

set?

V_BAT> V_LOWV

YES

Charge

Configuration

State

NO

HZ, CE or

DISABLE Pin

set?

T32Sec

Armed?

T15Min Timer?

NO

YES

HZ, CE or

DISABLE Pin

set?

YES

HZ State

T32Sec

Armed?

NO

YES

Charge State

Reset all registers

NO

Start T

15MIN

Figure 36. Charger VBUS POR

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19

FAN54005

Flow Charts (Continued)

CHARGE STATE

Disable Charging

NO

Indicate

VBUS Fault

Enable I

,

SHORT

Reset Safety reg

V_BAT< V

YES

VBUSOK?

YES

NO

SHORT

Indicate Charging

NO

PWM Charging

T_15MIN

VBUS OK?

YES

Indicate Charging

Timeout?

NO

YES

Disable Charging

Indicate timer fault

Set CE

Charge

Configuration

State

T_15MIN

Timeout?

YES

Indicate

VBUS Fault

NO

HIGHZ mode

I_OUT< I_TERM

Termination enabled

V_BAT> V_OREG–V_RCH

Indicate Charge

Complete

V_BAT< V_OREG–V_RCH

YES

NO

Reset Safety reg

Delay t_INT

NO

YES

Battery Removed

Stop Charging

YES

V_BAT< V_OREG–V_RCH

Reset charge

parameters

Enable IDET for T_DETECT

Figure 37. Charge Mode

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20

FAN54005

Flow Charts (Continued)

Charge

Configuration

State

T32Sec

YES

ARMED AND

Charge State

CE

CE# = 0?

NO

Has T15Min

and CCEE# = 0

START T15Min

NO

YES

VBAT < VOREG

for 262ms?

NO

YES

Figure 38. Charge Configuration

Charge Start

Start T_15MIN

Reset Registers

NO

YES

T_32SEC

Expired?

Start T_32SEC

YES

NO

Stop T_15MIN

T_15MIN

I²C Write

received?

T_15MIN

Continue

Charging

YES

NO

Active?

Expired?

Timer Fault :

Set CE

YES

CE

Figure 39. Timer Flow Chart

Dynamic Input Voltage Control

If V

collapses to V when the current is ramping up, the

SP

BUS

The FAN54005 has functionality that limits input current

in case a current−limited incompatible adapter is supplying

VBUS. These slowly increase the charging current until

either:

FAN54005 charges with an input current that keeps

=V . When the V control loop is limiting the charge

current, the SP bit (REG 05[4]) is set.

V

BUS

SP

• I

or I

is reached

INLIM

OCHARGE

or

• V =V .

BUS

SP

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21

FAN54005

Table 13. V_SPAS FUNCTION OF VSP BITS (REG 05[2:0])

Table 15. V_SAFE(V_OREGMax. Limit) AS FUNCTION

OF VSAFE BITS (REG 06[3:0])

Decimal

HEX

V

SP

Max. OREG

(REG 02[7:2])

V

OREG

Max. (V)

VSP

Decimal

VSAFE

HEX

0

1

2

3

4

5

6

7

00

01

02

03

04

05

06

07

4.213

4.293

4.373

4.453

4.533

4.613

4.693

4.773

0

1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

4.20

4.22

4.24

4.26

4.28

4.30

4.32

4.34

4.36

4.38

4.40

4.42

4.44

2

3

4

5

6

7

Safety Settings

8

FAN54005 contain a SAFETY register (REG 06) that

prevents the values in OREG (REG 02[7:2]) and

IOCHARGE (REG 04[6:4]) from exceeding the values of

the VSAFE and ISAFE values. Refer to Table 14 and

Table 15 for details.

9

10

11

12

13

14

15

After V

exceeds V

, the SAFETY register is

BAT

SHORT

loaded with its default value and may be written only before

any other register is written. The entire desired Safety

register value should be written twice to ensure the register

bits are set. After writing to any other register, the SAFETY

register is locked until V

falls below V

.

BAT

SHORT

The ISAFE (REG 06[6:4]) and VSAFE (REG 06[3:0])

registers establish the maximum values of V and

Thermal Regulation and Protection

When the IC’s junction temperature reaches T (about

RSNS

CF

V

OREG

used by the control logic. If the host attempts to write

120°C), the charger reduces its output current to

a value higher than VSAFE or ISAFE to OREG or

IOCHARGE, respectively; the VSAFE, ISAFE value

appears as the OREG, IOCHARGE register value,

respectively.

37.4 mV/R

to prevent overheating. If the temperature

SNS

increases beyond T

; charging is suspended, the

SHUTDOWN

FAULT bits are set to 101, and STAT is pulsed HIGH. In

Suspend Mode, all timers stop and the state of the IC’s logic

is preserved. Charging resumes at programmed current after

the die cools to about 120°C.

Table 14. I_SAFE(I_OCHARGELimit) AS FUNCTION OF

ISAFE BITS (REG 06[6:4])

Additional q

data points, measured using the

JA

I

Range (mA)

SAFE

FAN54005 evaluation board, are given in Table 16

(measured with T =25°C). Note that as power dissipation

180 mW

68 mW

A

Decimal

ISAFE

HEX

V

RSNS

(mV)

increases, the effective q decreases due to the larger

JA

difference between the die temperature and ambient.

0

1

2

3

4

5

6

7

00

01

02

03

04

05

06

07

37.4

208

246

283

321

397

434

510

548

550

650

Table 16. EVALUATION BOARD MEASURED q_JA

44.2

51.0

57.8

71.4

78.2

91.8

98.6

Dissipation (W)

0.504

q

JA

750

54°C/W

50°C/W

46°C/W

850

0.844

1050

1150

1350

1450

1.506

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22

FAN54005

Charge Mode Input Supply Protection

Sleep Mode

If V

the IC:

is below V

– V

, the battery is absent and

BAT

OREG

RCH

1. Sets the registers to their default values.

2. Sets the FAULT bits to 111.

3. Resumes charging with default values after t

When V

falls below V

+ V , and V

is above

BUS

BAT

SLP

BUS

V

the IC enters Sleep Mode to prevent the battery

IN(MIN)1,

.

INT

from draining into VBUS. During Sleep Mode, reverse

current is disabled by body switching Q1.

Battery Short−Circuit Protection

If the battery voltage is below the short−circuit threshold

(V ); a linear current source, I , supplies V

Input Supply Low−Voltage Detection

The IC continuously monitors VBUS during charging. If

SHORT

BAT

until V

> V

.

BAT

SHORT

V

BUS

falls below V

, the IC:

IN(MIN)2

1. Terminates charging

System Operation with No Battery

2. Pulses the STAT pin, sets the STAT bits to 11, and

sets the FAULT bits to 011.

The FAN54005 continues charging after VBUS POR with

the default parameters, regulating the V line to 3.54 V

BAT

If V

recovers above the V

rising threshold

until the host processor issues commands or the t

timer

BUS

IN(MIN)1

15MIN

after time t

(about two seconds), the charging process is

expires. In this way, the FAN54005 can start the system

without a battery.

The FAN54005 soft−start function may interfere with the

system supply when the battery is absent. The soft−start

INT

repeated. This function prevents the USB power bus from

collapsing or oscillating when the IC is connected to a

suspended USB port or a low−current−capable OTG device.

activates whenever V

from a lower to higher value. During soft−start, the I limit

drops to 100 mA for about 1 ms unless IINLIM is set to 11

(no limit). This could cause the system processor to fail to

start. To avoid this behavior, use the following sequence.

1. Set the OTG pin HIGH. When VBUS is plugged

, I

, or I

are set

IN

OREG INLIM

OCHARGE

Input Over−Voltage Detection

When V

exceeds VBUS , the IC:

OVP

BUS

1. Turns off Q3

2. Suspends charging

3. Sets the FAULT bits to 001, sets the STAT bits to

11, and pulses the STAT pin.

in, I

is set to 500 mA until the system

INLIM

processor powers up and can set parameters

through I C.

2. Program the Safety Register.

3. Set IINLIM to 11 (no limit).

4. Set OREG to the desired value (typically 4.18).

5. Reset the IO_LEVEL bit, then set IOCHARGE.

When V

falls about 100 mV below VBUS , the fault

OVP

BUS

2

is cleared and charging resumes after V

is revalidated.

BUS

VBUS Short While Charging

If VBUS is shorted with a very low impedance while the

IC is charging with I =100 mA, the IC may not meet

datasheet specifications until power is removed. To trigger

this condition, V must be driven from 5 V to GND with

INLIMIT

6. Set I

to 500 mA if a USB source is

INLIM

BUS

connected.

a high slew rate. Achieving this slew rate requires a 0 W

short from GND to the USB cable that is less than 10 cm

from the connector.

During the initial system startup, while the charger IC is

being programmed, the system current is limited to 500 mA

for 1 ms during steps 4 and 5. This is the value of the

soft−start I

Limit.

current used when I

is set to No

OCHARGE

INLIM

Charge Mode Battery Detection & Protection

If the system is powered up without a battery present, the

CV bit should be set. When a battery is inserted, the CV bit

is cleared.

VBAT Over−Voltage Protection

The OREG voltage regulation loop prevents V

overshooting the OREG voltage by more than 50 mV when

the battery is removed. When the PWM charger runs with no

battery, the TE bit is not set, and a battery is inserted that is

charged to a voltage higher than V

If no further pulses occur for 30 ms, the IC sets the FAULT

bits to 100, sets the STAT bits to 11, and pulses the STAT pin.

from

BAT

Charger Status / Fault Status

The STAT pin indicates the operating condition of the IC

and provides a fault indicator for interrupt driven systems.

; PWM pulses stop.

OREG

Table 17. STAT PIN FUNCTION

EN_STAT

Charge State

X

STAT Pin

OPEN

LOW

Battery Detection during Charging

The IC can detect the presence, absence, or removal of a

battery if the termination bit (TE) is set. During normal

0

X

1

Normal Conditions

Charging

charging, once V

is close to V

and the termination

BAT

OREG

charge current is detected, the IC terminates charging and

sets the STAT bits to 10. It then turns on a discharge current,

X

Fault (Charging or Boost)

128 ms Pulse, then

OPEN

I

, for t

. If V

is still above V

– V

,

DETECT

BAT

OREG

RCH

the battery is present and the IC sets the FAULT bits to 000.

www.onsemi.com

23

FAN54005

Boost Mode

The FAULT bits (REG 00[2:0]) indicate the type of fault

in Charge Mode. See Table 18 for details.

Boost Mode can be enabled if the IC is in 32−Second

Mode with the OTG pin and OPA_MODE bits as indicated

in Table 21. The OTG pin ACTIVE state is 1 if OTG_PL=1

and 0 when OTG_PL=0.

Table 18. FAULT STATUS BITS DURING CHARGE MODE

Fault Bit

If boost is active using the OTG pin, Boost Mode is

initiated even if the HZ_MODE=1. The HZ_MODE bit

overrides the OPA_MODE bit.

B2

0

B1

0

B0

0

Fault Description

Normal (No Fault)

0

1

VBUS OVP

Table 21. ENABLING BOOST

0

1

0

Sleep Mode

OTG_EN OTG Pin HZ_MODE OPA_MODE

BOOST

Enabled

Disabled

0

1

Poor Input Source

Battery OVP

Thermal Shutdown

Timer Fault

1

X

0

1

0

ACTIVE

X

0

X

1

0

X

1

0

X

1

0

1

0

1

0

1

ACTIVE

X

1

0

1

No Battery

ACTIVE

Charge Mode Control Bits

Setting either HZ_MODE or CE through I C disables the

charger and puts the IC into High−Impedance Mode. The

32S

registers (except SAFETY) reset, which enables t

charging. When the t

the IC enters High−Impedance Mode. If CE was set by

2

To remain in Boost Mode, the TMR_RST must be set by

the host before the t timer times out. If t times out in

32S

t

timer will continue to run. If it is allowed to expire, all

Boost Mode; the IC resets all registers, pulses the STAT pin,

sets the FAULT bits to 110, and resets the BOOST bit. VBUS

POR or reading REG00 clears the fault condition.

15MIN

expires, the IC sets the CE bit and

15MIN

t

overflow, a new charge cycle can only be initiated

Boost PWM Control

15MIN

2

through I C or VBUS POR.

The IC uses a minimum on−time and computed minimum

off−time to regulate VBUS. The regulator achieves

excellent transient response by employing current−mode

modulation. This technique causes the regulator to exhibit a

load line. During PWM Mode, the output voltage drops

slightly as the input current rises. With a constant V , this

appears as a constant output resistance.

The “droop” caused by the output resistance when a load

is applied allows the regulator to respond smoothly to load

transients with no undershoot from the load line. This can be

seen in Figure 32 and Figure 40.

Setting the RESET bit clears all registers (except Safety).

Table 19. DISABLE PIN AND CE BIT FUNCTIONALITY

Charging

ENABLE

DISABLE

DISABLE Pin

CE

0

HZ_MODE

BAT

0

X

1

0

X

1

X

Raising the DISABLE pin does stop the t

from

32S

350

325

300

275

250

225

200

advancing. If the DISABLE pin is raised during t

15MIN

charging, the t

timer is reset.

15MIN

Operational Mode Control

OPA_MODE (REG 01[0]) and the HZ_MODE (REG

01[1]) bits in conjunction with the FAULT state define the

operational mode of the charger.

Table 20. OPERATION MODE CONTROL

HZ_MODE

OPA_MODE

FAULT

Operation Mode

Charge

0

1

0

X

1

0

1

0

X

Charge Configure

Boost

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Figure 40. Output Resistance (R_OUT

)

X

High Impedance

The IC resets the OPA_MODE bit whenever the boost is

deactivated, whether due to a fault or being disabled by

setting the HZ_MODE bit.

www.onsemi.com

24

FAN54005

V

BUS

as a function of I

can be computed when the

To ensure VBUS does not pump significantly above the

LOAD

regulator is in PWM Mode (continuous conduction) as:

regulation point, the boost switch remains off as long as the

actual output voltage is greater than the regulation point.

V_BUS+ 5.07 * R_OUT@ I_LOAD

(eq. 1)

Boost Faults

At V =3.3 V, and I

=200 mA, V

would drop to:

BAT

LOAD

BUS

If a BOOST fault occurs:

V_BUS+ 5.07 * 0.26 @ 0.2 + 5.018 V

(eq. 2)

1. The STAT pin pulses.

At V =2.7 V, and I

=200 mA, V

would drop to:

BAT

LOAD

BUS

2. OPA_MODE bit is reset.

3. The power stage is in High−Impedance Mode.

4. The FAULT bits (REG 00[2:0]) are set per

Table 23

V_BUS+ 5.07 * 0.327 @ 0.2 + 5.005 V

(eq. 3)

PFM Mode

If V

> V

(nominally 5.07 V) when the

BUS

BOOST

Restart After Boost Faults

minimum off−time has ended, the regulator enters PFM

Mode. Boost pulses are inhibited until V < V . The

minimum on−time is increased to enable the output to pump

up sufficiently with each PFM boost pulse. Therefore the

regulator behaves like a constant on−time regulator, with the

bottom of its output voltage ripple at 5.07 V in PFM Mode.

If boost was enabled with the OPA_MODE bit and

OTG_EN=0, Boost Mode can only be enabled through

BUS

BOOST

2

subsequent I C commands since OPA_MODE is reset on

boost faults. If OTG_EN=1 and the OTG pin is still

ACTIVE (see Table 21), the boost restarts after a 5.2 ms

delay, as shown in Figure 41. If the fault condition persists,

restart is attempted every 5 ms until the fault clears or an I C

command disables the boost.

2

Table 22. BOOST PWM OPERATING STATES

Mode

LIN

Description

Linear Startup

Invoked When

> V

V

BAT

Table 23. FAULT BITS DURING BOOST MODE

Fault Bit

BUS

SS

Boost Soft−Start

Boost Operating Mode

V

< V

BUS BOOST

B2 B1 B0

BST

V

BAT

> UVLO

and

Fault Description

BST

SS Completed

0

1

0

1

0

Normal (no fault)

V

> VBUS

OVP

BUS

Startup

fails to achieve the voltage required to

BUS

When the boost regulator is shut down, current flow is

prevented from VBAT to VBUS, as well as reverse flow

from VBUS to VBAT.

advance to the next state during soft−start or

sustained (>50 ms) current limit during the BST

state.

0

1

0

1

0

1

0

1

V

< UVLO

BAT BST

LIN State

When the boost is enabled, if V

N/A: This code does not appear.

Thermal shutdown

> UVLO , the

BST

BAT

regulator first attempts to bring PMID within 400 mV of

using an internal 450 mA current source from VBAT

V

BAT

Timer fault; all registers reset.

N/A: This code does not appear.

(LIN State). If PMID has not achieved V

560 ms, a FAULT state is initiated.

– 400 mV after

BAT

0

VBUS

SS State

When PMID > V

switching with a reduced peak current limit of about 50% of

its normal current limit. The output slews up until V is

within 5% of its setpoint; at which time, the regulation loop

is closed and the current limit is set to 100%.

– 400 mV, the boost regulator begins

560

5200

BAT

450mA

BATTERY

CURRENT

BUS

0

64

BOOST

ENABLED

If the output fails to achieve 95% of its setpoint (V

)

BST

Figure 41. Boost Response Attempting to Start into

within 128 ms, the current limit is increased to 100%. If the

output fails to achieve 95% of its setpoint after this second

384 ms period, a fault state is initiated.

VBUS Short Circuit (times in ms)

VREG Pin

The 1.8 V regulated output on this pin can be disabled

through I C by setting the DIS_VREG bit (REG 05[6]).

BST State

2

This is the normal operating mode of the regulator. The

regulator uses a scheme of calculated t , modulated t

VREG can supply up to 2 mA. This circuit, which is

OFF

ON

with a minimum t . The calculated t

is proportional to

powered from PMID, is enabled only when PMID > V

ON

OFF

BAT

V

/ V

, which keeps the regulator’s switching

and does not drain current from the battery. During boost,

V is off. It is also off when the HZ_MODE bit (REG

REG

IN

OUT

frequency reasonably constant in CCM.

01[1])=1.

www.onsemi.com

25

FAN54005

Monitor Register (Reg 10h)

A transaction ends with a STOP condition, which is

defined as SDA transitioning from 0 to 1 with SCL HIGH,

as shown in Figure 44.

Additional status monitoring bits enable the host

processor to have more visibility into the status of the IC.

The monitor bits are real−time status indicators and are not

internally debounced or otherwise time qualified.

The state of the MONITOR register bits listed in

High−Impedance Mode is only valid when V

Slave Releases

Master Drives

t_HD;STO

ACK(0) or

NACK(1)

SDA

SCL

is valid.

BUS

I²C Interface

The FAN54005’s serial interface is compatible with

Standard, Fast, Fast Plus, and High−Speed Mode I C−Bus

2

Figure 44. Stop Bit

specifications. The SCL line is an input and the SDA line is

a bi−directional open−drain output; it can only pull down the

bus when active. The SDA line only pulls LOW during data

reads and signaling ACK. All data is shifted in MSB (bit 7)

first.

During a read from the FAN54005 (Figure 47), the master

issues a Repeated Start after sending the register address and

before resending the slave address. The Repeated Start is a

1−to−0 transition on SDA while SCL is HIGH, as shown in

Figure 45.

Slave Address

High−Speed (HS) Mode

Table 24. I²C SLAVE ADDRESS BYTE

The protocols for High−Speed (HS), Low−Speed (LS),

and Fast−Speed (FS) Modes are identical except the bus

speed for HS Mode is 3.4 MHz. HS Mode is entered when

the bus master sends the HS master code 00001XXX after

a start condition. The master code is sent in Fast or Fast Plus

Mode (less than 1 MHz clock); slaves do not ACK this

transmission.

Part Type

7

6

5

4

3

2

1

0

FAN54005

1

0

1

0

1

0

R/W

In hex notation, the slave address assumes a 0 LSB. The

hex slave address for the FAN54005 is D4H and is D6H for

all other parts in the family.

The master then generates a repeated start condition

(Figure 45) that causes all slaves on the bus to switch to HS

Mode. The master then sends I C packets, as described

above, using the HS Mode clock rate and timing.

The bus remains in HS Mode until a stop bit (Figure 44)

is sent by the master. While in HS Mode, packets are

separated by repeated start conditions (Figure 45).

Bus Timing

As shown in Figure 42, data is normally transferred when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

2

Data change allowed

Slave Releases

t_SU;STA

t_HD;STA

SDA

ACK(0) or

NACK(1)

SLADDR

MS Bit

SDA

SCL

T_H

T_SU

SCL

Figure 45. Repeated Start Timing

Read and Write Transactions

The figures below outline the sequences for data read and

write. Bus control is signified by the shading of the packet,

defined as

Figure 42. Data Transfer Timing

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which

is defined as SDA transitioning from 1 to 0 with SCL HIGH,

as shown in Figure 43.

Master Drives Bus

T_HD;STA

Slave Address

MS Bit

SDA

and

Slave Drives Bus

SCL

All addresses and data are MSB first.

Figure 43. Start Bit

www.onsemi.com

26

FAN54005

Table 25. BIT DEFINITIONS FOR FIGURE 46 AND FIGURE 47

Symbol

Definition

S

A

R

P

START, see Figure 43

ACK. The slave drives SDA to 0 to acknowledge the preceding packet.

NACK. The slave sends a 1 to NACK the preceding packet.

Repeated START, see Figure 45

STOP, see Figure 44

0

7 bits

8 bits

Data

S

Slave Address

0

A

Reg Addr

A

P

Figure 46. Write Transaction

0

1

7 bits

Slave Address

8 bits

7 bits

8 bits

Data

S

0

A

Reg Addr

A

R

Slave Address

1

A

P

Figure 47. Read Transaction

Register Descriptions

The nine FAN54005 user−accessible registers are defined in Table 26.

Table 26. I²C REGISTER ADDRESS

Register

Address Bits

Name

CONTROL0

CONTROL1

OREG

REG#

00

7

0

6

0

5

4

0

1

3

0

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

01

02

IC_INFO

03

IBAT

04

SP_CHARGER

SAFETY

05

06

MONITOR

10h

www.onsemi.com

27

FAN54005

Table 27. REGISTER BIT DEFINITIONS

This table defines the operation of each register bit for all IC versions. Default values are in bold text.

Bit

Name

Value

Type

Description

Default Value=X1XX 0XXX

timer; writing a 0 has no effect

CONTROL0

Register Address: 00

7

6

TMR_RST OTG

EN_STAT

1

0

W

R

Writing a 1 resets the t

32S

Returns the OTG pin level (1=HIGH)

R/W

Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate

faults

1

00

01

10

11

0

Enables STAT pin LOW when IC is charging

5:4

STAT

R

Ready

Charge in progress

Charge done

Fault

3

BOOST

FAULT

R

IC is not in Boost Mode

IC is in Boost Mode

1

2:0

R

Fault status bits: for Charge Mode, see Table 18

CONTROL1

Register Address: 01

Default Value=0111 0000 (70h)

7:6

5:4

IINLIM

01

00

01

10

11

0

R/W

Input current limit, see Table 12

VLOWV

3.4 V

Weak battery voltage threshold

3.5 V

3.6 V

3.7 V

3

2

TE

CE

R/W

Disable charge current termination

Enable charge current termination

Charger enabled.

1

0

1

Charger disabled. The T

timer is not suspended

32S

1

0

HZ_MODE

0

Not High−Impedance Mode

High−Impedance Mode

Charge Mode

See Table 21

1

OPA_MODE

0

1

Boost Mode

OREG

Register Address: 02

Default Value=0000 1010 (0Ah)

7:2

OREG

000010

R/W

Charger output “float” voltage; programmable from 3.5 to 4.44 V in 20 mV increments;

defaults to 000010 (3.54 V). See Table 8

1

0

OTG_PL

0

1

0

1

OTG pin active LOW

OTG pin active HIGH

Disables OTG pin

Enables OTG pin

OTG_EN

R/W

IC_INFO

7:5

Register Address: 03

Default Value=100101XX (9Xh)

Vendor Code

PN

100

101

XX

R

Identifies ON Semiconductor as the IC supplier

4:2

Part number bits, see the Ordering Information on page 1

1:0

REV

IC Revision bits

IBAT

7

Register Address: 04

Default Value=1000 1001 (89h)

RESET

1

W

Writing a 1 resets charge parameters, except the Safety register (REG 06), to their de-

faults: writing a 0 has no effect; read returns 1

6:4

IOCHARGE

000

R/W

Programs the maximum charge current when IO_LEVEL (REG 05[5]) = 0. See Table 10

www.onsemi.com

28

FAN54005

Table 27. REGISTER BIT DEFINITIONS

This table defines the operation of each register bit for all IC versions. Default values are in bold text.

Bit

3

Name

Reserved

ITERM

Value

1

Type

R

Description

Unused

Sets the current used for charging termination. See Table 11

2:0

001

R/W

SP_CHARGER

Register Address: 05

Default Value=001X X100

7

6

Reserved

0

R

Unused

DIS_VREG

IO_LEVEL

SP

R/W

1.8 V regulator is ON

1

1.8 V regulator is OFF

5

4

3

0

R/W

R

Output current is controlled by the IOCHARGE bits

1

Output current control is limited to 34 mV across R

SNS

0

DIVC is not active (V

is able to stay above V

)

BUS

SP

1

DIVC has been detected and V

is being regulated to V

BUS SP

EN_LEVEL

VSP

0

R

DISABLE pin is LOW

1

DISABLE pin is HIGH

2:0

100

R/W

DIVC input regulation voltage. See Table 13

SAFETY

7

Register Address: 06

Default Value=0100 0000 (40h)

Reserved

ISAFE

0

R

Bit disabled and always returns 0 when read back

6:4

100

0000

R/W

Sets the maximum I

value used by the control circuit. See Table 14

used by the control circuit. See Table 15

OCHARGE

3:0

VSAFE

Sets the maximum V

OREG

MONITOR

Register Address: 10h (16)

7

6

ITERM_CMP

VBAT_CMP

R

ITERM comparator output, 1 when VRSENSE > See Table 11

Output of VBAT comparator

1 during charging indicates V

> V

BAT

SHORT

1 during HZ_MODE indicates V

> V

LOWV

BAT

1 during Boost Mode indicated V

> UVLO

BST

BAT

5

4

LINCHG

T_120

R

30 mA linear charger ON

Thermal regulation comparator; when=1 and T_145=0, the charge current is limited to

22.1 mV across R

SENSE

3

2

1

0

ICHG

IBUS

R

0 indicates the I

loop is controlling the battery charge current

OCHARGE

0 indicates the IBUS (input current) loop is controlling the battery charge current

1 indicates VBUS has passed validation and is capable of charging

VBUS_VALID

CV

1 indicates the constant−voltage loop (OREG) had been active at least once since the

last V

plug in

BUS

0 indicates the constant−voltage loop (OREG) had never been reached since the last

VBUS plug in or the part is in the Charge Done state with TE=1

www.onsemi.com

29

FAN54005

PCB Layout Recommendations

Bypass capacitors should be placed as close to the IC as

routed to their bypass capacitors, using top copper whenever

possible. Copper area connecting to the IC should be

maximized to improve thermal performance if possible.

possible. In particular, the total loop length for CMID should

be minimized to reduce overshoot and ringing on the SW,

PMID, and VBUS pins. All power and ground pins must be

Figure 48. PCB Layout Recommendations

The table below pertains to the MOD information on the following page.

PRODUCT−SPECIFIC DIMENSIONS

Product

D

E

X

Y

FAN54005UCX

1.960 0.030 mm

1.870 0.030 mm

0.335 mm

0.180 mm

2

ON Semiconductor is licensed by the Philips Corporation to use the I C bus protocol.

www.onsemi.com

30

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WLCSP20 1.96x1.87x0.586

CASE 567SL

ISSUE O

DATE 30 NOV 2016

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON16608G

WLCSP20 1.96x1.87x0.586

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

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www.onsemi.com

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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	FAN54005UCX
厂家：	ONSEMI
描述：	电池充电控制器，开关，200mA - 1.45 A，带 USB-OTG 升压稳压器电池开关控制器稳压器
文件：	总32页 (文件大小：4712K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN54005UCX [ONSEMI]

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