FAN54015BUCX [ONSEMI]
符合 USB 规范的单体锂离子开关充电器（带 USB-OTG 升压调节器）;
| 型号： | FAN54015BUCX |
| 厂家： | 
ONSEMI |
| 描述： | 符合 USB 规范的单体锂离子开关充电器（带 USB-OTG 升压调节器） 开关 调节器 |
| 文件： | 总33页 (文件大小：1184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USB-Compliant Single-Cell
Li-Ion Switching Charger
with USB-OTG Boost
Regulator
FAN54015
Description
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The FAN54015 combines a highly integrated switch−mode charger,
to minimize single−cell Lithium−ion (Li−ion) charging time from a
USB power source, and a boost regulator to power a USB peripheral
from the battery.
The charging parameters and operating modes are programmable
through an I C Interface that operates up to 3.4 Mbps. The charger and
boost regulator circuits switch at 3 MHz to minimize the size of
external passive components.
2
WLCSP20 1.96x1.87x0.586
CASE 567SL
The FAN54015 provides battery charging in three phases:
conditioning, constant current and constant voltage.
MARKING DIAGRAM
To ensure USB compliance and minimize charging time, the input
2
current limit can be changed through the I C by the host processor.
A9&K
&.&2&Z
Charge termination is determined by a programmable minimum
current level. A safety timer with reset control provides a safety
backup for the I C host. Charge status is reported to the host through
2
2
the I C port.
A9 = Specific Device Code
&K = 2−Digits Lot Run Traceability Code
&. = Pin One Dot
&2 = 2−Digit Date Code Format
&Z = Assembly Plant Code
The integrated circuit (IC) automatically restarts the charge cycle
when the battery falls below an internal threshold. If the input source is
removed, the IC enters a high−impedance mode, preventing leakage
from the battery to the input. Charge current is reduced when the die
temperature reaches 120°C, protecting the device and PCB from
damage.
The FAN54015 can operate as a boost regulator on command from
the system. The boost regulator includes a soft−start that limits inrush
current from the battery and uses the same external components used
for charging the battery.
ORDERING INFORMATION
See detailed ordering and shipping information on page 31 of
this data sheet.
Features (continued)
• 3 MHz Synchronous Buck PWM Controller
with Wide Duty Cycle Range
Features
• Fully Integrated, High−Efficiency Charger for Single−Cell Li−Ion
and Li−Polymer Battery Packs
• Small Footprint 1 mH External Inductor
• Safety Timer with Reset Control
• 1.8 V Regulated Output from VBUS for
Auxiliary Circuits
• Faster Charging than Linear
• Charge Voltage Accuracy: +0.5% at 25°C
+1% from 0 to 125°C
• Dynamic Input Voltage Control
• +5% Input Current Regulation Accuracy
• +5% Charge Current Regulation Accuracy
• Low Reverse Leakage to Prevent Battery
Drain to VBUS
• 20 V Absolute Maximum Input Voltage
• 6 V Maximum Input Operating Voltage
• 1.45 A Maximum Charge Rate
• 5 V, 500 mA Boost Mode for USB OTG for
3.0 V to 4.5 V Battery Input
• Available in a 1.96 x 1.87 mm, 20−bump,
0.4 mm Pitch WLCSP Package
• These are Pb−Free Devices
2
• Programmable through High−Speed I C Interface (3.4 Mb/s) with
Fast Mode Plus Compatibility
♦ Input Current
♦ Fast−Charge / Termination Current
♦ Charger Voltage
Applications
• Cell Phones, Smart Phones, PDAs
• Tablet, Portable Media Players
• Gaming Device, Digital Cameras
♦ Termination Enable
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
November, 2019 − Rev. 2
FAN54015D
FAN54015
L1
SW
VBUS
1 μH
C
1 μF
BUS
C
0.1 μF
OUT
PGND
PMID
C
4.7 μF
MID
CSIN
R
SDA
SENSE
FAN54015
68 mW
SCL
DISABLE
OTG/USB#
STAT
VBAT
Battery
C
10 μF
+
BAT
VREG
SYSTEM
LOAD
C
REG
1 μF
Figure 1. Typical Application
Table 1. FEATURE SUMMARY
Automatic
Charge
Special
Charger (Note 1)
Safety
Limits
Battery Absent
Behavior
Part Number
Slave Address
E2 Pin
VREG (E3 Pin)
FAN54015UCX
1101010
Yes
Yes
Yes
ON
DISABLE
1.8 V
1. A “special charger” is a current−limited charger that is not a USB compliant source.
VREG
1.8 V / PMID REG
C
REG
PMID
PMID
1 μF
Q1
Q2
C
Q3
MID
4.7 μF
Q1A
Q1B
VBUS
CHARGE
PUMP
C
BUS
L1
1 μF
SW
PWM
MODULATOR
1 μH
I_IN
CONTROL
VBUS
OVP
R
C
SENSE
OUT
0.1 μF
PGND
VCC
VREF
+
Battery
CSIN
VBAT
DAC
C
BAT
SDA
SCL
PMID
SYSTEM
LOAD
2
I C
STAT
30 mA
INTERFACE
OSC
DISABLE
LOGIC
AND
PMID
Q1A
ON
Q1B
OFF
ON
OTG/USB#
Greater than VBAT
Less than VBAT
CONTROL
OFF
Figure 2. IC and System Block Diagram
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2
FAN54015
Table 2. RECOMMENDED EXTERNAL COMPONENTS
Component
Description
Vendor
Parameter
Typ
Unit
L1
Murata: LQM2HPN1R0
Murata: LQM2MPN1R0
L
1.0
mH
1 mH 20%, 1.6 A, DCR = 55 mW, 2520
1 mH 30%, 1.4 A, DCR = 85 mW, 2016
10 mF, 20%, 6.3 V, X5R, 0603
CBAT
CMID
CBUS
Murata: GRM188R60J106M
TDK: C1608X5R0J106M
C
C (Note 2)
C
10
4.7
1.0
mF
mF
mF
4.7 mF, 10%, 6.3 V, X5R, 0603
1.0 mF, 10%, 25 V, X5R, 0603
Murata: GRM188R60J475K
TDK: C1608X5R0J475K
Murata GRM188R61E105K
TDK:C1608X5R1E105M
2. A 6.3 V rating is sufficient for C
because PMID is protected from over−voltage surges on VBUS by Q3 (Figure 2).
MID
A1
B1
C1
D1
E1
A2
B2
C2
D2
E2
A3
B3
C3
D3
E3
A4
B4
C4
D4
E4
A4
B4
C4
D4
E4
A3
B3
C3
D3
E3
A2
B2
C2
D2
E2
A1
B1
C1
D1
E1
Top View
Bottom View
Figure 3. WLCSP−20 Pin Assignments
PIN DEFINITIONS
Pin #
A1, A2
A3
Name
VBUS
NC
Description
Charger Input Voltage and USB−OTG output voltage. Bypass with a 1 mF capacitor to PGND.
No Connect. No external connection is made between this pin and the IC’s internal circuitry.
2
A4
SCL
I C Interface Serial Clock. This pin should not be left floating.
B1−B3
PMID
Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense, and
high−voltage input switch. Bypass with a minimum of 4.7 mF, 6.3 V capacitor to PGND.
2
B4
SDA
SW
I C Interface Serial Data. This pin should not be left floating.
C1 − C3
C4
Switching Node. Connect to output inductor.
STAT
PGND
Status. Open−drain output indicating charge status. The IC pulls this pin LOW when charging.
Power Ground. Power return for gate drive and power transistors. The connection from this pin to the bottom
D1 − D3
of C
should be as short as possible.
MID
D4
E1
E2
E3
E4
OTG
On−The−Go. Enables boost regulator in conjunction with OTG_EN and OTG_PL bits (see Table 16). On
VBUS Power−On Reset (POR), this pin sets the input current limit for t charging.
15MIN
CSIN
Current−Sense Input. Connect to the sense resistor in series with the battery. The IC uses this node to sense
current into the battery. Bypass this pin with a 0.1 mF capacitor to PGND.
2
DISABLE Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is controlled by the I C
registers. When this pin is HIGH, the 15−minute timer is reset. This pin does not affect the 32−second timer.
VREG
Regulator Output. Connect to a 1 mF capacitor to PGND. This pin can supply up to 2mA of DC load current.
The output voltage is PMID, which is limited to 1.8 V.
VBAT
Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 0.1 mF capacitor to
PGND if the battery is connected through long leads.
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3
FAN54015
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Continuous
Min
–1.4
–2.0
–0.3
−
Max
Unit
V
BUS
VBUS Voltage
20.0
V
Pulsed, 100 ms Maximum Non−Repetitive
V
STAT
STAT Voltage
16.0
V
V
V
I
PMID Voltage
7.0
SW, CSIN, VBAT, DISABLE Voltage
Voltage on Other Pins
–0.3
–0.3
−
7.0
6.5 (Note 3)
4
V
V
O
Maximum V
Slope above 5.5 V when Boost or Charger are Active
V/ms
dVBUS
dt
BUS
ESD
Electrostatic Discharge Protection
Level
Human Body Model per JESD22−A114
Charged Device Model per JESD22−C101
2000
500
V
T
Junction Temperature
Storage Temperature
–40
–65
−
+150
+150
+260
°C
°C
°C
J
T
STG
T
L
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Lesser of 6.5 V or V + 0.3 V.
I
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4
Max
6
Unit
V
V
BUS
Supply Voltage
V
Maximum Battery Voltage when Boost enabled
Negative VBUS Slew Rate during VBUS Short Circuit,
−
4.5
4
V
BAT(MAX)
T
≤ 60°C
≥ 60°C
−
V/ms
dVBUS
A
C
≤ 4.7 mF (see VBUS Short While Charging)
*
MID
T
A
−
2
dt
T
Ambient Temperature
Junction Temperature (see Thermal Regulation and Protection section)
–30
–30
+85
+120
°C
°C
A
T
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
THERMAL PROPERTIES
Symbol
Parameter
Value
60
Unit
°C/W
°C/W
q
q
Junction−to−Ambient Thermal Resistance
Junction−to−PCB Thermal Resistance
JA
JB
20
Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p boards in
accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature T at a given ambient
J(max)
temperature T . For measured data, see Table 11.
A
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4
FAN54015
ELECTRICAL SPECIFICATIONS (Unless otherwise specified: according to the circuit of Figure 1; recommended operating
temperature range for T and T ; V = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical
J
A
BUS
values are for T = 25°C)
J
Symbol
Parameter
Conditions
Min
Typ
Max Unit
POWER SUPPLIES
I
VBUS Current
V
V
> V
> V
, PWM Switching
; PWM Enabled,
−
−
10
−
−
mA
mA
VBUS
BUS
BUS(min)
2.5
BUS
BUS(min)
Not Switching (Battery OVP Condition);
I_IN Setting = 100 mA
0°C < T < 85°C, HZ_MODE = 1
−
−
63
90
mA
mA
mA
J
< V
V
, 32S Mode
BAT
LOWV
I
VBAT to VBUS Leakage Current
0°C < T < 85°C, HZ_MODE = 1,
0.2
5.0
LKG
J
V
BAT
= 4.2 V, V
= 0 V
BUS
I
Battery Discharge Current in
High−Impedance Mode
0°C < T < 85°C, HZ_MODE = 1, V = 4.2 V
BAT
−
−
−
−
20
10
BAT
J
DISABLE = 1, 0°C < T < 85°C, V
= 4.2 V
J
BAT
CHARGER VOLTAGE REGULATION
V
OREG
Charge Voltage Range
3.5
–0.5%
–1%
−
−
−
4.4
V
Charge Voltage Accuracy
T = 25°C
+0.5%
+1%
A
T = 0 to 125°C
J
CHARGING CURRENT REGULATION
I
Output Charge Current Range
550
92
−
1450
102
mA
%
V
< V
< V
, R
= 68 mW
OCHRG
LOWV
BAT
OREG
SENSE
Charge Current Accuracy Across R
20 mV ≤ V
≤ 40 mV
97
97
SENSE
IREG
V
IREG
> 40 mV
94
100
%
WEAK BATTERY DETECTION
V
LOWV
Weak Battery Threshold Range
Weak Battery Threshold Accuracy
Weak Battery Deglitch Time
3.4
–5
−
−
−
3.7
+5
−
V
%
Rising Voltage
30
ms
LOGIC LEVELS: DISABLE, SDA, SCL, OTG
V
High−Level Input Voltage
Low−Level Input Voltage
Input Bias Current
1.05
−
−
−
−
V
V
IH
V
0.4
IL
I
IN
Input Tied to GND or V
−
0.01
1.00
mA
IN
CHARGE TERMINATION DETECTION
I
Termination Current Range
Termination Current Accuracy
50
–25
–5
−
−
−
400
+25
+5
mA
%
V
> V
– V
, R
= 68 mW
(TERM)
BAT
OREG
RCH
SENSE
[V
– V
] from 3 mV to 20 mV
CSIN
CSIN
BAT
BAT
[V
– V
] from 20 mV to 40 mV
−
Termination Current Deglitch Time
2 mV Overdrive
30
−
ms
V
1.8 V LINEAR REGULATOR
1.8 V Regulator Output
INPUT POWER SOURCE DETECTION
V
REG
I
from 0 to 2 mA
1.7
1.8
1.9
REG
V
V
VBUS Input Voltage Rising
Minimum VBUS During Charge
VBUS Validation Time
To Initiate and Pass VBUS Validation
During Charging
−
−
−
4.29
3.71
30
4.42
3.94
−
V
V
IN(MIN)1
IN(MIN)2
t
ms
VBUS_VALID
SPECIAL CHARGER (V
)
BUS
V
SP
Special Charger Setpoint Accuracy
–3
−
+3
%
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5
FAN54015
ELECTRICAL SPECIFICATIONS (Unless otherwise specified: according to the circuit of Figure 1; recommended operating
temperature range for T and T ; V = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical
J
A
BUS
values are for T = 25°C) (continued)
J
Symbol
Parameter
Conditions
Min
Typ
Max Unit
INPUT CURRENT LIMIT
I
Input Current Limit Threshold
I
I
Set to 100 mA
Set to 500 mA
88
93
98
mA
INLIM
IN
450
475
500
IN
V
REF
BIAS GENERATOR
V
REF
Bias Regulator Voltage
V
BUS
> V
or V
> V
BAT(MIN)
−
−
−
6.5
V
IN(MIN)
BAT
Short−Circuit Current Limit
20
−
mA
BATTERY RECHARGE THRESHOLD
V
RCH
Recharge Threshold
Deglitch Time
Below V
100
120
130
150
mV
ms
(OREG)
V
BAT
Falling Below V
Threshold
RCH
−
−
STAT OUTPUT
V
STAT Output Low
I
= 10 mA
−
−
−
−
0.4
1
V
STAT(OL)
STAT(OH)
STAT
I
STAT High Leakage Current
V
= 5 V
mA
STAT
BATTERY DETECTION
I
Battery Detection Current before Charge
Done (Sink Current) (Note 4)
Begins after Termination Detected and
≤ V – V
−
–0.80
262
−
mA
ms
DETECT
V
BAT
OREG
RCH
t
Battery Detection Time
DETECT
SLEEP COMPARATOR
Sleep−Mode Entry Threshold,
V
– V
V
SLP
2.3 V ≤ V
≤ V , V Falling
OREG BUS
0
0.04
30
0.10
V
BUS
BAT
BAT
t
Deglitch Time for VBUS Rising Above
by V
Rising Voltage
−
−
ms
SLP_EXIT
V
BAT
SLP
POWER SWITCHES (see Figure 2)
R
Q3 On Resistance (VBUS to PMID)
Q1 On Resistance (PMID to SW)
Q2 On Resistance (SW to GND)
I
= 500 mA
−
−
−
180
130
150
250
225
225
mW
DS(ON)
IN(LIMIT)
CHARGER PWM MODULATOR
f
Oscillator Frequency
Maximum Duty Cycle
Minimum Duty Cycle
2.7
−
3.0
−
3.3
100
−
MHz
%
SW
D
MAX
D
−
0
%
MIN
I
Synchronous to Non−Synchronous
Current Cut−Off Threshold (Note 5)
Low−Side MOSFET (Q2) Cycle−by− Cycle
Current Limit
−
140
−
mA
SYNC
BOOST MODE OPERATION (OPA_MODE = 1, HZ_MODE = 0)
V
Boost Output Voltage at VBUS
2.5 V < V
< 4.5 V, I
< 4.5 V, I
from 0 to 200 mA
from 0 to 500 mA
4.80
4.77
−
5.07
5.07
140
5.17
5.17
300
1908
−
V
BOOST
BAT
BAT
LOAD
3.0 V < V
LOAD
I
Boost Mode Quiescent Current
Q2 Peak Current Limit
PFM Mode, V
= 3.6 V, I = 0
OUT
mA
mA
V
BAT(BOOST)
BAT
I
1272
−
1590
2.42
2.58
LIMPK(BST)
UVLO
Minimum Battery Voltage for Boost
Operation
While Boost Active
BST
To Start Boost Regulator
−
2.70
VBUS LOAD RESISTANCE
VBUS to PGND Resistance
R
Normal Operation
Charger Validation
−
−
1500
100
−
−
kW
VBUS
W
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6
FAN54015
ELECTRICAL SPECIFICATIONS (Unless otherwise specified: according to the circuit of Figure 1; recommended operating
temperature range for T and T ; V = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical
J
A
BUS
values are for T = 25°C) (continued)
J
Symbol
Parameter
Conditions
Min
Typ
Max Unit
PROTECTION AND TIMERS
VBUS
VBUS Over−Voltage Shutdown
Hysteresis
V
V
Rising
Falling
6.09
−
6.29
100
2.3
6.49
−
V
mV
A
OVP
BUS
BUS
I
Q1 Cycle−by−Cycle Peak Current Limit
Battery Short−Circuit Threshold
Hysteresis
Charge Mode
−
−
LIMPK(CHG)
V
V
BAT
V
BAT
V
BAT
Rising
Falling
1.95
−
2.00
100
30
2.05
−
V
SHORT
mV
mA
°C
I
Linear Charging Current
Thermal Shutdown Threshold (Note 6)
Hysteresis (Note 6)
< V
20
−
40
−
SHORT
SHORT
T
T Rising
J
145
10
SHUTDWN
T Falling
J
−
−
T
Thermal Regulation Threshold (Note 6)
Detection Interval
Charge Current Reduction Begins
−
120
2.1
−
°C
s
CF
t
−
−
INT
t
32−Second Timer (Note 7)
Charger Enabled
Charger Disabled
15−Minute Mode
Charger Inactive
20.5
18.0
12.0
–25
25.2
25.2
13.5
−
28.0
34.0
15.0
25
s
32S
t
15−Minute Timer
min
%
15MIN
Dt
Low−Frequency Timer Accuracy
LF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Negative current is current flowing from the battery to VBUS (discharging the battery).
5. Q2 always turns on for 60 ns, then turns off if current is below I
6. Guaranteed by design; not tested in production.
.
SYNC
7. This tolerance (%) applies to all timers on the IC, including soft−start and deglitching timers.
I2C TIMING SPECIFICATIONS (Guaranteed by design)
Symbol
Parameter
SCL Clock Frequency
Conditions
Standard Mode
Fast Mode
High−Speed Mode, C ≤ 100 pF
Min
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Typ
−
Max Unit
fSCL
100
kHz
−
400
−
3400
B
High−Speed Mode, C ≤ 400 pF
−
1700
−
B
tBUF
Bus−Free Time between STOP and START
Conditions
Standard Mode
Fast Mode
4.7
1.3
4
ms
−
tHD;STA
START or Repeated START Hold Time
Standard Mode
Fast Mode
−
ms
ns
ns
ms
ms
ns
ns
ms
ns
ns
ns
ms
ns
600
160
4.7
1.3
160
320
4
−
High−Speed Mode
Standard Mode
Fast Mode
−
tLOW
tHIGH
SCL LOW Period
−
−
High−Speed Mode, C ≤ 100 pF
−
B
High−Speed Mode, C ≤ 400 pF
−
B
SCL HIGH Period
Standard Mode
Fast Mode
−
600
60
−
High−Speed Mode, C ≤ 100 pF
−
B
High−Speed Mode, C ≤ 400 pF
120
4.7
600
−
B
tSU;STA
Repeated START Setup Time
Standard Mode
Fast Mode
−
−
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FAN54015
I2C TIMING SPECIFICATIONS (Guaranteed by design) (continued)
Symbol
Parameter
Conditions
Min
−
Typ
160
250
100
10
−
Max Unit
High−Speed Mode
Standard Mode
Fast Mode
−
−
ns
ns
tSU;DAT
Data Setup Time
Data Hold Time
−
−
−
High−Speed Mode
Standard Mode
Fast Mode
−
−
tHD;DAT
tRCL
0
3.45
900
70
ms
ns
ns
ns
ns
0
−
High−Speed Mode, C ≤ 100 pF
0
−
B
High−Speed Mode, C ≤ 400 pF
0
−
150
1000
300
80
B
SCL Rise Time
SCL Fall Time
Standard Mode
Fast Mode
20 + 0.1 C
20 + 0.1 C
B
B
High−Speed Mode, C ≤ 100 pF
−
−
10
20
B
High−Speed Mode, C ≤ 400 pF
160
300
300
40
B
tFCL
Standard Mode
Fast Mode
20 + 0.1 C
20 + 0.1 C
ns
ns
ns
B
B
High−Speed Mode, C ≤ 100 pF
−
−
10
20
B
High−Speed Mode, C ≤ 400 pF
80
B
tRDA tRCL1 SDA Rise Time
Standard Mode
Fast Mode
20 + 0.1 C
20 + 0.1 C
1000
300
80
B
B
Rise Time of SCL after a Repeated START
Condition
and after ACK Bit
High−Speed Mode, C ≤ 100 pF
−
−
10
20
B
High−Speed Mode, C ≤ 400 pF
160
300
300
80
B
tFDA
SDA Fall Time
Standard Mode
Fast Mode
20 + 0.1 C
B
B
20 + 0.1 C
High−Speed Mode, C ≤ 100 pF
−
−
−
−
−
−
10
20
B
High−Speed Mode, C ≤ 400 pF
160
−
B
tSU;STO
Stop Condition Setup Time
Standard Mode
Fast Mode
4
ms
ns
ns
pF
600
160
−
−
High−Speed Mode
−
C
Capacitive Load for SDA, SCL
400
B
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8
FAN54015
TIMING DIAGRAMS
tF
tSU;STA
tBUF
SDA
SCL
tR
TSU;DAT
tHD;STO
tHIGH
tHD;DAT
tLOW
tHD;STA
tHD;STA
REPEATED
START
START
STOP
START
Figure 4. I2C Interface Timing for Fast and Slow Modes
REPEATED
START
STOP
tFDA
tRDA
tSU;DAT
SDAH
tSU;STA
tRCL1
tFCL
tHIGH
tHD;DAT
note A
tRCL
tSU;STO
SCLH
tLOW
tHD;STA
REPEATED
START
= MCS Current Source Pull−up
= RP Resistor Pull−up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 5. I2C Interface Timing for High−Speed Mode
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9
FAN54015
CHARGE MODE TYPICAL CHARACTERISTICS
(Unless otherwise specified, circuit of Figure 1, V
= 4.2 V, V = 5.0 V, and T = 25°C)
BUS A
OREG
180
160
140
120
100
80
900
800
700
600
500
400
300
200
100
−
60
5.5 VBUS
5.0 VBUS
4.5 VBUS
5.5 VBUS
5.0 VBUS
4.5 VBUS
40
20
−
2.5
3
3.5
4
4.5
2.5
3
3.5
4
4.5
Battery Voltage, V
(V)
Battery Voltage, V
(V)
BAT
BAT
Figure 6. Battery Charge Current vs. VBUS with
Figure 7. Battery Charge Current vs. VBUS with
INLIM = 500 mA
IINLIM = 100 mA
I
97%
94%
91%
88%
85%
82%
94%
92%
90%
88%
86%
84%
4.20 VBAT, 4.5 VBUS
4.20 VBAT, 5.0 VBUS
3.54 VBAT, 5.0 VBUS
3.54 VBAT, 4.5 VBUS
5.5 VBUS
5.0 VBUS
4.5 VBUS
100
300
500
700
900 1100 1300 1500
Battery Charge Current (mA)
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
Battery Voltage, V (V)
BAT
Figure 8. Charger Efficiency, No IINLIM
OCHARGE = 1450 mA
,
Figure 9. Charger Efficiency vs. VBUS
INLIM = 500 mA
,
I
I
Figure 10. Auto−Charge Startup at VBUS Plug−in,
INLIM = 100 mA, OTG = 1, VBAT = 3.4 V
Figure 11. Auto−Charge Startup at VBUS Plug−in,
I
IINLIM = 500 mA, OTG=1, VBAT = 3.4 V
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10
FAN54015
CHARGE MODE TYPICAL CHARACTERISTICS
(Unless otherwise specified, circuit of Figure 1, V
= 4.2 V, V = 5.0 V, and T = 25°C) (continued)
BUS A
OREG
Figure 12. AutoCharge Startup with 300mA Limited
Charger / Adaptor, IINLIM = 500 mA, OTG = 1,
Figure 13. Charger Startup with HZ_MODE Bit Reset,
INLIM = 500 mA, IOCHARGE = 1050 mA, OREG = 4.2 V,
BAT = 3.6 V
I
V
BAT = 3.4 V
V
Figure 14. Battery Removal / Insertion During
Charging, VBAT = 3.9 V, IOCHARGE = 1050 Ma,
No IINLIM, TE = 0
Figure 15. Battery Removal / Insertion During
Charging, VBAT = 3.9 V, IOCHARGE = 1050 mA,
No IINLIM, TE = 1
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11
FAN54015
CHARGE MODE TYPICAL CHARACTERISTICS
(Unless otherwise specified, circuit of Figure 1, V
= 4.2 V, V
= 5.0 V, and T = 25°C) (continued)
OREG
BUS
A
200
150
100
50
1.82
1.81
1.80
1.79
1.78
1.77
−30°C
+25°C
+85°C
−30°C, 5.0 VBUS
+25°C, 5.0 VBUS
+85°C, 5.0 VBUS
0
4.0
4.5
5.0
5.5
6.0
0
1
2
3
4
5
Input Voltage, V
(V)
1.8 V Regulator Load Current (mA)
BUS
Figure 16. VBUS Current in High−Impedance Mode
Figure 17. VREG 1.8 V Output Regulation
with Battery Open
Figure 18. No Battery, VBUS at Power Up
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12
FAN54015
BOOST MODE TYPICAL CHARACTERISTICS
(Unless otherwise specified, using circuit of Figure 1, V
= 3.6 V, T = 25°C)
BAT
A
100
95
90
85
80
75
100
95
90
85
3.0 VBAT
80
−10°C, 3.6 VBAT
+25°C, 3.6 VBAT
+85°C, 3.6 VBAT
3.6 VBAT
4.2 VBAT
75
0
100
200
300
400
500
0
100
200
300
400
500
V
BUS
Load Current (mA)
V
BUS
Load Current (mA)
Figure 19. Efficiency vs. VBAT
Figure 20. Efficiency Over Temperature
5.10
5.05
5.00
4.95
4.90
4.85
4.80
5.10
5.05
5.00
4.95
4.90
4.85
4.80
−10°C, 3.6 VBAT
+25°C, 3.6 VBAT
+85°C, 3.6 VBAT
3.0 VBAT
3.6 VBAT
4.2 VBAT
0
100
200
300
400
500
0
100
200
300
400
500
V
BUS
Load Current (mA)
V
BUS
Load Current (mA)
Figure 21. Output Regulation vs. VBAT
Figure 22. Output Regulation Over Temperature
250
200
150
100
50
20
15
10
−30°C
+25°C
+85°C
5
0
−30°C
+25°C
+85°C
2
2.5
3
3.5
4
4.5
5
2
2.5
3
3.5
4
4.5
5
Battery Voltage, V
(V)
Battery Voltage, V
(V)
BUS
BUS
Figure 23. Quiescent Current
Figure 24. High−Impedance Mode Battery Current
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13
FAN54015
BOOST MODE TYPICAL CHARACTERISTICS
(Unless otherwise specified, using circuit of Figure 1, V
= 3.6 V, T = 25°C)
BAT
A
Figure 27. Boost PWM Waveform
Figure 28. Boost PFM Waveform
30
25
20
15
10
5
30
25
20
15
10
5
2.7 VBAT
3.6 VBAT
4.2 VBAT
4.5 VBAT
−30°C, 3.6 VBAT
+25°C, 3.6 VBAT
+85°C, 3.6 VBAT
0
0
0
100
200
300
400
500
0
100
200
300
400
500
V
BUS
Load Current (mA)
V
BUS
Load Current (mA)
Figure 25. Output Ripple vs. VBAT
Figure 26. Output Ripple vs. Temperature
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14
FAN54015
BOOST MODE TYPICAL CHARACTERISTICS
(Unless otherwise specified, using circuit of Figure 1, V
= 3.6 V, T = 25°C)
BAT
A
VBUS
IL
IBAT
Figure 29. Startup, 3.6 VBAT, 44 W Load, Additional
10 mF, X5R Across VBUS
Figure 30. VBUS Fault Response, 3.6 VBAT
Figure 31. Load Transient, 5 − 155 − 5 mA,
Figure 32. Load Transient, 5 − 255 − 5 mA,
tR = tF = 100 ns
tR = tF = 100 ns
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15
FAN54015
Battery Charging Curve
If the battery voltage is below V
source pre−charges the battery until V
The PWM charging circuit is then started and the battery is
charged with a constant current if sufficient input power is
available. The current slew rate is limited to prevent
overshoot.
The FAN54015 is designed to work with a current−limited
input source at VBUS. During the current regulation phase
CIRCUIT DESCRIPTION / OVERVIEW
When charging batteries with a current−limited input
source, such as USB, a switching charger’s high efficiency
over a wide range of output voltages minimizes charging
time.
FAN54015 combines a highly integrated synchronous
buck regulator for charging with a synchronous boost
regulator, which can supply 5 V to USB On−The−Go (OTG)
peripherals. The regulator employs synchronous
rectification for both the charger and boost regulators to
maintain high efficiency over a wide range of battery
voltages and charge states.
, a linear current
SHORT
reaches V
.
BAT
SHORT
of charging, I
or the programmed charging current
INLIM
limits the amount of current available to charge the battery
and power the system. The effect of I
be seen in Figure 34.
on I
can
INLIM
CHARGE
The FAN54015 has three operating modes:
1. Charge Mode:
VOREG
Charges a single−cell Li−ion or Li−polymer
battery.
ICHARGE
2. Boost Mode:
VBAT
Provides 5 V power to USB−OTG with an
integrated synchronous rectification boost
regulator using the battery as input.
ITERM
VSHORT
ISHORT
3. High−Impedance Mode:
Both the boost and charging circuits are OFF in
this mode. Current flow from VBUS to the battery
or from the battery to VBUS is blocked in this
mode. This mode consumes very little current
from VBUS or the battery.
PRE−
CHARGE
CONSTANT CURRENT CONSTANT
(CC) VOLTAGE (CV)
NOTE: Default settings are denoted by bold typeface.
Figure 33. Charge Curve, ICHARGE Not Limited by IINLIM
Charge Mode
VOREG
In Charge Mode, FAN54015 employs four regulation
loops:
1. Input Current: Limits the amount of current drawn
from VBUS. This current is sensed internally and
ICHARGE
VBAT
2
can be programmed through the I C interface.
2. Charging Current: Limits the maximum charging
current. This current is sensed using an external
ITERM
VSHORT
ISHORT
R
SENSE
resistor.
3. Charge Voltage: The regulator is restricted from
exceeding this voltage. As the internal battery
voltage rises, the battery’s internal impedance and
PRE−
CHARGE
CURRENT
REGULATION
VOLTAGE
REGULATION
R
SENSE
work in conjunction with the charge
voltage regulation to decrease the amount of
current flowing to the battery. Battery charging is
Figure 34. Charge Curve, IINLIM Limits ICHARGE
completed when the voltage across R
drops
SENSE
Assuming that V
charged “float” voltage, the current that the battery accepts
with the PWM regulator limiting its output (sensed at
is programmed to the cell’s fully
OREG
below the I
threshold.
TERM
4. Temperature: If the IC’s junction temperature
reaches 120°C, charge current is reduced until the
IC’s temperature stabilizes at 120°C.
VBAT) to V
declines, and the charger enters the
OREG
voltage regulation phase of charging. When the current
declines to the programmed I value, the charge cycle
is complete. Charge current termination can be disabled by
resetting the TE bit (REG1[3]).
The charger output or “float” voltage can be programmed
by the OREG bits from 3.5 V to 4.44 V in 20 mV increments,
as shown in Table 3.
5. An additional loop limits the amount of drop on
TERM
VBUS to a programmable voltage (V ) to
SP
accommodate “special chargers” that limit current
to a lower current than might be available from a
“normal” USB wall charger.
www.onsemi.com
16
FAN54015
Table 3. OREG BITS (OREG[7:2]) VS. CHARGER VOUT
(VOREG) FLOAT VOLTAGE
A new charge cycle begins when one of the following
occurs:
• The battery voltage falls below V
Decimal
0
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOREG Decimal
Hex
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
VOREG
4.14
4.16
4.18
4.20
4.22
4.24
4.26
4.28
4.30
4.32
4.34
4.36
4.38
4.40
4.42
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
− V
OREG
RCH
3.50
3.52
3.54
3.56
3.58
3.60
3.62
3.64
3.66
3.68
3.70
3.72
3.74
3.76
3.78
3.80
3.82
3.84
3.86
3.88
3.90
3.92
3.94
3.96
3.98
4.00
4.02
4.04
4.06
4.08
4.10
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
• VBUS Power on Reset (POR) clears and the battery
1
voltage is below the weak battery threshold (V
).
LOWV
2
• CE or HZ_MODE is reset through I C write to
2
CONTROL1 (R1) register.
3
4
Charge Current Limit (IOCHARGE
)
5
Table 5. IOCHARGE (REG4 [6:4]) CURRENT AS
FUNCTION OF IOCHARGE BITS AND RSENSE RESISTOR
VALUES
6
7
8
I
(mA)
100 mW
374
OCHARGE
V
RSENSE
(mV)
9
68 mW
550
DEC
BIN
000
001
010
011
100
101
110
111
HEX
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0
1
2
3
4
5
6
7
37.4
44.2
51.0
57.8
71.4
78.2
91.8
98.6
650
442
750
510
850
578
1050
1150
1350
1450
714
782
918
986
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
Termination Current Limit
Current charge termination is enabled when TE
(REG1[3]) = 1. Typical termination current values are given
in Table 6.
Table 6. ITERM CURRENT AS FUNCTION OF ITERM
BITS (REG4[2:0]) AND RSENSE RESISTOR VALUES
I
(mA)
TERM
V
RSENSE
(mV)
68 mW
49
100 mW
I
TERM
0
3.3
6.6
33
66
1
2
3
4
5
6
7
97
9.9
146
194
243
291
340
388
99
13.2
16.5
19.8
23.1
26.4
132
165
198
231
264
The following charging parameters can be programmed
2
by the host through I C:
Table 4. PROGRAMMABLE CHARGING PARAMETERS
Parameter
Name
Register
REG2[7:2]
REG4[6:4]
REG1[7:6]
REG4[2:0]
REG1[5:4]
When the charge current falls below I
, PWM
TERM
charging stops and the STAT bits change to READY (00) for
about 500 ms while the IC determines whether the battery
and charging source are still connected. STAT then changes
to CHARGE DONE (10), provided the battery and charger
are still connected.
Output Voltage Regulation
Battery Charging Current Limit
Input Current Limit
V
OREG
I
OCHRG
I
INLIM
Charge Termination Limit
Weak Battery Voltage
I
TERM
V
LOWV
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17
FAN54015
PWM Controller in Charge Mode
USB−Friendly Boot Sequence
The IC uses a current−mode PWM controller to regulate
the output voltage and battery charge currents. The
synchronous rectifier (Q2) has a current limit that which off
the FET when the current is negative by more than 140 mA
peak. This prevents current flow from the battery.
At VBUS POR, when the battery voltage is above the
weak battery threshold (V
accordance with its I C register settings. If V
), the IC operates in
LOWV
2
< V
,
BAT
LOWV
the IC sets all registers to their default values and enables the
charger using an input current limit controlled by the OTG
pin (100 mA if OTG is LOW and 500 mA if OTG is HIGH).
This feature can revive a battery whose voltage is too low to
ensure reliable host operation. Charging continues in the
absence of host communication even after the battery has
Safety Timer
Section references Figure 39.
At the beginning of charging, the IC starts a 15−minute
timer (t
). When this times out, charging is terminated.
15MIN
reached V
, whose default value is 3.54 V, and the
OREG
2
Writing to any register through I C stops and resets the
charger remains active until t
times out. Once the host
15MIN
t
timer, which in turn starts a 32−second timer (t ).
15MIN
32S
processor begins writing to the IC, charging parameters are
Setting the TMR_RST bit (REG0[7]) resets the t
timer.
32S
set by the host, which must continually reset the t timer
32S
If the t
timer times out; charging is terminated, the
32S
to continue charging using the programmed charging
registers are set to their default values, and charging resumes
using the default values with the t timer running.
parameters. If t .times out, the register defaults are loaded,
32S
15MIN
the FAULT bits are set to 110, STAT is pulsed HIGH, and
charging continues with default charge parameters.
Normal charging is controlled by the host with the t
32S
timer running to ensure that the host is alive. Charging with
the t timer running is used for charging that is
Input Current Limiting
15MIN
unattended by the host. If the t
turns off the charger, sets the CE bit, and indicates a timer
fault (110) on the FAULT bits (REG0[2:0]). This sequence
timer expires; the IC
To minimize charging time without overloading VBUS
current limitations, the IC’s input current limit can be
15MIN
programmed by the I
bits (REG1[7:6]).
INLIM
prevents overcharge if the host fails to reset the t timer.
32S
Table 7. INPUT CURRENT LIMIT
VBUS POR / Non−Compliant Charger Rejection
I
REG1[7:6]
Input Current Limit
100 mA
INLIM
When the IC detects that V
has risen above V
BUS
IN(MIN)1
(4.4 V), the IC applies a 100 W load from VBUS to GND. To
clear the VBUS POR (Power−On−Reset) and begin
00
01
10
11
500 mA
charging, VBUS must remain above V
and below
IN(MIN)1
800 mA
VBUS
for t
(30 ms) before the IC initiates
OVP
VBUS_VALID
No limit
charging. The VBUS validation sequence always occurs
before charging is initiated or re−initiated (for example, after
The OTG pin establishes the input current limit when
is running.
a VBUS OVP fault or a V
recharge initiation).
RCH
t
t
ensures that unfiltered 50 / 60 Hz chargers
15MIN
VBUS_VALID
and other non−compliant chargers are rejected.
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18
FAN54015
FLOW CHARTS
VBUS POR
YES
HZ State
HZ, CEor
DISABLE Pin
set?
VBAT > VLOWV
YES
Charge
Configuration
State
NO
NO
NO
HZ, CEor
DISABLE Pin
set?
T32Sec
Armed?
T15Min Timer?
NO
NO
YES
YES
YES
HZ, CEor
DISABLE Pin
set?
YES
HZ State
T32Sec
Armed?
NO
YES
Charge State
Reset all registers
Start T15MIN
NO
Figure 35. Charger VBUS PO
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19
FAN54015
FLOW CHARTS (continued)
CHARGE STATE
Disable Charging
NO
Indicate
VBUS Fault
Enable ISHORT
,
Reset Safety reg
YES
VBAT < VSHORT
VBUS OK?
YES
NO
Indicate Charging
NO
PWM Charging
T15MIN
VBUS OK?
YES
Indicate Charging
Timeout?
NO
YES
Indicate timer fault
Set CE
Charge
Configuration
State
Disable Charging
T15MIN
Timeout?
YES
Indicate
VBUS Fault
NO
NO
HIGHZ mode
IOUT < ITERM
Termination enabled
BAT > VOREG – VRCH
Indicate Charge
Complete
YES
VBAT < VOREG – VRCH
NO
V
Reset Safety reg
Delay tINT
NO
YES
Battery Removed
Stop Charging
YES
VBAT < VOREG – VRCH
Reset charge
parameters
Enable IDET for TDETECT
Figure 36. Charge Mode
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20
FAN54015
FLOW CHARTS (continued)
HZ State
Charge
Configuration
State
DISABLE
PIN
Reset T15min
if running
HIGH
LOW
T32Sec
ARMED AND
CE= 0?
Stop T32Sec
YES
Charge State
RUN
T32Sec
NO
NO
Has T15Min
and CE= 0
START T15Min
NO
HZ or CE set?
YES
VBAT > VLOWV?
YES
YES
HIGH
NO
VBAT < VOREG
for 262 ms?
NO
YES
DISABLE
PIN
LOW
Charge State
Figure 37. Charge Configuration
Figure 38. HZ−State
Charge Start
Start T15MIN
Reset Registers
YES
T32SEC
NO
Expired?
Start T32SEC
YES
NO
Stop T15MIN
T15MIN
I2C Write
received?
T15MIN
Continue
Charging
YES
NO
NO
Active?
Expired?
Timer Fault :
Set CE
YES
Figure 39. Timer Flow Chart
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21
FAN54015
Special Charger
Table 9. ISAFE (IOCHARGE LIMIT) AS FUNCTION OF
ISAFE BITS (REG6[6:4])
The FAN54015 has additional functionality to limit input
current in case a current−limited “special charger” is
supplying VBUS. These slowly increase the charging
current until either:
ISAFE (REG6[6:4])
I
(mA)
100 mW
374
SAFE
68 mW
550
• I
or I
is reached
DEC
BIN
000
001
010
011
100
101
110
111
HEX
00
01
02
03
04
05
06
07
V
(mV)
INLIM
OCHARGE
RSENSE
0
1
2
3
4
5
6
7
37.4
or
• V
= V .
SP
44.2
51.0
57.8
71.4
78.2
91.8
98.6
650
442
BUS
If V
collapses to V when the current is ramping up,
BUS
SP
750
510
the FAN54015 charge with an input current that keeps
= V . When the V control loop is limiting the
850
578
V
BUS
SP
SP
1050
1150
1350
1450
714
charge current, the SP bit (REG5[4]) is set.
782
Table 8. VSP AS FUNCTION OF SP BITS (REG5[2:0])
SP (REG5[2:0])
918
986
DEC
BIN
000
001
010
011
HEX
00
V
SP
0
1
2
3
4.213
4.293
4.373
4.453
Table 10. VSAFE (VOREG LIMIT) AS FUNCTION OF
VSAFE BITS (REG6[3:0])
01
VSAFE (REG6[3:0])
02
VOREG
03
Max.
4.20
4.22
4.24
4.26
4.28
4.30
4.32
4.34
4.36
4.38
4.40
4.42
4.44
4.44
4.44
4.44
DEC
0
BIN
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
HEX
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
Max. OREG (REG2[7:2])
100011
4
5
6
7
100
101
110
111
04
05
06
07
4.533
4.613
4.693
4.773
1
100100
2
100101
3
100110
4
100111
Safety Settings
FAN54015 contain a SAFETY register (REG6) that
prevents the values in OREG (REG2[7:2]) and IOCHARGE
(REG4[6:4]) from exceeding the values of the VSAFE and
ISAFE values.
5
101000
6
101001
7
101010
After V
exceeds V
, the SAFETY register is
8
101011
BAT
SHORT
loaded with its default value and may be written only before
any other register is written. The entire desired Safety
register value should be written twice to ensure the register
bits are set. After writing to any other register, the SAFETY
register is locked until V
The ISAFE (REG6[6:4]) and VSAFE (REG6[3:0])
registers establish values that limit the maximum values of
9
101100
10
11
12
13
14
15
101101
101110
falls below V
.
BAT
SHORT
101111
110000
110001
I
and V
used by the control logic. If the host
OCHARGE
OREG
attempts to write a value higher than VSAFE or ISAFE to
OREG or IOCHARGE, respectively; the VSAFE, ISAFE
value appears as the OREG, IOCHARGE register value,
respectively.
110010
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22
FAN54015
Thermal Regulation and Protection
When the IC’s junction temperature reaches T (about
120°C), the charger reduces its output current to 550 mA to
prevent overheating. If the temperature increases beyond
this condition, V
a high slew rate. Achieving this slew rate requires a 0 W short
to the USB cable less than 10 cm from the connector.
must be driven from 5 V to GND with
BUS
CF
Charge Mode Battery Detection & Protection
T
; charging is suspended, the FAULT bits are set
SHUTDOWN
to 101, and STAT is pulsed HIGH. In Suspend Mode, all
timers stop and the state of the IC’s logic is preserved.
Charging resumes at programmed current after the die cools
to about 120°C.
VBAT Over−Voltage Protection
The OREG voltage regulation loop prevents V
overshooting the OREG voltage by more than 50 mV when
the battery is removed. When the PWM charger runs with no
battery, the TE bit is not set and a battery is inserted that is
charged to a voltage higher than V
If no further pulses occur for 30 ms, the IC sets the FAULT
bits to 100, sets the STAT bits to 11, and pulses the STAT pin.
from
BAT
Additional q
data points, measured using the
JA
FAN54015 evaluation board, are given in Table 11
; PWM pulses stop.
OREG
(measured with T = 25°C). Note that as power dissipation
A
increases, the effective q decreases due to the larger
JA
difference between the die temperature and ambient.
Battery Detection During Charging
The IC can detect the presence, absence, or removal of a
battery if the termination bit (TE) is set. During normal
Table 11. EVALUATION BOARD MEASURED qJA
Power (W)
0.504
q
JA
charging, once V
is close to V
and the termination
BAT
OREG
charge current is detected, the IC terminates charging and
sets the STAT bits to 10. It then turns on a discharge current,
54°C/W
50°C/W
46°C/W
0.844
I
, for t
. If V
is still above V
– V
,
DETECT
DETECT
BAT
OREG
RCH
1.506
the battery is present and the IC sets the FAULT bits to 000.
If V is below V – V , the battery is absent and
BAT
OREG
RCH
Charge Mode Input Supply Protection
the IC:
1. Sets the registers to their default values.
2. Sets the FAULT bits to 111.
3. Resumes charging with default values after t
Sleep Mode
When V
falls below V
+ V , and V
is above
BUS
BAT
SLP
BUS
.
INT
V
the IC enters Sleep Mode to prevent the battery
IN(MIN),
from draining into VBUS. During Sleep Mode, reverse
current is disabled by body switching Q1.
Battery Short−Circuit Protection
If the battery voltage is below the short−circuit threshold
(V ); a linear current source, I , supplies V
SHORT
SHORT
BAT
Input Supply Low−Voltage Detection
The IC continuously monitors VBUS during charging. If
until V
> V
.
BAT
SHORT
V
falls below V
1. Terminates charging
2. Pulses the STAT pin, sets the STAT bits to 11, and
sets the FAULT bits to 011.
, the IC:
BUS
IN(MIN)
System Operation with No Battery
The FAN54015 continues charging after VBUS POR with
the default parameters, regulating the V line to 3.54 V
until the host processor issues commands or the 15−minute
timer expires. In this way, the FAN54015 can start the
system without a battery.
The FAN54015 soft−start function can interfere with the
system supply with battery absent. The soft−start activates
BAT
If V
recovers above the V
rising threshold after
BUS
IN(MIN)
time t
(about two seconds), the charging process is
INT
repeated. This function prevents the USB power bus from
collapsing or oscillating when the IC is connected to a
suspended USB port or a low−current−capable OTG device.
whenever V
, I
, or I
are set from a lower
IN
is set to 11 (no limit).
OREG INLIM
OCHARGE
Input Over−Voltage Detection
to higher value. During soft−start, the I limit drops to
When the V
exceeds VBUS , the IC:
100 mA for about 1 ms unless I
BUS
OVP
INLIM
1. Turns off Q3
2. Suspends charging
3. Sets the FAULT bits to 001, sets the STAT bits to
11, and pulses the STAT pin.
This could cause the system processor to fail to start. To
avoid this behavior, use the following sequence.
1. Set the OTG pin HIGH. When VBUS is plugged
in, I
is set to 500 mA until the system
INLIM
When V
falls about 150 mV below VBUS , the
processor powers up and can set parameters
BUS
OVP
2
fault is cleared and charging resumes after V
is
through I C.
BUS
revalidated (see VBUS POR / Non−Compliant Charger
Rejection).
2. Program the Safety Register.
3. Set I
to 11 (no limit).
INLIM
4. Set OREG to the desired value (typically 4.18).
5. Reset the IO_LEVEL bit, then set IOCHARGE.
VBUS Short While Charging
If VBUS is shorted with a very low impedance while the
6. Set I
to 500 mA if a USB source is
INLIM
IC is charging with I
= 100 mA, the IC may not meet
INLIMIT
connected.
datasheet specifications until power is removed. To trigger
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23
FAN54015
During the initial system startup, while the charger IC is
being programmed, the system current is limited to 500 mA
for 1 ms during steps 4 and 5. This is the value of the
Table 14. DISABLE PIN AND CE BIT FUNCTIONALITY
Charging
ENABLE
DISABLE
DISABLE
DISABLE
DISABLE Pin
CE
0
HZ_MODE
0
X
X
1
0
X
1
soft−start ICHARGE current used when I
is set to No
INLIM
Limit.
1
If the system is powered up without a battery present, the
CV bit should be set. When a battery is inserted, the CV bit
is cleared.
X
X
X
Charger Status / Fault Status
The STAT pin indicates the operating condition of the IC
and provides a fault indicator for interrupt driven systems.
Raising the DISABLE pin stops t from advancing, but
32S
does not reset it. If the DISABLE pin is raised during t
15MIN
charging, the t
timer is reset.
15MIN
Operational Mode Control
Table 12. STAT PIN FUNCTION
OPA_MODE (REG1[0]) and the HZ_MODE (REG1[1])
bits in conjunction with the FAULT state define the
operational mode of the charger.
EN_STAT
Charge State
X
STAT Pin
OPEN
OPEN
LOW
0
X
1
Normal Conditions
Charging
Table 15. OPERATION MODE CONTROL
HZ_MODE
OPA_MODE
FAULT
Operation Mode
Charge
X
Fault (Charging or Boost) 128 ms Pulse, then OPEN
0
0
0
1
0
X
1
0
1
0
X
The FAULT bits (R0[2:0]) indicate the type of fault in
Charge Mode (see Table 13).
Charge Configure
Boost
X
High Impedance
Table 13. FAULT STATUS BITS DURING CHARGE
MODE
The IC resets the OPA_MODE bit whenever the boost is
deactivated, whether due to a fault or being disabled by
setting the HZ_MODE bit.
Fault Bit
B2
0
B1
0
B0
0
Fault Description
Normal (No Fault)
VBUS OVP
BOOST MODE
0
0
1
Boost Mode can be enabled if the IC is in 32−Second
Mode with the OTG pin and OPA_MODE bits as indicated
in Table 16. The OTG pin ACTIVE state is 1 if OTG_PL = 1
and 0 when OTG_PL = 0.
If boost is active using the OTG pin, Boost Mode is
initiated even if the HZ_MODE = 1. The HZ_MODE bit
overrides the OPA_MODE bit.
0
1
0
Sleep Mode
0
1
1
Poor Input Source
Battery OVP
1
0
0
1
0
1
Thermal Shutdown
Timer Fault
1
1
0
1
1
1
No Battery
Table 16. ENABLING BOOST
OTG_EN OTG Pin HZ_ MODE OPA_MODE BOOST
Charge Mode Control Bits
Setting either HZ_MODE or CE through I C disables the
charger and puts the IC into High−Impedance Mode and
2
1
X
X
0
1
0
ACTIVE
X
X
0
X
1
1
0
X
1
0
X
1
0
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
resets t . If V
< V
while in High−Impedance
32S
BAT
LOWV
ACTIVE
X
Mode, t
begins running and, when it overflows, all
32S
registers (except SAFETY) reset, which enables t
charging on versions with the 15−minute timer.
15MIN
ACTIVE
ACTIVE
When t
overflows, the IC sets the CE bit and the IC
15MIN
enters High−Impedance Mode. If CE was set by t
15MIN
overflow, a new charge cycle can only be initiated through
I C or VBUS POR.
Setting the RESET bit clears all registers. If HZ_MODE
or CE bits were set when the RESET bit is set, these bits are
To remain in Boost Mode, the TMR_RST must be set by
the host before the t timer times out. If t times out in
Boost Mode; the IC resets all registers, pulses the STAT pin,
sets the FAULT bits to 110, and resets the BOOST bit. VBUS
POR or reading R0 clears the fault condition.
2
32S
32S
also cleared, but the t
timer is not started, and the IC
32S
remains in High−Impedance Mode.
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24
FAN54015
Boost PWM Control
Table 17. Boost PWM Operating States
The IC uses a minimum on−time and computed minimum
off− time to regulate VBUS. The regulator achieves
excellent transient response by employing current−mode
modulation. This technique causes the regulator to exhibit a
load line.
Mode
LIN
Description
Linear Startup
Invoked When
V
> V
BUS
BAT
BUS
SS
Boost Soft−Start
Boost Operating Mode
V
< V
BST
BST
V
BAT
> UVLO
Completed
and SS
BST
During PWM Mode, the output voltage drops slightly as
the input current rises. With a constant V , this appears as
BAT
a constant output resistance.
Startup
The “droop” caused by the output resistance when a load
is applied allows the regulator to respond smoothly to load
transients with no undershoot from the load line. This can be
seen in Figure 31 and Figure 40.
When the boost regulator is shut down, current flow is
prevented from V to V , as well as reverse flow from
BAT
BUS
V
BUS
to V
.
BAT
LIN State
350
325
300
275
250
225
200
When EN rises, if V
attempts to bring PMID within 400 mV of V
internal 450 mA current source from VBAT (LIN State). If
PMID has not achieved V
FAULT state is initiated.
> UVLO , the regulator first
BAT BST
using an
BAT
– 400 mV after 560 ms, a
BAT
SS State
When PMID > V
– 400 mV, the boost regulator begins
BAT
switching with a reduced peak current limit of about 50% of
its normal current limit. The output slews up until V is
within 5% of its setpoint; at which time, the regulation loop
is closed and the current limit is set to 100%.
BUS
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
Battery Voltage, V
If the output fails to achieve 95% of its setpoint (V
)
BAT
BST
within 128 ms, the current limit is increased to 100%. If the
output fails to achieve 95% of its setpoint after this second
384 ms period, a fault state is initiated.
Figure 40. Output Resistance (ROUT
)
V
BUS
as a function of I
can be computed when the
LOAD
regulator is in PWM Mode (continuous conduction) as:
BST State
VOUT + 5.07 * ROUT @ ILOAD
This is the normal operating mode of the regulator. The
regulator uses a minimum t
scheme. The minimum t
which keeps the regulator’s switching frequency reasonably
constant in CCM. t is proportional to V and is a
(eq. 1)
− minimum t modulation
OFF
ON
At V
At V
= 3.3 V, and I
= 200 mA, V
would drop to:
BAT
LOAD
BUS
is propotional to V / V
,
OFF
IN
OUT
VOUT + 5.07 * 0.26 @ 0.2 + 5.018 V
(eq. 2)
would drop to:
(eq. 3)
ON(MIN)
BAT
= 2.7 V, and I
= 200 mA, V
BUS
BAT
LOAD
higher value if the inductor current reached 0 before
in the prior cycle.
VOUT + 5.07 * 0.327 @ 0.2 + 5.005 V
t
OFF(MIN)
To ensure the VBUS does not pump significantly above
the regulation point, the boost switch remains off as long as
FB > V
PFM Mode
.
REF
If V
> VREF
(nominally 5.07 V) when the
BOOST
BUS
minimum off−time has ended, the regulator enters PFM
Mode. Boost pulses are inhibited until V < VREF
Boost Faults
If a BOOST fault occurs:
.
BOOST
BUS
The minimum on−time is increased to enable the output to
pump up sufficiently with each PFM boost pulse. Therefore
the regulator behaves like a constant on−time regulator, with
the bottom of its output voltage ripple at 5.07 V in PFM
Mode.
1. The STAT pin pulses.
2. OPA_MODE bit is reset.
3. The power stage is in High−Impedance Mode.
4. The FAULT bits (REG0[2:0]) are set per Table 18.
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25
FAN54015
0
0
VBUS
Restart After Boost Faults
560
5200
If boost was enabled with the OPA_MODE bit and
OTG_EN = 0, Boost Mode can only be enabled through
450 mA
BATTERY
CURRENT
2
subsequent I C commands since OPA_MODE is reset on
64
boost faults. If OTG_EN = 1 and the OTG pin is still
ACTIVE (see Table 16), the boost restarts after a 5.2 ms
delay, as shown in Figure 41. If the fault condition persists,
restart is attempted every 5 ms until the fault clears or an I C
command disables the boost.
BOOST
ENABLED
2
Figure 41. Boost Response Attempting to Start into
BUS Short Circuit (Times in ms)
V
VREG Pin
Table 18. FAULT BITS DURING BOOST MODE
Fault Bit
The 1.8 V regulated output on this pin can be disabled
2
through I C by setting the DIS_VREG bit (REG5[6]).
VREG can supply up to 2 mA. This circuit, which is
B2 B1 B0
Fault Description
powered from PMID, is enabled only when PMID > V
BAT
0
0
0
0
0
1
0
1
0
Normal (no fault)
and does not drain current from the battery. During boost,
is off. It is also off when the HZ_MODE bit
V
V
> VBUS
OVP
BUS
V
REG
fails to achieve the voltage required to
(REG1[1]) = 1.
BUS
advance to the next state during soft−start or
sustained (>50 μs) current limit during the BST
state.
Monitor Register (Reg10H)
Additional status monitoring bits enable the host
processor to have more visibility into the status of the IC.
The monitor bits are real−time status indicators and are not
internally debounced or otherwise time qualified.
The state of the MONITOR register bits listed in
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
V < UVLO
BAT BST
N/A: This code does not appear.
Thermal shutdown
Timer fault; all registers reset.
N/A: This code does not appear.
High−Impedance Mode is only valid when V
is valid.
BUS
Table 19. MONITOR REGISTER BIT DEFINITIONS
STATE
0
1
BIT#
NAME
Active When
MONITOR Address 10H
< V
7
6
ITERM_CMP
VBAT_CMP
V
– V
V
CSIN
– V
> V
ITERM
Charging with TE = 1
Charging with TE = 0
Charging
CSIN
BAT
ITERM
BAT
V
– V
< 1 mV
V
– V
> 1mV
CSIN
BAT
CSIN
BAT
V
< V
VBAT > V
SHORT
BAT
SHORT
V
< V
VBAT > V
LOWV
High−Impedance Mode
Boosting
BAT
LOWV
V
BAT
< UVLO
V > UVLO
BAT BST
BST
5
4
3
LINCHG
T_120
ICHG
Linear Charging Not Enabled
Linear Charging Enabled
Charging
T < 120°C
J
T > 120°C
J
Charging Current Controlled by
Charging Current Not Controlled by
Charging
Charging
I
Control Loop
I
Control Loop
CHARGE
CHARGE
2
1
0
IBUS
VBUS_VALID
CV
I
Limiting Charging Current
Charge Current Not Limited by I
BUS
BUS
V
BUS
Not Valid
V
BUS
is Valid
V
> V
BUS BAT
Constant Current Charging
Constant Voltage Charging
Charging
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26
FAN54015
2
I C INTERFACE
The FAN54015’s serial interface is compatible with
Standard, Fast, Fast Plus, and High−Speed Mode I C−Bus
specifications. The SCL line is an input and the SDA line is
a bi−directional open−drain output; it can only pull down the
bus when active. The SDA line only pulls LOW during data
reads and signaling ACK. All data is shifted in MSB (bit 7)
first.
During a read from the FAN54015 (Figure 46, Figure 47),
the master issues a Repeated Start after sending the register
address and before resending the slave address. The
Repeated Start is a 1−to−0 transition on SDA while SCL is
HIGH, as shown in Figure 45.
2
High−Speed (HS) Mode
The protocols for High−Speed (HS), Low−Speed (LS),
and Fast−Speed (FS) Modes are identical except the bus
speed for HS Mode is 3.4 MHz. HS Mode is entered when
the bus master sends the HS master code 00001XXX after
a start condition. The master code is sent in Fast or Fast Plus
Mode (less than 1 MHz clock); slaves do not ACK this
transmission.
Slave Address
Table 20. I2C SLAVE ADDRESS BYTE
Part Type
7
6
5
4
3
2
1
0
FAN54015
1
1
0
1
0
1
0
R/W
The master then generates a repeated start condition
(Figure 45) that causes all slaves on the bus to switch to HS
Mode. The master then sends I C packets, as described
above, using the HS Mode clock rate and timing.
The bus remains in HS Mode until a stop bit (Figure 44)
is sent by the master. While in HS Mode, packets are
separated by repeated start conditions (Figure 45).
In hex notation, the slave address assumes a 0 LSB. The
hex slave address for the FAN54015 is D4H and is D6H for
all other parts in the family.
2
Bus Timing
As shown in Figure 42, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow ample time for the data to set up before the
tSU;STA tHD;STA
Slave Releases
ACK(0) or
NACK(1)
SLADDR
MS Bit
SDA
SCL
Data change allowed
SDA
TH
Figure 45. Repeated Start Timing
TSU
SCL
Read and Write Transactions
The figures below outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
Figure 42. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 43.
defined as Master Drives Bus and
Slave Drives Bus
.
All addresses and data are MSB first.
Table 21. BIT DEFINITIONS FOR FIGURE 46,
FIGURE 47, AND FIGURE 48
THD;STA
Slave Address
SDA
MS Bit
Symbol
Definition
START, see Figure 43
S
A
SCL
ACK. The slave drives SDA to 0 to acknowledge the
preceding packet.
Figure 43. Start Bit
A
NACK. The slave sends a 1 to NACK the preceding
packet.
A transaction ends with a STOP condition, which is
defined as SDA transitioning from 0 to 1 with SCL HIGH,
as shown in Figure 44.
R
P
Repeated START, see Figure 45
STOP, see Figure 44. Figure 44
Slave Releases
Master Drives
tHD;STO
ACK(0) or
NACK(1)
SDA
SCL
Figure 44. Stop Bit
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27
FAN54015
7 bits
8 bits
8 bits
Data
0
0
0
S
Slave Address
0
A
Reg Addr
A
A
P
Figure 46. Write Transaction
7 bits
Slave Address
8 bits
Reg Addr
7 bits
8 bits
Data
0
0
0
1
S
0
A
A
R
Slave Address
1
A
A
P
Figure 47. Read Transaction
REGISTER DESCRIPTIONS
The nine FAN54015 user−accessible registers are defined
in Table 22.
Table 22. I2C REGISTER ADDRESS
Register
Address Bits
Name
CONTROL0
CONTROL1
OREG
REG#
7
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
4
3
0
0
0
0
0
0
0
0
2
0
0
0
0
1
1
1
0
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
2
03 or 3BH
IC_INFO
IBAT
4
5
SP_CHARGER
SAFETY
6
MONITOR
10h
Table 23. REGISTER BIT DEFINITIONS
(This table defines the operation of each register bit for all IC versions. Default values are in bold text.)
Bit
Name
Value
Type
Description
CONTROL0
Register Address: 00
Default Value = X1XX 0XXX
7
6
TMR_RST
OTG
W
R
Writing a 1 resets the t
timer; writing a 0 has no effect
1
32S
Returns the OTG pin level (1 = HIGH)
EN_STAT
STAT
0
1
R/W Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate faults
Enables STAT pin LOW when IC is charging
5:4
00
01
10
11
0
R
Ready
Charge in progress
Charge done
Fault
3
BOOST
FAULT
R
IC is not in Boost Mode
1
IC is in Boost Mode
2:0
R
Fault status bits: for Charge Mode, see Table 13; for Boost Mode, see Table 18
CONTROL1
Register Address: 01
Default Value = 0011 0000 (30h)
7:6
IINLIM
VLOWV
R/W Input current limit, see Table 7
5:4
00
01
10
11
R/W 3.4 V
3.5 V
Weak battery voltage threshold
3.6 V
3.7 V
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28
FAN54015
Table 23. REGISTER BIT DEFINITIONS
(This table defines the operation of each register bit for all IC versions. Default values are in bold text.) (continued)
Bit
Name
TE
Value
Type
Description
CONTROL1
Register Address: 01
Default Value = 0011 0000 (30h)
3
0
1
0
1
0
1
0
1
R/W Disable charge current termination
Enable charge current termination
R/W Charger enabled
Charger disabled
2
CE
1
0
HZ_MODE
R/W Not High−Impedance Mode
High−Impedance Mode
See Table 16
OPA_MODE
R/W Charge Mode
Boost Mode
OREG
Register Address: 02
Default Value = 0000 1010 (0Ah)
7:2
OREG
R/W Charger output “float” voltage; programmable from 3.5 to 4.44V in 20mV increments;
defaults to 000010 (3.54 V), see Table 3
1
0
OTG_PL
0
1
0
1
R/W OTG pin active LOW
OTG pin active HIGH
R/W Disables OTG pin
Enables OTG pin
OTG_EN
IC_INFO
7:5
Register Address: 03
Default Value = 10010100 (94h)
Vendor Code
PN
100
00
1
R
R
R
Identifies ON Semiconductor as the IC supplier
Part number bits, see the Ordering Info on page 31
4:2
1:0
REV
IC Revision, revision 1.X, where X is the decimal of these three bits
IBAT
7
Register Address: 04
Default Value = 1000 1001 (89h)
RESET
W
Writing a 1 resets charge parameters, except the Safety register (Reg6), to their defaults:
writing a 0 has no effect; read returns 1
6:4
3
IOCHARGE
Reserved
ITERM
Table 5
1
R/W Programs the maximum charge current, see Table 5
Unused
R/W Sets the current used for charging termination, see Table 6
R
2:0
Table 6
SP_CHARGER
Register Address: 05
Default Value = 001X X100
7
6
Reserved
0
0
1
0
1
R
Unused
DIS_VREG
IO_LEVEL
R/W 1.8 V regulator is ON
1.8 V regulator is OFF
5
R/W Output current is controlled by IOCHARGE bits
Voltage across R
for output current control is set to 34 mV (500 mA for
SENSE
R
SENSE
= 68 mW and 340 mA for 100 mW)
4
3
SP
EN_LEVEL
VSP
0
R
R
Special charger is not active (V
is able to stay above V
)
BUS
SP
1
Special charger has been detected and V
DISABLE pin is LOW
is being regulated to V
BUS SP
0
1
DISABLE pin is HIGH
2:0
SAFETY
7
Table 8
R/W Special charger input regulation voltage, see Table 8
Register Address: 06
Default Value = 0100 0000 (40h)
Reserved
ISAFE
0
R
Bit disabled and always returns 0 when read back
6:4
Table 9
Table 10
R/W Sets the maximum I value used by the control circuit, see Table 9
OCHARGE
3:0
VSAFE
R/W Sets the maximum V
used by the control circuit, see Table 10
OREG
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29
FAN54015
Table 23. REGISTER BIT DEFINITIONS
(This table defines the operation of each register bit for all IC versions. Default values are in bold text.) (continued)
Bit
Name
Value
Type
Description
MONITOR
Register Address: 10h (16)
See Table 19
7
6
5
4
ITERM_CMP
VBAT_CMP
LINCHG
See
Table 19
R
R
R
R
ITERM comparator output, 1 when VRSENSE > ITERM reference
Output of VBAT comparator
30 mA linear charger ON
T_120
Thermal regulation comparator; when = 1 and T_145 = 0, the charge current is limited to
22.1 mV across R
SENSE
3
2
1
0
ICHG
IBUS
R
R
R
R
0 indicates the ICHARGE loop is controlling the battery charge current
0 indicates the IBUS (input current) loop is controlling the battery charge current
1 indicates VBUS has passed validation and is capable of charging
VBUS_VALID
CV
1 indicates the constant−voltage loop (OREG) is controlling the charger and all current
limiting loops have released
PCB LAYOUT RECOMMENDATIONS
PMID, and VBUS pins. All power and ground pins must be
Bypass capacitors should be placed as close to the IC as
possible. In particular, the total loop length for CMID should
be minimized to reduce overshoot and ringing on the SW,
routed to their bypass capacitors, using top copper whenever
possible. Copper area connecting to the IC should be
maximized to improve thermal performance if possible.
Figure 48. PCB Layout Recommendations
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30
FAN54015
ORDERING INFORMATION
Temperature
Range
PN Bits:
IC_INFO[4:2]
†
Part Number
Package
Shipping
FAN54015UCX
−40 to 85°C
20−Bump, Wafer−Level Chip−Scale
Package (WLCSP), 0.4 mm Pitch,
Estimated Size: 1.96 x 1.87 mm
(Pb−Free)
101
3000 / Tape & Reel
3000 / Tape & Reel
FAN54015BUCX (Note 8)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
8. FAN54015BUCX includes backside lamination.
2
ON Semiconductor is licensed by the Philips Corporation to carry the I C bus protocol.
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31
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP20 1.96x1.87x0.586
CASE 567SL
ISSUE O
DATE 30 NOV 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON16608G
WLCSP20 1.96x1.87x0.586
PAGE 1 OF 1
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