FAN54046UCX-T_技术文档

FAN54040 — FAN54047

USB-OTG, 1.55 A, Li-Ion Switching Charger with Power

Path and 2.3 A Production Test Support

Description

Features

The FAN5404X family includes I²C controlled 1.55 A USB-

.

Fully Integrated, High-Efficiency Charger for Single-Cell

Li-Ion and Li-Polymer Battery Packs

compliant sw itch-mode chargers w ith pow er path operation

and USB OTG boost operation. Integrated w ith the charger,

the IC supports production test mode, w hich provides 4.2 V

at up to 2.3 A to the system.

.

Pow er Path Circuit Ensures Fast System Startup w ith a

Dead Battery w hen VBUS is Connected

.

1.55 A Maximum Charge Current

Float Voltage Accuracy:

To facilitate fast system startup, the IC includes a pow er

path circuit, w hich disconnects the battery from the system

rail, ensuring that the system can pow er up quickly follow ing

a VBUS connection. The pow er path circuit ensures that the

system rail stays up w hen the charger is plugged in, even if

the battery is dead or shorted.

-

±0.5% at 25°C

±1% from 0 to 125°C

.

±5% Input and Charge Current Regulation Accuracy

Temperature-Sense Input Prevents Auto-Charging for

JEITA Compliance

The charging parameters and operating modes are

programmable through an I²C Interface that operates up to

3.4 Mbps. The charger and boost regulator circuits sw itch at

3 MHz to minimize the size of external passive components.

.

Thermal Regulation and Shutdow n

4.2 V at 2.3 A Production Test Mode

5 V, 500 mA Boost Mode for USB OTG

28 V Absolute Maximum Input Voltage

6 V Maximum Input Operating Voltage

The FAN5404X provides battery charging in three phases:

conditioning, constant current, and constant voltage. The

integrated circuit automatically restarts the charge cycle

w hen the battery falls below a voltage threshold. If the input

source is removed, the IC enters a high-impedance mode

blocking battery current from leaking to the input. Charge

status is reported back to the host through the I²C port.

Programmable through High-Speed I²C Interface

(3.4 Mb/s) w ith Fast Mode Plus Compatibility

-

Input Current

Fast-Charge / Termination Current

Float Voltage

Dynamic input voltage control prevents a w eak adapter’s

voltage from collapsing, ensuring charging capability from

such adapters.

Termination Enable

The FAN5404X is available in a 25-bump, 0.4 mm pitch,

WLCSP package.

.

3 MHz Synchronous Buck PWM Controller w ith

Wide Duty Cycle Range

.

Small Footprint 1 µH External Inductor

Safety Timer w ith Reset Control

VBUS

C_BUS

L1

SW

C_SYS

SYS

PGND

Dynamic Input Voltage Control

SYSTEM

LOAD

Q5

PMID

GATE

Very Low Battery Current w hen Charger Inactive

C_MID

External

PMOS

Applications

FAN5404X

POK_B

ILIM

VBAT

.

Cell Phones, Smart Phones, PDAs

C_BAT

SDA

SCL

NTC

REF

Tablet, Portable Media Players

Gaming Device, Digital Cameras

R_REF

BATTERY

DIS

C_REF

+

STAT

AGND

T

Figure 1. Typical Application

All trademarks are the property of their respective owners.

December-2017, Rev. 2

Publication Order Number:

FAN54041/D

Ordering Information

Part Number

FAN54040UCX

FAN54041UCX

FAN54042UCX⁽¹⁾

FAN54045UCX⁽¹⁾

FAN54046UCX⁽¹⁾

FAN54047UCX

Temperature Range

Package

PN Bits: IC_INFO[5:3] Packing Method

000

001

25-Bump, Wafer-Level

Chip-Scale Package

(WLCSP), 0.4 mm Pitch

010

-40 to 85°C

Tape and Reel

101

110

Note:

1. Contact ON Semiconductor Sales for availability.

Table 1. Feature Comparison Summary

Part Number

Slave Address

Automatic Charge

Battery Absent Behavior

E1 Pin

FAN54040

FAN54041

FAN54042

FAN54045

FAN54046

FAN54047

1101011

Yes

No

Off

On

Off

On

POK_B

ILIM

Yes

No

ILIM

Yes

ILIM

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2

Block Diagram

VBUS

PMID

SW

Q3

C_BUS

Q1

C_MID

Q1A

Q1B

PGND

CHARGE

PUMP

L1

IBUS &

VBUS

CONTROL

C_SYS

AGND

PWM

MODULATOR

Q2

SYS

SYSTEM

LOAD

VBUS OVP

POWER OK

PGND

Q5

GATE

External

PMOS

Q4

CC and CV

Battery

Charger

Q4A

Q4B

POK_B

ILIM

SDA

SCL

I2C INTERFACE

VBAT

NTC

C_BAT

LOGIC AND CONTROL

DIS

TEMP

SENSE

R_REF

STAT

REF

C_REF

BATTERY

+

T

PMID

Q1A

Q1B

SYS

Q4A

Q4B

Greater than V_BAT

Less than V_BAT

ON

OFF

ON

Greater than V_BAT

Less than V_BAT

ON

OFF

ON

OFF

Figure 2. IC and System Block Diagram

Table 2. Recommended External Components

Component

Description

Vendor

Parameter

L

Typ.

Unit

1.0

75

µH

Taiyo Yuden MAKK2016T1R0M

or Equivalent

L1

1 µH, 20%, 2.2 A, 2016

DCR (Series R)

mΩ

Murata: GRM188R60J106M

TDK: C1608X5R0J106M

C_BAT,C_SYS

C_MID

10 µF, 20%, 6.3 V, X5R, 0603

4.7 µF, 10%, 6.3 V, X5R, 0603

1.0 µF, 10%, 25 V, X5R, 0603

C

10

4.7

1.0

µF

(2)

Murata: GRM188R60J475K

TDK: C1608X5R0J475K

C

Murata GRM188R61E105K

TDK:C1608X5R1E105M

C_BUS,

C

Q5

C_REF

ON Semiconductor FDMA905P

R_DS(ON)

C

16

PMOS,12 V, 16 mΩ, MLP2x2

1 µF, 10%, 6.3 V, X5R, 0402

mΩ

µF

1.0

Note:

2. 6.3 V rating is sufficient for C_MIDsince PMID is protected from over-voltage surges on VBUS by Q3.

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3

Pin Configuration

SDA PGND SW

PMID VBUS

A5

B5

C5

D5

E5

A4

B4

C4

D4

E4

A3

B3

C3

D3

E3

A2

B2

C2

D2

E2

A1

B1

C1

D1

E1

A1

A2

B2

C2

D2

A3

B3

C3

A4

B4

C4

A5

SCL

B1

B5

DIS

C1

GATE

C5

STAT

D1

SYS VBAT NTC

D3

E3

D4

D5

POK_B AGND

REF

E5

E1

E2

E4

Figure 3. Top View

Figure 4. Bottom View

Pin Definitions

Pin #

Name Description

SDA

SCL

I²C Interface Serial Data. This pin should not be left floating.

I²C Interface Serial Clock. This pin should not be left floating.

A1

B1

C1

Disable. If this pin is held HIGH, Q1 and Q3 are turned off, creating a HIGH Z condition at VBUS and

the PWM converter is disabled.

DIS

Status. Open-drain output indicating charge status. The IC pulls this pin LOW w hen charge is in

progress; can be used to signal the host processor w hen a fault condition occurs.

D1

E1

STAT

Pow er OK (FAN54040-2). Open-drain output that pulls LOW w hen VBUS is plugged in and the battery

POK_B has risen above V_LOWV. This signal is used to signal the host processor that it can begin to draw

significant current.

Input Current Limit (FAN54045-7). Controls input current limit in Auto-Charge Mode. When LOW, input

current is limited to 100 mA maximum. When HIGH, input current is limited to 500 mA. In 32-Second

Mode, the input current limit is set by the I_BUSLIMbits.

E1

ILIM

Power Ground. Pow er return for gate drive and pow er transistors. The connection from this pin to the

bottom of C_MIDshould be as short as possible.

A2 – D2

PGND

E2

AGND Analog Ground. All IC signals are referenced to this node.

A3 – C3

SW

Switching Node. Connect to output inductor.

System Supply. Output voltage of the sw itching charger and input to the pow er path controller. Bypass

SYS to PGND w ith a 10 μF capacitor.

D3 – E3

A4 – C4

SYS

Power Input Voltage. Pow er input to the charger regulator, bypass point for the input current sense.

Bypass w ith a minimum of a 4.7 µF, 6.3 V capacitor to PGND.

PMID

Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass w ith a 10 µF capacitor

to PGND. VBAT is a pow er path connection.

D4 – E4

A5 – B5

VBAT

VBUS

Charger Input Voltage and USB-OTG output voltage. Bypass w ith a 1 µF capacitor to PGND.

External MOSFET Gate. This pin controls the gate of an external P-channel MOSFET transistor used to

augment the internal ideal diode. The source of the P-channel MOSFET should be connected to SYS

and the drain should be connected to VBAT.

C5

GATE

Thermistor input. The IC compares this node w ith taps on a resistor divider from REF to inhibit auto-

charging w hen the battery temperature is outside of permitted fast-charge limits.

D5

E5

NTC

REF

Reference Voltage. REF is a 1.8 V regulated output.

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4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable

above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,

extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute

maximum ratings are stress ratings only.

Symbol

Parameter

Min.

Max.

Unit

Continuous

-0.3

-1.0

–0.3

V_BUS

Voltage on VBUS Pin

28.0

V

Pulsed, 100 ms Maximum Non-Repetitive

Voltage on PMID Voltage Pin

7.0

6.5⁽³⁾

V_I

V

Voltage on SW, SYS, VBAT, STAT, DIS Pins

Voltage on Other Pins

V_O

dV

BUS

Maximum V _BUSSlope Above 5.5 V w hen Boost or Charger Active

V/µs

4

dt

Human Body Model per JESD22-A114

Electrostatic Discharge

2000

500

15

V

Protection Level

Charged Device Model per JESD22-C101

ESD

Air Gap

(4)

USB Connector

Pins (V _BUSto GND)

IEC 61000-4-2 System ESD

kV

Contact

8

T_J

T_STG

T_L

Junction Temperature

Storage Temperature

–40

–65

+150

+260

°C

Lead Soldering Temperature, 10 Seconds

Note :

3. Lesser of 6.5 V or V_I+ 0.3 V.

4. Guaranteed if C_BUS≥1 µF and C_MID≥ 4. 7µF.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating

conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol

Parameter

Min.

Max.

6

Unit

V

V_BUS

Supply Voltage

4

V_BAT(MAX)Maximum Battery Voltage w hen Boost enabled

4.5

4

V

T_A< 60°C

T_A> 60°C

dV

Negative VBUS Slew Rate during VBUS Short Circuit,

_MID< 4.7 µF, see VBUS Short While Charging

BUS

V/µs

−

C

dt

T_A

T_J

2

Ambient Temperature

Junction Temperature (see Thermal Regulation and Protection section)

–30

+85

+120

°C

Thermal Properties

Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured w ith four-layer

2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature

T_{J( max)}at a given ambient temperature T_A. For measured data, see Table 18.

Symbol

Parameter

Junction-to-Ambient Thermal Resistance (see also Figure 18)

Junction-to-PCB Thermal Resistance

Typical

Unit

°C/W

50

20

θ_JA

θ_JB

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5

Electrical Specifications

Unless otherw ise specified: according to the circuit of Figure 1; recommended operating temperature range for T_Jand T_A;

V_BUS=5.0 V; HZ_MODE; OPA _MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for T_J=25°C.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Power Supplies

V_BUS> V_BUS(min), PWM Sw itching

10

mA

V_BUS> V_BUS(min); V_BAT> V_OREG

I_BUSLIM=100 mA

2.5

I_VBUS

VBUS Current

0°C < T_J< 85°C, HZ_MODE=1

V_BAT< V_LOWV, 32S Mode, I_REG=0

280

10

µA

Battery Discharge Current in High-

Impedance Mode

DIS=1, or HZ_MODE=1,

I_{BAT_HZ}

I_{BUS_HZ}

<1

V

_BUS=0, 5 V or Floating, V_BAT=4.2 V

Battery Leakage Current to V_BUSin

High-Impedance Mode

DIS=1, or HZ_MODE=1,

V_BUSShorted to Ground, V_BAT=4.2 V

-5.0

-0.2

Charger Voltage Regulation

Charge Voltage Range

3.5

–0.5

–1

4.4

+0.5

+1

V

V_OREG

T_A=25°C

%

Charge Voltage Accuracy

Charging Current Regulation

Output Charge Current Range

T_J=0 to 125°C

IO_LEV EL =0

V_LOWV< V_BAT< V_OREG

IO_LEV EL =1

550

290

–5

1550

390

+5

mA

%

I_OCHRG

340

Charge Current Accuracy

Weak Battery Detection

Weak Battery Threshold Range

IO_LEV EL =0

3.4

–5

3.7

+5

V

%

V_LOWV

Weak Battery Threshold Accuracy

Weak Battery Deglitch Time

Rising Voltage, 2 mV Overdrive

Input Tied to GND or V_BUS

30

ms

Logic Levels : DIS, SDA, SCL

V_IH

V_IL

High-Level Input Voltage

1.05

V

Low -LevelInput Voltage

Input Bias Current

0.4

I

IN

0.01

1.00

µA

Charge Termination Detection

Termination Current Range

V_BAT> V_OREG– V_RCH, V_BUS> V_SLP

I_TERMSetting < 100 mA

50

–15

–5

400

+15

+5

mA

%

I

Termination Current Accuracy

(TERM)

I_TERMSetting > 200 mA

Termination Current Deglitch Time

30

ms

Power Path (Q4) Control

IO_LEV EL =1

290

400

340

450

390

510

mA

I_BUSLIM> 01,

IO_LEV EL =0

I_LIN

Pow er Path Max. Charge Current

I_OCHARGE< 02

I_BUSLIM> 01,

IO_LEV EL =0

650

725

800

mA

I_OCHARGE> 02

(SYS-VBAT) Falling

(SYS-VBAT) Rising

–6

-1

–5

+1

–3

2

mV

VBAT to SYS Threshold for Q4 and

Gate Transition While Charging

V_THSYS

Production Test Mode

V_BAT(PTM)Production Test Output Voltage

I_BAT(PTM)Production Test Output Current

1 mA < I_BAT< 2 A, V_BUS=5.5 V

4.116 4.200

2.3

4.284

V

A

20% Duty w ith Max. Period 10 ms

Continued onthe following page…

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6

Electrical Specifications (Continued)

Unless otherw ise specified: according to the circuit of Figure 1; recommended operating temperature range for T_Jand T_A;

V_BUS=5.0 V; HZ_MODE; OPA _MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for T_J=25°C.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Input Power Source Detection

T1

T2

T3

T4

T1 (0°C) Temperature Threshold

71.9

62.6

31.9

21.3

73.9

64.6

32.9

23.3

75.9

66.6

34.9

25.3

T1 (10°C) Temperature Threshold

T1 (45°C) Temperature Threshold

T1 (60°C) Temperature Threshold

% of

V_REF

Input Power Source Detection

V_IN(MIN)1VBUS Input Voltage Rising

V_IN(MIN)2Minimu m VBUS during Charge

To Initiate and Pass VBUS Validation

During Charging

4.29

3.71

30

4.42

3.94

V

t_{VBUS_VALID}VBUS Validation Time

ms

V_BUSControl Loop

V_BUSLIM

VBUS Loop Setpoint Accuracy

–3

+3

%

Input Current Limit

I_BUSLIMSet to 100 mA

I_BUSLIMSet to 500 mA

88

93

98

Charger Input Current Limit

Threshold

I_BUSLIM

mA

450

475

500

V_REFBias Generator

Bias Regulator Voltage

Short-Circuit Current Limit

V_BUS> V_IN(MIN)

1.8

2.5

V

V_REF

mA

Battery Recharge Threshold

Recharge Threshold

Below V_(OREG)

100

120

130

150

mV

ms

V_RCH

Deglitch Time

V_BATFalling Below V_RCHThreshold

STAT, POK_B Output

V_STAT(OL)

I_STAT(OH)

STAT Output Low

I_STAT=10 mA

V_STAT=5 V

0.4

1

V

STAT High Leakage Current

µA

Battery Detection

Battery Detection Current before

I_DETECT

t_DETECT

–0.8

262

mA

ms

Charge Done (Sink Current)⁽⁵⁾

Battery Detection Time

Begins after Termination Detected

and V_BAT< V_OREG–V_RCH

Sleep Comparator

Sleep-Mode Entry Threshold,

V_BUS– V_BAT

Power Switches (see Figure 2)

Q3 On Resistance (VBUS to PMID)

V_SLP

2.3 V < V_BAT< V_OREG, V_BUSFalling

0

0.04

0.10

V

I_IN(LIMIT)=500 mA

180

130

150

70

250

225

100

Q1 On Resistance (PMID to SW)

Q2 On Resistance (SW to GND)

Q4 On Resistance (SYS to VBAT)

mΩ

R_DS(ON)

V_BAT=4.2 V

mΩ

Synchronous to Non-Synchronous

Current Cut-Off Threshold⁽⁶⁾

Low -Side MOSFET (Q2) Cycle-by-

Cycle Current Limit

I_SYNC

140

mA

Continued onthe following page…

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7

Electrical Specifications (Continued)

Unless otherw ise specified: according to the circuit of Figure 1; recommended operating temperature range for T_Jand T_A;

V_BUS=5.0 V; HZ_MODE; OPA _MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for T_J=25°C.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Charger PWM Modulator

f_SW

D_MAX

D_MIN

Oscillator Frequency

Maximum Duty Cycle

Minimu m Duty Cycle

2.7

3.0

0

3.3

MHz

%

100

%

Boost Mode Operation (OPA_MODE=1, HZ_MODE=0)

2.5 V < V_BAT< 4.5 V, I_LOADfrom 0 to

200 mA

4.80

4.77

5.07

5.20

V_BOOST

Boost Output Voltage at VBUS

V

3.0 V < V_BAT< 4.5 V, I_LOADfrom 0 to

500 mA

I_BAT(BOOST)Boost Mode Quiescent Current

PFM Mode, V_BAT=3.6 V, I_LOAD=0

250

1550

2.32

2.48

350

µA

I_LIMPK(BST)

Q2 Peak Current Limit

1350

1950

mA

While Boost Active

Minimu m Battery Voltage for Boost

Operation

UVLO_BST

V

To Start Boost Regulator

2.70

VBUS Load Resistance

Normal Operation

VBUS Validation

500

100

kΩ

R_VBUS

VBUS to PGND Resistance

Ω

Protection and Timers

VBUS Over-Voltage Shutdow n

V_BUSRising

V_BUSFalling

6.09

1.95

6.29

100

6.49

2.05

V

VBUS_OVP

I_LIMPK(CHG)

V_SHORT

Hysteresis

mV

Q1 Cycle-by-Cycle Peak Current

Limit

Charge Mode

V_BATRising

3

A

Battery Short-Circuit Threshold

Hysteresis

2.00

100

13

V

mV

Pow er Path

V_BAT< V_SHORT

I_SHORT

Linear Charging Current

mA

°C

Linear

30

Thermal Shutdow n Threshold⁽7

T_JRising

145

25

)

T_SHUTDWN

)

Hysteresis⁽7

T_JFalling

)

T_CF

t_INT

Thermal Regulation Threshold⁽7

Charge Current Reduction Begins

120

2.1

°C

s

Detection Interval

32-Second Timer⁽⁸⁾

Charger Enabled

Charger Disabled

20.5

18.0

25.2

28.0

34.0

t_32S

s

15-Minute Mode (FAN54040,

FAN54042, FAN54046, FAN54047)

t_15MIN

15-Minute Timer

12.0

–25

13.5

15.0

25

min

%

∆t_LF

Low -Frequency Timer Accuracy

Charger Inactive

Note s:

5. Negative current is current flow ing from the battery to VBUS (discharging the battery).

6. Q2 alw ays turns on for 60 ns, then turns off if current is below I_SYNC

7. Guaranteed by design; not tested in production.

.

8. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers.

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8

I²C Timing Specifications

Guaranteed by design.

Symbol

Parameter

Conditions

Min.

Typ. Max.

Unit

Standard Mode

100

400

1000

3400

1700

4.7

Fast Mode

f_SCL

SCL Clock Frequency

Fast Mode Plus

kHz

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

BUS-free Time betw een STOP and

START Conditions

t_BUF

Fast Mode

1.3

µs

Fast Mode Plus

0.5

Standard Mode

4

µs

ns

µs

ns

µs

ns

µs

ns

Fast Mode

600

260

160

4.7

START or Repeated START Hold

Time

t_HD;STA

Fast Mode Plus

High-Speed Mode

Standard Mode

Fast Mode

1.3

t_LOW

SCL LOW Period

Fast Mode Plus

0.5

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

160

320

4

Fast Mode

600

260

60

t_HIGH

SCL HIGH Period

Fast Mode Plus

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

120

4.7

Fast Mode

600

260

160

250

100

50

t_SU;STA

Repeated START Setup Time

Fast Mode Plus

High-Speed Mode

Standard Mode

Fast Mode

t_SU;DATData Setup Time

ns

Fast Mode Plus

High-Speed Mode

Standard Mode

10

0

3.45

900

450

70

µs

ns

Fast Mode

t_HD;DATData Hold Time

Fast Mode Plus

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

150

20+0.1C_B

10

20

1000

300

120

80

Fast Mode

t_RCL

SCL Rise Time

Fast Mode Plus

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

160

Continued onthe following page…

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9

I²C Timing Specifications (Continued)

Guaranteed by design.

Symbol

Parameter

Conditions

Min.

Typ. Max.

Unit

Standard Mode

20+0.1C_B

10

300

120

40

Fast Mode

t_FCL

SCL Fall Time

Fast Mode Plus

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

20

10

20

80

Rise Time of SCL after a Repeated

START Condition and after ACK Bit

t_RCL1

ns

160

1000

300

120

80

20+0.1C_B

Fast Mode

20+0.1C_B

t_RDA

SDA Rise Time

SDA Fall Time

Fast Mode Plus

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

10

20

20+0.1C_B

160

300

120

80

Fast Mode

20+0.1C_B

t_FDA

Fast Mode Plus

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

10

20

4

160

µs

ns

pF

Fast Mode

600

120

160

t_SU;STOStop Condition Setup Time

Fast Mode Plus

High-Speed Mode

C_B

Capacitive Load for SDA and SCL

400

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10

Timing Diagrams

t_F

t_SU;STA

t_BUF

SDA

t_R

T_SU;DAT

t_HD;STO

t_HIGH

t_HD;DAT

SCL

t_LOW

t_HD;STA

REPEATED

START

STOP

START

Figure 5. I²C Interface Timing for Fast and Slow Modes

REPEATED

START

STOP

t_FDA

t_RDA

t_SU;DAT

SDAH

t_SU;STA

t_RCL1

t_FCL

t_HIGH

t_HD;DAT

note A

t_RCL

t_SU;STO

SCLH

t_LOW

t_HD;STA

REPEATED

START

= MCS Current Source Pull-up

= R_PResistor Pull-up

Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.

Figure 6. I²C Interface Timing for High-Speed Mode

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11

Charge Mode Typical Characteristics

Unless otherw ise specified, circuit of Figure 1, V_OREG=4.2 V, V_BUS=5.0 V, and T_A=25°C.

800

700

600

500

400

300

200

140

130

120

110

100

90

4.5 VBUS

5.0 VBUS

5.5 VBUS

4.5 VBUS

5.0 VBUS

5.5 VBUS

80

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

Battery Voltage VBAT (V)

Figure 7. Battery Charge Current vs. V_BUSwith

I_BUSLIM=100 mA

Figure 8. Battery Charge Current vs. V_BUSwith

I_BUSLIM=500 mA

95

90

85

80

75

90

88

86

84

82

4.5VBUS, 3.9VBAT

4.5 VBUS

5.0 VBUS

5.5 VBUS

5.0VBUS, 3.54VBAT

80

70

65

5.0VBUS, 4.2VBAT

5.5VBUS, 3.9VBAT

78

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

550

750

950

1150

1350

1550

Battery Voltage VBAT (V)

Battery Charge Current IBAT (mA)

Figure 10. Efficiency vs. Charging Current,

I_BUSLIM=No Limit

Figure 9. Efficiency vs. V_BUS, I_BUSLIM=500 mA, I_SYS=0

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12

Charge Mode Typical Characteristics

Unless otherw ise specified, circuit of Figure 1, V_OREG=4.2 V, V_BUS=5.0 V, and T_A=25°C.

Figure 11. Charger Startup at V_BUSPlug-In, 100 mA

Figure 12. Charger Startup at V_BUSPlug-In, 500 mA

I_BUSLIM, 3.2 V_BAT, 100 Ω SYS Load

I_INBUSLIM, 3.2 V_BAT, 100 Ω SYS Load

Figure 13. Charger Startup at V_BUSPlug-In Using

Figure 14. Charger Startup with HZ Bit Reset, 500 mA

300 mA Current Limited Source, 500 mA I_BUSLIM

,

I_BUSLIM, 950 mA I_CHARGE, 50 Ω SYS Load

3.2 V_BAT, 50 Ω SYS Load

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13

Charge Mode Typical Characteristics

Unless otherw ise specified, circuit of Figure 1, V_OREG=4.2 V, V_BUS=5.0 V, and T_A=25°C.

Figure 15. Battery Removal / Insertion while Charging,

TE=0, 3.9 V_BAT, I_CHRG=950 mA, I_BUSLIM=No Limit, 50 Ω

SYS Load

Figure 16. Battery Removal / Insertion when

Charging, TE=1, 3.9 V_BAT, I_CHRG=950 mA, I_BUSLIM=No

Limit, 50 Ω SYS Load

Figure 17. No Battery at V_BUSPower-Up, FAN54040, 100 Ω

SYS Load, 1 kΩ V_BATLoad

Figure 18. No Battery at V_BUSPower-Up, FAN54042,

100 Ω SYS Load, 1 kΩ V_BATLoad

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14

Charge Mode Typical Characteristics

Unless otherw ise specified, circuit of Figure 1, V_OREG=4.2 V, V_BUS=5.0 V, and T_A=25°C.

1,000

800

600

400

200

0

2.00

1.80

1.60

1.40

1.20

1.00

-30C

+25C

+85C

-30C

+25C

+85C

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

0

1

2

3

4

5

VBUS Input Voltage (V)

VREF Load Current (mA)

Figure 19. HZ Mode VBUS Current vs. Temperature,

3.7 V_BAT

Figure 20. V_REFvs. Load Current, Over-Temperature,

5.0 V_BUS

Figure 21. Charging vs. Temperature (NTC), +30°C to -10°CFigure 22 Charging vs. Temperature (NTC), +30°C to +70°C

3.7 V_BAT, I_CHRG=950 mA, No I_BUSLIM, 100 Ω SYS Load 3.7 V_BAT, I_CHRG=950 mA, No I_BUSLIM,100 Ω SYS Load

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15

GSM Typical Characteristics

A 2.0 A GSM pulse applied at VBAT w ith 5 µs rise / fall time. Simultaneous to GSM pulse, 50 Ω additional load applied at SYS.

Figure 23. 2.0 A GSM Pulse Response, I_BUSLIM=500 mA

Control, I_CHRG=950 mA, 3.7 V_BAT, OREG=4.2 V

Figure 24. 2.0 A GSM Pulse Response, I_BUSLIM=500 mA,

I_CHRG=950 mA, 3.7 V_BAT, OREG=4.2 V, 200 mA Source

Current Limit

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16

Boost Mode Typical Characteristics

Unless otherw ise specified, using circuit of Figure 1, V_BAT=3.6 V, T_A=25°C.

100

95

90

85

80

75

100

95

90

85

80

75

-10C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

2.7VBAT

3.6VBAT

4.2VBAT

0

100

200

300

400

500

0

100

200

300

400

500

VBUS Load Current (mA)

Figure 25. Efficiency vs. I_BUSOver V_BAT

Figure 26. Efficiency vs. I_BUSOver-Temperature, 3.6 V_BAT

5.15

5.10

5.05

5.00

4.95

4.90

4.85

30

25

20

15

2.7VBAT

3.6VBAT

4.2VBAT

10

2.7VBAT

5

3.6VBAT

4.2VBAT

0

100

200

300

400

500

0

100

200

300

400

500

VBUS Load Current (mA)

Figure 27. Regulation vs. I_BUSOver V_BAT

Figure 28. Output Ripple vs. I_BUSOver V_BAT

350

300

250

200

150

100

10

-30C

+25C

+85C

8

6

4

2

0

-30C

+25C

+85C

2

2.5

3

3.5

4

4.5

5

2

2.5

3

3.5

4

4.5

5

Battery Voltage, VBAT (V)

Figure 29. Quiescent Current (I_Q) vs. V_BATOver-

Temperature

Figure 30. Battery Discharge Current vs. V_BAT, HZ /

Sleep Mode

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17

Boost Mode Typical Characteristics

Unless otherw ise specified, using circuit of Figure 1, V_BAT=3.6 V, T_A=25°C.

Figure 31. OTG Startup, 50 Ω Load, 3.6 V_BAT

Figure 32. OTG V_BUSOverload Response

External / Additional 10 µf on VBUS

Figure 33. Load Transient, 20-200-20 mA I_BUS

,

Figure 34. Line Transient, 50 Ω Load, 3.9-3.3-

t_RISE/FALL=100 ns

3.9 V_BAT, t_RISE/FALL=10 µs

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18

Circuit Description / Overview

When charging batteries w ith a current-limited input source,

such as USB, a sw itching charger’s high efficiency over a

w ide range of output voltages minimizes charging time.

Battery Charging Curve

If the battery voltage is below V_SHORT, a linear current source

pre-charges the battery until V_BATreaches V_SHORT. The PWM

charging circuit is then started and the battery is charged

w ith a constant current if sufficient input pow er is available.

The current slew rate is limited to prevent overshoot.

FAN5404X combines a highly integrated synchronous buck

regulator for charging w ith a synchronous boost regulator,

w hich can supply 5 V to USB On-The-Go (OTG) peripherals.

The FAN5404X employs synchronous rectification for both

the charger and boost regulators to maintain high efficiency

over a w ide range of battery voltages and charge states.

The FAN5404X is designed to w ork w ith a current-limited

input source at VBUS. During the current regulation phase of

charging, I_BUSLIMor the programmed charging current limits

the amount of current available to charge the battery and

pow er the system. The effect of I_BUSLIMon I_CHARGEcan be

seen in Figure 36.

The FAN5404X has four operating modes:

1. Charge Mode:

Charges a single-cell Li-ion or Li-polymer battery.

2. Boost Mode:

V_BAT

V_FLOAT

Provides 5 V pow er to USB-OTG w ith an integrated

synchronous rectification boost regulator, using the

battery as input.

I_BAT

I_CHARGE

I_{O_LEVEL}

V_BATMIN

3. High-Impedance Mode:

Both the boost and charging circuits are OFF in this

mode. Current flow from VBUS to the battery or from the

battery to VBUS is blocked in this mode. This mode

consumes very little current from VBUS or the battery.

I_TERM

V_SHORT

I_SHORT

4. Production Test Mode

This mode provides 4.2 V output on VBAT and supplies

a load current of up to 2.3 A.

I_SHORT

CHARGE

CONSTANT

VOLTAGE (CV)

PRE-

CONSTANT

CHARGE CURRENT (CC)

RE-

CHARGE

ICHARGE Current Charging

Charge Mode

Figure 35. Charge Curve, I_CHARGENot Limited by I_INLIM

In Charge Mode, FAN5404X employs six regulation loops:

1. Input Current: Limits the amount of current draw n from

VBUS. This current is sensed internally and can be

programmed through the I²C interface.

V_BAT

V_FLOAT

I_CHARGE

2. Charging Current: Limits the maximum charging current.

This current is sensed using an internal sense

MOSFET.

I_BAT

I_{O_LEVEL}

V_BATMIN

I_TERM

3. VBUS Voltage: This loop is designed to prevent the

input supply from being dragged below V_BUSLIM(typically

4.5 V) w hen the input pow er source is current limited.

An example of this w ould be a travel charger. This loop

cuts back the current w hen V_BUSapproaches V_BUSLIM,

allow ing the input source to run in current limit.

V_SHORT

I_SHORT

CHARGE

CONSTANT

VOLTAGE (CV)

PRE-

CONSTANT

CHARGE CURRENT (CC)

RE-

CHARGE

Input Current Limited Charging

4. Charge Voltage: The regulator is restricted from

exceeding this voltage. As the internal battery voltage

rises, the battery’s internal impedance w orks in

conjunction w ith the charge voltage regulation to

decrease the amount of current flow ing to the battery.

Battery charging is completed w hen the current through

Q4 drops below the I_TERMthreshold.

Figure 36. Charge Curve, I_BUSLIMLimits I_CHARGE

Assuming that V_OREGis programmed to the cell’s fully

charged “float” voltage, the current that the battery accepts

w ith the PWM regulator limiting its output (sensed at VBAT)

to V_OREGdeclines and the charger enters the voltage

regulation phase of charging. When the current declines to

the programmed I_TERMvalue, the charge cycle is complete.

Charge current termination can be disabled by resetting the

TE bit (REG1[3]).

5. Pow er Path: When V_BATis below V_BATMIN, Q4 operates

as a linear current source and modulates its current to

ensure that the voltage on SYS stays above 3.4 V.

6. Temperature: If the IC’s junction temperature reaches

120°C, charge current is reduced until the IC’s

temperature is below 120°C.

The charger output or “float” voltage can be programmed by

the OREG bits from 3.5 V to 4.44 V in 20 mV increments, as

show n in Table 4.

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19

The follow ing charging parameters can be programmed by

the host through I²C:

Charge Current Limit (I_OCHARGE

)

Table 5. I_OCHARGECurrent asFunctionof I_OCHARGE

Bits (REG4 [6:3])

Table 3. Programmable Charging Parameters

Parameter

Output Voltage Regulation

Battery Charging Current Limit

Input Current Limit

Name

V_OREG

I_OCHRG

Register

REG2[7:2]

REG4[6:3]

REG1[7:6]

REG4[2:0]

REG1[5:4]

DEC

BIN

0000

HEX

I

_OCHARGE(mA)

550

0

1

0001

650

I

INLIM

2

0010

2

750

Charge Termination Limit

Weak Battery Voltage

I_TERM

3

0011

3

850

V_LOWV

4

0100

4

950

5

0101

5

1,050

1,150

1,250

1,350

1,450

1,550

Table 4. OREG Bits (OREG[7:2]) vs. Charger V_OUT

(V_OREG) Float Voltage

6

0110

6

Decimal Hex VOREG

7

8

0111

7

1000

8

0

1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

3.50

3.52

3.54

3.56

3.58

3.60

3.62

3.64

3.66

3.68

3.70

3.72

3.74

3.76

3.78

3.80

3.82

3.84

3.86

3.88

3.90

3.92

3.94

3.96

24

25

18

19

3.98

4.00

4.02

4.04

4.06

4.08

4.10

4.12

4.14

4.16

4.18

4.20

4.22

4.24

4.26

4.28

4.30

4.32

4.34

4.36

4.38

4.40

4.42

4.44

9

1001

9

2

26

1A

1B

1C

1D

1E

1F

20

10-15

1010-1111

A-F

3

27

When the IO_LEVEL bit is set (default), the I_OCHARGEbits are

ignored and charge current is set to 340 mA.

4

28

5

29

PWM Controller in Charge Mode

6

30

The IC uses a current-mode PWM controller to regulate the

output voltage and battery charge currents. The synchronous

rectifier (Q2) has a negative current limit that turns off Q2 at

140 mA to prevent current flow from the battery.

7

31

8

32

9

33

21

10

11

12

13

14

15

16

17

18

19

20

21

22

23

34

22

Termination Current Limit

35

23

Current charge termination is enabled w hen TE (REG1[3])=1.

Typical termination current values are given in Table 6.

36

24

37

25

Table 6. Termination Current asFunction of ITERM

Bits (REG4[2:0]) or PC_IT Bits(REG7[2:0]

38

26

Termination Current

39

27

ITERM Bits or PC_IT Bits

(mA)

40

28

0

1

2

3

4

5

6

7

50

41

29

100

150

200

250

300

350

400

42

2A

2B

2C

2D

2E

2F-3F

43

44

45

46

47 - 63

Note:

When the charge current falls below I_TERM;PWM charging

stops, but the STAT pin remains LOW. The STAT pin then

goes HIGH and the STATUS bits change to CHARGE DONE

(10), provided the battery and charger are still connected.

9. Default settings are denoted by bold typeface.

Provided DIS, CE# and HZ_MODE are LOW, a new charge

cycle begins w hen one of the follow ing occurs:

1. The battery voltage falls below V_OREG- V_RCHafter

charge termination has occurred.

2. Any I²C w rite occurs causing the T32 s timer to run.

A post-charging feature, “top-off” charging, is available to

continue the battery charging to a low er charge current to

maximize battery capacity. The PC_EN bit must be set to 1

before the battery charging current reaches the termination

current I_TERMfor normal charging. The post-charging

termination current is set by the PC_IT[2:0] bits, as show n in

Table 6. If PC_EN is set to 1; right after the normal charging

is ended as described above, post charging is started w ith

PC_ON monitor bit set to 1. Once the current reaches the

Products that include the auto-charge feature also begin

charging if:

3. VBUS Pow er-on-Reset (POR) occurs and the battery

voltage is below the w eak battery threshold (V_LOWV).

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20

threshold for post-charging completion, PWM charging stops

and PC_ON bit changes back to 0.

time, POK_B is HIGH. If V_BAT< V_SHORT, Q4’s current is

further reduced to about 13 mA (I_SHORT) w hen I_BUSLIMis set to

100 or 500 mA . For all other input current limits, I_SHORT

current is approximately 30 mA.

During post-charging, the STAT pin is HIGH, indicating that

the charge current is below the I_TERMlevel. To exit post-

charging, one of the follow ing must occur: a V_BUSPOR, the

POK_B cycled w hen V_BAT<3.0 V, or the CE# or HZ_Mode

bit cycled.

The POK_B signal can be used to keep the system in a low -

pow er state, preventing excessive loading from the system

w hile attempting to charge a depleted battery.

Table 7. VBATMIN Thresholdsto Exit Power Path

Mode

SafetyTimer

At the beginning of charging, the IC starts a 15-minute timer

(t_15MIN). When this timer times out, charging is terminated.

Writing to any register through I²C stops and resets the t_15MIN

timer, w hich in turn starts a 32-second timer (t_32S). Setting

the TMR_RST bit (REG0[7]) resets the t_32Stimer. If the t_32S

timer times out; charging is terminated, the registers are set

to their default values, and charging resumes using the

default values w ith the t_15MINtimer running.

I_BUSLIM(mA)

V_BATMIN(V)

100

500

3.4

3.3

3.2

800

No Limit

After V_BATreaches V_BATMIN, Q4 closes and is used as a

current-sense element to limit I_CHARGEper the I²C register

settings by limiting the PWM modulator’s current (Full PWM

Mode). During PWM Mode, if SYS drops more than 5 mV

(V_THSYS) below V_BAT, Q4 and Q5 are turned on (GATE is

Normal charging is controlled by the host w ith the t_32Stimer

running to ensure that the host is alive. Charging w ith the

t_15MINtimer running is used for charging unattended by the

host. If the t_15MINtimer expires, the IC turns off the charger

and indicates

a timer fault (110) on the FAULT bits

pulled LOW). Once SYS voltage becomes higher than V_BAT

Q5 is turned off and Q4 again serves as the current-sense

element to limit I_OCHARGE

,

(REG0[2:0]). This sequence prevents overcharge if the host

fails to reset the t_32Stimer.

.

Q4 and Q5 are both turned on w hen the IC enters SLEEP

Mode (V_BUS< V_BAT).

V_BUSPOR / Non-CompliantCharger Rejection

256 ms after VBUS is connected, the IC pulses the STAT pin

and sets the VBUS_CON bit. Before starting to supply

current, the IC applies a 110 Ω load from VBUS to GND.

V_BUSmust remain above V_IN(MIN)1and below VBUS_OVPfor

t_{VBUS_VALID}(32 ms) before the IC initiates charging or

supplies pow er to SYS. The V_BUSvalidation sequence

alw ays occurs before significant current is draw n from VBUS

(for example, after a VBUS OVP fault or a V_RCHrecharge

initiation). t_{VBUS_VALID}ensures that unfiltered 50/60 Hz

chargers and other non-compliant chargers are rejected.

POK_B pulls LOW once V_BATreaches V_LOWV, and remains

LOW as long as the IC is in Full PWM Mode. The IC remains

in Full PWM Mode as long as V_BAT> 3.0 V, at w hich point,

the IC enters Pow er Path Charging Mode.

Startup with a Dead Battery

At V_BUSPOR, a 2 kΩ load is applied to VBAT for 256 ms to

discharge any residual system capacitance in case the

battery is absent or its discharge protection sw itch is open.

USB-FriendlyBoot Sequence

If V_BAT< V_LOWV, all registers are reset to default values and

the IC charges in T15Min Mode. If V_BAT< V_SHORT, the

SAFETY register is reset to its default value and the Battery

Detection test below is performed.

At V_BUSPOR, w hen the battery voltage is above the w eak

battery threshold (V_LOWV); the IC operates in accordance w ith

its I²C register settings. If V_BAT< V_LOWVand t_32sis not

running, the IC sets all registers to their default values and

begins to deliver pow er to SYS.

Battery Detection

If V_BATis below V_SHORTw hen charging is enabled, the

DBAT_B bit is reset and the IC (except FAN54045 and

FAN54046) performs an addition battery detection test.

FAN54040, FAN54042, and FAN54047 feature auto-charge,

w hich allow these parts to deliver charge to the battery prior

to receiving host commands.

After V_BATrises above V_SHORT, PWM charging begins (w hen

CE# = 0) w ith the float voltage (V_OREG) temporarily set to 4 V.

If the battery voltage exceeds 3.7 V w ithin 32 ms of the

beginning of PWM charging, the battery is absent. If battery

absence is detected:

FAN54041 does not automatically initiate charging at V_BUS

POR. Instead, it w aits in IDLE state for the host to initiate

charging through I²C commands. While in IDLE state, Q4

and Q5 are on. This allow s the system to run through a

separate pow er path w ithout requiring an additional

disconnection MOSFET.

1. STAT pulses, w ith FAULT bits set to 111, and the

NOBAT bit is set.

2. For FAN54040 only; the t_15MINtimer is disabled until

V_BUSis removed, IDLE state is entered, and POK_B

remains HIGH.

Power Path Operation

As long as V_BAT< V_BATMIN, Q4 operates as a linear current

source, (Pow er Path Mode) w ith its current limited to

340 mA . The IC then regulates SYS to 3.54 V and attempts

to charge the battery w ith as much current as possible w ith

the available I_BUSLIMinput current, w ithout allow ing SYS to

drop below 3.4 V. This ensures that system pow er alw ays

receives first priority from a limited input supply. During this

3. The IC bypasses the protection sw itch close test below ,

since no battery is present.

The FAN54042 and FAN54047 continue to charge.

If V_BATremained below 3.7 V during the initial 32 ms period,

Pow er Path Mode charging continues to ensure that the

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21

battery’s discharge protection sw itch has closed before

exiting Pow er Path Mode:

Once the host processor begins w riting to the IC, charge

parameters are set by the host, w hich must continually reset

the t_32Stimer to continue charging using the programmed

charging parameters.

1. If V_BATis less than 3.4 V, V_SYSis set to 4 V, and Pow er

Path charging continues until V_BAThas exceeded 3.4 V

for at least 128 ms. Charging continues until:

If t_32Stimes out; the register defaults are loaded, the FAULT

bits are set to 110, STAT is pulsed, and charging continues

w ith default charge parameters in T15MIN Mode for the

FAN54040, FAN54042, and FAN54047.

2. V_BAThas dropped below 3.2 V for at least 32 ms. Once

this occurs, V_SYSreturns to the OREG register setting

(default 3.54 V).

POK_B (see Table 8)

3. V_BAThas again risen above V_BATMINfor at least 4 ms.

The POK_B pin and bit are intended to provide feedback to

the baseband processor that the battery is strong enough to

allow the device to fully function. Whenever the IC is

operating in Pow er Path Mode, POK_B is HIGH. On exiting

After these three events, PWM Mode is entered and the IC

sets the DBAT_B bit. If the host sets the DBAT_B bit

(Reg2[1]), events 1 and 2 above are skipped and PWM

Mode is entered once V_BATrises above V_BATMIN

.

Pow er Path Mode, POK_B remains HIGH until V_BAT> V_LOWV

.

In a typical application, as soon as the host processor has

cleared its UVLO threshold (typically 3.3 V), the host’s low

level softw are w ould set the IBUSLIM and IOCHARGE

registers to charge the battery more rapidly above V_BATMINas

soon as the host determines that more than 100 mA is

available through VBUS (see Figure 37).

Reg1[5:4] sets the V_LOWVthreshold.

The STAT pin pulses any time the POK_B pin changes.

Table 8. Q4, Q5, POK_B, andGATE Operation vs. ChargingMode

Q4 CC-CV Control

V_BUS

V_BAT

V_SYS

Q4 Q5 GATE POK_B

Pow er Path Mode: Maintain V_SYS> 3.4 V

Pow er Path Mode: Limit I_CHARGE< 340 mA

Valid

< V_BATMIN

<3.4

Linear OFF HIGH

HIGH

LOW

HIGH

> 3.4 Linear OFF HIGH

> V_BATMINand < V_LOWV

> V_LOWV

PWM Mode. Q4 Senses Current for I_CHARGE

Valid

X

ON OFF HIGH

ON ON LOW

OFF

<V_BAT

X

Note:

10. POK_B remains LOW until Q4 returns to Pow er Path Mode. Q4 and Q5 are both ON if V_SYS< V_BATand CE# = 0.

If CE# = 1 and V_SYS< V_BAT, Q5 is OFF and Q4 blocks current flow from VBAT to SYS.

Table 9. Q4, Q5 Operation as a Function of Relationship between V_BUSand V_BAT

PWM

Charger

CE#

V_BUS

V_BAT

Q4

Q5

GATE

< V_SYS

>V_BATMIN

,

ON

PWM Mode

0

Valid

ON

OFF

HIGH

> V_SYS

>V_BATMIN

,

ON

PWM Mode

Disabled

0

1

Valid

ON

LOW

HIGH

X

OFF

2 V < V_BAT

V_BATMIN

<

ON

Pow er Path Charging

30 mA Linear Charging

OFF

0

X

Valid

X

Linear

ON

OFF

ON

HIGH

LOW

OFF

< 2 V_BAT

X

ON

www.onsemi.com

22

System Wake-up

Load Low-level

software

Determine USB

power available

Battery

Installed?

NO

HALT

YES

Set Safety

Register

Set IINLIM per USB

power available,

reset IO_LEVEL and

set IOCHARGE bits

NO

Set TMR_RST bit

every 10 sec.

DEADBAT

bit SET?

2 minutes

elapsed?

NO

YES

Set all charge

parameters

SET

DEADBAT bit

YES

NO

Load full

functionality

POK_B = 0?

YES

Figure 37. Recommended Host Software Sequence when Booting with Dead Battery

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23

Battery Temperature (NTC) Monitor

The host processor can disable temperature-driven control

of charging parameters by w riting 1 to the TEMP_DIS bit.

Since TEMP_DIS is reset w henever the IC resets its

registers, the temperature controls are enforced w henever

the IC is auto-charging, since auto-charge is alw ays

preceeded by a reset of registers.

The FAN5404X reduces the maximum charge current and

termination voltage if an NTC measuring battery temperature

(T_BAT) indicates that it is outside the fast-charging limits (T2

to T3), as described in the JEITA specification¹. There are

four temperature thresholds that change battery charger

operation: T1, T2, T3, and T4, show n in Table 10.

To disable the thermistor circuit, tie the NTC pin to GND.

Before enabling the charger, the IC tests to see if NTC is

shorted to GND. If NTC is shorted to GND, no thermistor

readings occur and the NTC_OK and NTC1-NTC4 is reset.

Table 10. Battery Temperature Thresholds

For use w ith 10 kΩ NTC, β = 3380, and R_REF= 10 kΩ.

The IC first measures the NTC immediately prior to entering

any PWM charging state, then measures the NTC once per

second, updating the result in NTC1-NTC4 bits (Reg

12H[3:0]).

Threshold

Temperature

% of V_REF

73.9

T1

T2

T3

T4

0°C

10°C

45°C

60°C

64.6

32.9

Table 13. NTC1-NTC4 Decoding

23.3

T_BAT(°C)

NTC4 NTC3 NTC2 NTC1

Above T4

1

0

1

0

1

0

1

0

Table 11. Charge Parametersvs. T_BAT

T_BAT(°C) I_CHARGE

Betw een T3 and T4

Betw een T2 and T3

Betw een T1 and T2

Below T1

V_FLOAT

Below T1

Charging to VBAT Disabled

I_OCHARGE/ 2⁽¹¹⁾

Betw een T1 and T2

Betw een T2 and T3

Betw een T3 and T4

Above T4

4.0 V

V_OREG

4.0 V

I_OCHARGE

I_OCHARGE/ 2⁽¹¹⁾

Charging to VBAT Disabled

Note:

11. If I_OCHARGEis programmed to less than 650 mA, the

charge current is limited to 340 mA.

Thermistors w ith other β values can be used, w ith some shift

in the corresponding temperature threshold, as show n in

Table 12.

Table 12. Thermistor Temperature Thresholds

R_REF= R_THRMat 25°C

Parameter

Various Thermistors

R_THRM(25°C)

10 kΩ

3380

0°C

10 kΩ

3940

3°C

47 kΩ

4050

6

100 kΩ

4250

8

β

T1

T2

T3

T4

10°C

45°C

60°C

12°C

42°C

55°C

13

14

41

40

53

51

1

Japan Electronics and Information Technology Industries

Association (JEITA) and Battery Association of Japan. “A Guide to

the Safe Use of Secondary Lithium Ion Batteries in Notebook-type

Personal Computers,” April 28, 2007.

www.onsemi.com

24

Flow Charts

VBUS POR

HZ or

DISABLE Pin

set?

T32Sec

Armed?

YES

NO

YES

V_BAT> V_LOWV

NO

YES

Ready State

HZ, or

DISABLE Pin

set?

YES

HZ State

T32Sec

Armed?

NO

YES

Charge State

Reset all registers

Start T_32SEC

NO

Figure 38. Charger V_BUSPOR Flow Chart

PWM = OFF

Ready State

Q4, Q5 = ON

RUN

T32Sec

NO

VBAT > VLOWV?

YES

HZ or

DISABLE Pin

set?

YES

HZ_STATE

NO

T32Sec

Armed?

NO

Charge State

YES

Figure 39. Ready State Flow Chart

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25

NO

CHARGE STATE

FIRST TIME?

YES

NO

YES

Linear Charging

Reset Safety reg

YES

V_BAT< V_SHORT

Enable PWM

Battery

YES

NO

Present?

YES

NO

Timer

Enable PWM

YES

CE# = 1

NO

CE# = 1

Enunciate

battery absent

fault

Running?

NO

IDLE State

Battery absent

behavior?

NO

ON

V_BAT< V_BATMIN

OFF

YES

Protection

switch closed?

YES

NO

IDLE State

Enable PWM

charging

Enable PowerPath

charging

NO

Battery Removed

Battery

NO

Reset charge

parameters &

Safety Regs

Present?

T_15MINT.O. or

[T_32ST.O. and

FAN54041] ?

I_OUT< I_TERM

and TE = 1

NO

YES

Indicate Charge

Complete

YES

PWM ON

VBUS OK?

NO

EOC = 1

Q4 and Q5 OFF

Indicate timer fault

NO

V_BAT

<

NO

V_OREG–V_RCH

?

Indicate VBUS

Fault

Disable PWM for

2 seconds

IDLE State

YES

CHARGE

STATE

Figure 40. Charge State Flow Chart

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26

PWM = OFF

Q4, Q5 = ON

HZ State

DIS

Reset T15min

if running

HIGH

LOW

Stop T32Sec

Run T32Sec

NO

HZ_MODE or

DIS pin set?

YES

VBAT > VLOWV?

YES

NO

Timer

Armed?

NO

IDLE STATE

YES

Start timer and GOTO

Charge State

Figure 41. HZ State

PWM = OFF

Q4, Q5 = ON

IDLE State

T32Sec

Armed?

NO

YES

HZ or

DISABLE Pin

set?

Charge State

NO

YES

HZ STATE

Figure 42. IDLE State

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27

Charge Start

Start T15MIN

Reset Registers

YES

T32SEC

Expired?

NO

Start T32SEC

Stop T15MIN

YES

NO

T15MIN

Active?

I²C Write

Received?

T15MIN

Continue

Charging

YES

NO

Expired?

Timer Fault

PWM = OFF

YES

Figure 43. Timer Flow Chart for FAN54040, FAN54042, FAN54047

Charge Start

from Host control

Timer Fault

Stop PWM and

Reset Registers

T32SEC

Expired?

Reset

T32SEC

Charge

NO

YES

NO

TMR_RST

Bit Set?

YES

Figure 44. Timer Flow Chart for FAN54041

Input Current Limiting

For the FAN54041, no charging occurs automatically at

VBUS POR, so the input current limit is established by the

I_BUSLIMbits.

To minimize charging time w ithout overloading VBUS current

limitations, the IC’s input current limit can be programmed by

the I_BUSLIMbits (REG1[7:6]).

VBUS Control loop

Table 14. Input Current Limit

The IC includes a control loop that limits input current in

case a current-limited source is supplying V_BUS

.

I_BUSLIMREG1[7:6]

Input Current Limit

100 mA

The control increases the charging current until either:

00

01

10

11

500 mA

.

I

_BUSLIMor I_OCHARGEis reached OR

V

_BUS=V_BUSLIM

.

800 mA

No Limit

If V_BUScollapses to V_BUSLIM, the VBUS loop reduces its

current to keep V_BUS=V_BUSLIM. When the VBUS control loop

is limiting the charge current, the VLIM bit (REG5[3]) is set.

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28

Table 15. V_BUSLimit as Functionof VBUSLIM Bits

(REG5[2:0])

Table 17. V_SAFE(V_OREGLimit) asFunction of VSAFE

Bits (REG6[3:0])

V_BUSLIM(REG5[2:0])

VSAFE (REG6[3:0])

DEC

BIN

HEX

V_BUSLIM

OREG Max. VOREG

DEC

BIN

HEX

(REG2[7:2])

Max.

4.20

4.22

4.24

4.26

4.28

4.30

4.32

4.34

4.36

4.38

4.40

4.42

4.44

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

4.213

4.293

4.373

4.453

4.533

4.613

4.693

4.773

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

0

1

100011

100100

2

100101

3

100110

4

100111

5

101000

6

101001

7

101010

8

101011

SafetySettings

9

101100

The IC contains a SAFETY register (REG6) that prevents

the values in OREG (REG2[7:2]) and IOCHARGE

(REG4[7:4]) from exceeding the values of the VSAFE and

ISAFE values.

10

11

A

B

C-F

101101

101110

12-15 1100-1111

101111-110010

After V_BATrises above V_SHORT, the SAFETY register is

loaded w ith its default value and may be w ritten to only

before w riting to any other register. The same 8-bit value

should be w ritten to the Safety register tw ice to set the

register value. After w riting to any other register, the

Thermal Regulation and Protection

When the IC’s junction temperature reaches T_CF(about 120°C),

the charger reduces its output current to 550 mA to prevent

overheating. If the temperature increases beyond T_SHUTDOWN

SAFETY register is locked until V_BATfalls below V_SHORT

.

;

The ISAFE (REG6[7:4]) and VSAFE (REG6[3:0]) registers

establish values that limit the maximum values of I_OCHARGE

and V_OREGused by the control logic. If the host attempts to

w rite a value higher than VSAFE or ISAFE to OREG or

IOCHARGE, respectively; the VSAFE, ISAFE value appears

as the OREG, IOCHARGE register value, respectively.

charging is suspended, the FAULT bits are set to 101, and

STAT is pulsed HIGH. In Suspend Mode, all timers stop and the

state of the IC’s logic is preserved. Charging resumes at

programmed current after the die cools to about 120°C.

Additional θ_JAdata points, measured using the FAN54040

evaluation board, are given in Table 18 (measured w ith

T_A=25°C). Note that as pow er dissipation increases, the

effective θ_JAdecreases due to the larger difference betw een

the die temperature and ambient.

Table 16. Maximum I_OCHARGEas Function of ISAFE

Bits (REG6[7:4])

DEC

BIN

HEX

I_OCHARGE(MAX)(mA)

Table 18. Evaluation Board Measured θ_JA

0

0000

0001

0

1

550

650

Power (W)

θ_JA

1

0.504

54°C/W

50°C/W

46°C/W

2

0010

2

750

0.844

3

0011

3

850

1.506

4

0100

4

950

5

0101

5

1,050

1,150

1,250

1,350

1,450

1,550

6

0110

6

7

8

0111

7

1000

8

9

1001

9

10-15

1010-1111

A-F

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29

Battery Detection DuringCharging

Charge Mode Input SupplyProtection

SleepMode

When V_BUSfalls below V_BAT+ V_SLPand V_BUSis above V_IN(MIN),

the IC enters Sleep Mode to prevent the battery from

draining into VBUS. During Sleep Mode, reverse current is

disabled by body sw itching Q1.

The IC can detect the presence, absence, or removal of a

battery if the termination bit (TE) is set and CE# = 0. During

normal charging, once V_BATis close to V_OREGand the charge

current falls below I_TERM; the PWM charger continues to

provide pow er to SYS and Q4 is turned off. It then turns on a

discharge current, I_DETECT, for t_DETECT. If V_BATis still above

V_OREG– V_RCH, the battery is present and the IC sets the

STATUS bits to 10 (Charge Done). If V_BATis below V_OREG

V_RCH, the battery is absent and the IC:

–

Input Supply Low-Voltage Detection

The IC continuously monitors V_BUSduring charging. If V_BUS

falls below V_IN(MIN), the IC:

1. Sets the charging parameters to their default values.

1. Terminates charging

2. Sets the FAULT bits to 111 (Battery Absent) and sets

the NOBAT bit.

2. Pulses the STAT pin, sets the STATUS bits to 11, and

sets the FAULT bits to 011.

3. If EOC=0, the IC turns off the PWM for t_INT, then

resumes charging. If the battery is still absent, the

If V_BUSrecovers above the V_IN(MIN)rising threshold after time

t_INT(about tw o seconds), the charging process is repeated.

This function prevents the USB pow er bus from collapsing or

oscillating w hen the IC is connected to a suspended USB

port or a low -current-capable OTG device.

battery absent fault is then re-enunciated every t_INT

.

4. If EOC = 1, the PWM remains on to provide pow er to

SYS, but charge termination and the battery absent test

are performed every t_INT

.

Input Over-Voltage Detection

When the V_BUSexceeds VBUS_OVP, the IC:

Linear Charging

If the battery voltage is below the short-circuit threshold

(V_SHORT); a linear current source, I_SHORT, charges V_BATuntil

1. Turns off Q3

V_BAT> V_SHORT

.

2. Suspends charging

For I_BUSLIMsettings of 100 mA or 500 mA, the linear charging

current is typically 13 mA. For higher I_BUSLIMsettings, the

linear charging current is increased to 30 mA.

3. Sets the FAULT bits to 001, sets the STATUS bits to

11, and pulses the STAT pin.

When V_BUSfalls about 100 mV below VBUS_OVP, the fault is

cleared and charging resumes after V_BUSis revalidated

(see VBUS POR / Non-Compliant Charger Rejection).

Charger Status / Fault Status

The STAT pin indicates the operating condition of the IC and

provides a fault indicator for interrupt driven systems.

VBUS Short While Charging

Table 19. STAT Pin Function

If VBUS is shorted w ith a very low impedance w hile the IC is

charging w ith I_BUSLIMIT=100 mA, the IC may not meet

datasheet specifications until pow er is removed. To trigger

this condition, V_BUSmust be driven from 5 V to GND w ith a

high slew rate. Achieving this slew rate requires a 0 Ω short

to the USB cable less than 10 cm from the connector.

EN_STAT

Charge State

STAT Pin

0

X

1

X

OPEN

LOW

Normal Conditions

Charging

128 µs Pulse,

then OPEN

SYS Short During Discharge / Supplemental Mode

Caution should be taken to ensure the SYS pin is not

shorted w hen connected to a battery. This condition can

induce high current flow through the BATFET (Q4) until the

battery’s ow n safety circuit trips. The resulting high current

can damage the IC.

X

Fault (Charging or Boost)

The FAULT bits (R0[2:0]) indicate the type of fault in Charge

Mode (see Table 28).

Production Test Mode (PTM)

Charge Mode BatteryDetection & Protection

V_BATOver-Voltage Protection

PTM provides 4.2 V at up to 2.3 A to VBAT w hen V_BUS

5.5 V ±5%.

=

The OREG voltage regulation loop prevents V_BATf rom

overshooting V_OREGby more than 50 mV w hen the battery is

removed. When the PWM charger runs w ith no battery, the

TE bit is not set and a battery is inserted that is charged to a

voltage higher than V_OREG; PWM pulses stop. If no further

pulses occur for 30 ms, the IC sets the FAULT bits to 100,

sets the STATUS bits to 11, and pulses the STAT pin.

The IC enters PTM w hen the PROD bit is set and the

NOBAT bit is HIGH, indicating that the IC has detected

battery absence. A battery absence detection test after

VBUS POR is performed automatically for FAN54040,

FAN54042, and FAN54047 only.

A battery-absent detection test can be performed at any time

by setting the TE bit, setting V_OREGto at least 4.0 V, then

resetting the CE# bit. If no battery is present; charge

termination occurs, follow ed by a battery absent test, w hich

sets the NOBAT bit. Battery-absence detection is completed

w ithin 500 ms from the time that CE# is set.

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30

In PTM, GA TE is LOW, Q4 and Q5 are on, and all auxiliary

control loops are disabled. Only the OREG loop is active,

w hich controls V_BATto 4.2 V, regardless of the OREG

register setting. Thermal shutdow n remains active.

The “droop” caused by the output resistance w hen a load is

applied allow s the regulator to respond smoothly to load

transients w ith no undershoot from the load line. This can be

seen in Figure 33 and Figure 45.

400

360

320

280

240

200

During PTM, high current pulses (load currents greater than

1.5 A) must be limited to 20% duty cycle w ith a minimum

period of 10 ms.

Charge Mode Control Bits

Setting either HZ_MODE through I²C or DIS pin to HIGH

disables the charger, puts the IC into High-Impedance Mode,

and stops t_32S. If V_BAT< V_LOWVw hile in High-Impedance

Mode, t_32Sbegins running and, w hen it overflow s, all

registers (except SAFETY) reset, w hich enables t_15MIN

charging on versions w ith the 15-minute timer if DIS=0.

When t_15MINoverflow s, the IC enters High-Impedance Mode

(IDLE). A new charge cycle can only be initiated through I²C

or VBUS POR.

2.0

2.5

3.0

3.5

4.0

4.5

Battery Voltage, VBAT (V)

Setting the RESET bit clears all registers. If HZ_MODE bit

w as set w hen the RESET bit is set, this bit is also cleared,

but the t_32Stimer is not started and the IC remains in High-

Impedance Mode.

Figure 45. Output Resistance (R_OUT

)

V_BUSas a function of I_LOADcan be computed w hen the

regulator is in PWM Mode (continuous conduction) as:

V_OUT= 5.07 − R_OUT•I_LOAD

EQ. 1

EQ. 2

EQ. 3

Table 20. DIS Pin andHZ_MODE Bit Functionality

Charging

ENA BLE

DIS Pin

HZ_MODE

At V_BAT=3.0 V and I_LOAD=300 mA, V _BUSdrops to:

V_OUT= 5.07 − 0.30 • 0.3 = 4.98V

0

X

1

0

1

X

DISABLE

At V_BAT=3.6 V and I_LOAD=500 mA, V _BUSdrops to:

V_OUT= 5.07 − 0.24 • 0.5 = 4.95V

Raising the DIS pin stops t_32Sfrom advancing, but does not

reset it. If the DIS pin is raised during t_15MINcharging, the

t_15MINtimer is reset. CE# determines w hether charging to

V_BATis enabled or not.

PFM Mode

If V_BUS> V REF_BOOST(nominally 5.07 V) w hen the minimum

off-time ends, the regulator enters PFM Mode. Boost pulses

are inhibited until V_BUS< V REF_BOOST. The minimum on-time

is increased to enable the output to pump up sufficiently w ith

each PFM boost pulse. Therefore, the regulator behaves like

a constant on-time regulator, w ith the bottom of its output

voltage ripple at 5.07 V in PFM Mode.

Boost Mode

Boost Mode can be enabled if the IC is in 32-Second Mode

by setting the OPA _MODE bit HIGH and clearing the

HZ_MODE bit.

Table 21. Enabling Boost

HZ_MODE

OPA_MODE

BOOST

Enabled

Disabled

Table 22. Boost PWM Operating States

0

1

X

0

Mode

LIN

Description

Linear Startup

Boost Soft-Start

Invoked When

V_BAT> V_BUS

X

SS

V_BUS< V_BST

V_BAT> UVLO_BSTand

SS Completed

To remain in Boost Mode, the TMR_RST must be set by the

host before the t_32Stimer times out. If t_32Stimes out in Boost

Mode; the IC resets all registers, pulses the STAT pin, sets

the FAULT bits to 110, and resets the BOOST bit. VBUS

POR or reading R0 clears the fault condition.

BST

Boost Operating Mode

Startup

When the boost regulator is shut dow n, current flow is

prevented from V_BATto V_BUS, as w ell as reverse flow from

Boost PWM Control

V_BUSto V_BAT

.

The IC uses a minimum on-time and computed minimum off-

time to regulate V_BUS. The regulator achieves excellent

transient response by employing current-mode modulation.

This technique causes the regulator to exhibit a load line.

During PWM Mode, the output voltage drops slightly as the

input current rises. With a constant V_BAT, this appears as a

constant output resistance.

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31

LIN State

Monitor Registers (Reg10H, Reg11H)

When EN rises, if V_BAT> UVLO_BST; the regulator first

attempts to bring PMID w ithin 400 mV of V_BATusing an

internal 450 mA current source from VBAT (LIN State). If

PMID has not achieved V_BAT– 400 mV after 560 µs, a

FAULT state is initiated.

Additional status monitoring bits enable the host processor

to have more visibility into the status of the IC. The monitor

bits are real-time status indicators and are not internally

debounced or otherw ise time qualified.

The state of the MONITOR register bits listed in High-

Impedance Mode is valid only w hen V_BUSis valid.

SS State

When PMID > V_BAT– 400 mV , the boost regulator begins

sw itching w ith a reduced peak current limit of about 50% of

its normal current limit. The output slew s up until V_BUSis

w ithin 5% of its setpoint; at w hich time, the regulation loop is

closed and the current limit is set to 100%.

I²C Interface

The FAN5404X’s serial interface is compatible w ith

Standard, Fast, Fast Plus, and High-Speed Mode I²C bus

specifications. The FAN5404X SCL line is an input and the

SDA line is a bi-directional open-drain output; it can only pull

dow n the bus w hen active. The SDA line only pulls LOW

during data reads and w hen signaling ACK. All data is

shifted in MSB (bit 7) first.

If the output fails to achieve 95% of its setpoint (V_BST) w ithin

128 µs, the current limit is increased to 100%. If the output

fails to achieve 95% of its setpoint after this second 384 µs

period, a fault state is initiated.

Slave Address

Table 24. I²C Slave AddressByte

BST State

This is the normal operating mode of the regulator. The

7

6

5

4

3

2

1

0

regulator uses

a minimum t_OFF-minimum t_ONmodulation

V

IN

1

0

1

0

1

scheme. The minimum t_OFFis proportional to

, w hich

R/W

V

OUT

keeps the regulator’s sw itching frequency reasonably

constant in CCM. t_ON(MIN)is proportional to V_BATand is a

higher value if the inductor current reached 0 before t_OFF(MIN)

in the prior cycle.

In hex notation, the slave address assumes a 0 LSB. The

hex slave address is D6H for all parts in the family. Other

slave addresses can be accommodated upon request.

Contact an ON Semiconductor representative.

To ensure V_BUSdoes not overshoot the regulation point, the

Bus Timing

boost sw itch remains off as long as V_FB> V_REF(BST)

.

As show n in Figure 46, data is normally transferred w hen

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

Boost Faults

If a BOOST fault occurs:

1. The STAT pin pulses.

2. OPA_MODE bit is reset.

Data change allowed

3. The pow er stage is in High-Impedance Mode.

4. The FAULT bits (REG0[2:0]) are set per Table 23.

SDA

Restart After Boost Faults

t_H

OPA_MODE is reset on boost faults. Boost Mode can only

be re-enabled by setting the OPA_MODE bit.

t_SU

SCL

Table 23. Fault Bits During Boost Mode

Figure 46. Data Transfer Timing

Fault Bit

Fault Description

B2 B1 B0

Each bus transaction begins and ends w ith SDA and SCL

HIGH. A transaction begins w ith a START condition, w hich is

defined as SDA transitioning from 1 to 0 w ith SCL HIGH, as

show n in Figure 47

0

1

Normal (no fault)

V_BUS> VBUS_OVP

V_BUSfails to achieve the voltage required to

advance to the next state during soft-start

or sustained (>50 µs) current limit during the

t_HD;STA

Slave Address

MS Bit

SDA

SCL

0

1

0

BST state.

0

1

0

1

0

1

0

1

V_BAT< UVLO_BST

NA: This code does not appear.

Thermal shutdow n

Figure 47. Start Bit

Timer fault; all registers reset.

NA: This code does not appear.

www.onsemi.com

32

Transactions end w ith a STOP condition, w hich is SDA

transitioning from 0 to 1 w ith SCL HIGH, as show n in Figure 48.

Read and Write Transactions

The figures below outline the sequences for data read and

w rite. Bus control is signified by the shading of the packet,

Slave Releases

Master Drives

t_HD;STO

Slave Drives Bus

ACK(0) or

NACK(1)

defined as

All addresses and data are MSB first.

and

.

SDA

SCL

Table 25. Bit Definitionsfor Figure 50 - Figure 53

Symbol

Definition

S

START, see Figure 47

Figure 48. Stop Bit

ACK. The slave drives SDA to 0 to acknow ledge

the preceding packet.

During a read from the FAN5404X (Figure 51), the master

issues a Repeated Start after sending the register address

and before resending the slave address. The Repeated Start

is a 1-to-0 transition on SDA w hile SCL is HIGH, as show n in

Figure 49.

A

NACK. The slave sends a 1 to NACK the

preceding packet.

R

P

Repeated START, see Figure 49

STOP, see Figure 48

High-Speed (HS) Mode

The protocols for High-Speed (HS), Low -Speed (LS), and

Fast-Speed (FS) Modes are identical except the bus speed

f or HS Mode is 3.4 MHz. HS Mode is entered w hen the bus

master sends the HS master code 00001XXX after a start

condition. The master code is sent in Fast or Fast Plus Mode

(less than 1 MHz clock); slaves do not ACK the

transmission.

Multi-Byte (Sequential) Read and Write

Transactions

Sequential Write (Figure 52)

The Slave Address, Reg Addr address, and the first data

byte are transmitted to the FAN5404x in the same w ay as in

a byte w rite (Figure 50). How ever, instead of generating a

Stop condition, the master transmits additional bytes that are

w ritten to consecutive sequential registers after the falling

edge of the eighth bit. After the last byte w ritten and its ACK

bit received, the master issues a STOP bit. The IC contains

an 8-bit counter that increments the address pointer after

each byte is w ritten.

The master then generates

a repeated start condition

(Figure 49) that causes all slaves on the bus to sw itch to HS

Mode. The master then sends I²C packets, as described

above, using the HS Mode clock rate and timing.

The bus remains in HS Mode until a stop bit (Figure 48) is

sent by the master. While in HS Mode, packets are

separated by repeated start conditions (Figure 49).

Sequential Read(Figure 53)

Slave Releases

t_SU;STA

t_HD;STA

Sequential reads are initiated in the same w ay as a single-

byte read (Figure 51), except that once the slave transmits

the first data byte, the master issues an acknow ledge

instead of a STOP condition. This directs the slave’s I²C

logic to transmit the next sequentially addressed 8-bit w ord.

The FAN5404x contains an 8-bit counter that increments the

address pointer after each byte is read, w hich allow s the entire

memory contents to be read during one I²C transaction.

ACK(0) or

NACK(1)

SLADDR

MS Bit

SDA

SCL

Figure 49. Repeated Start Timing

Figure 50. Single-Byte Write Transaction

Figure 51. Single-Byte Read Transaction

Figure 52. Multi-Byte (Sequential) Write Transaction

Figure 53. Multi-Byte (Sequential) Read Transaction

www.onsemi.com

33

Register Descriptions

The eight user-accessible IC registers are defined in Table 26.

Table 26. I²C Register Address

Register

Address Bits

Name

REG#

7

6

5

4

3

2

1

0

CONTROL0

CONTROL1

OREG

0H

1H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2H

IC_INFO

3H

IBAT

4H

VBUS_CONTROL

SAFETY

5H

6H

POST_CHARGING

MONITOR0

MONITOR1

NTC

7H

10H

11H

12H

13H

WD_CONTROL

Table 27. Register Bit Definitions

This table defines the operation of each register bit for all IC versions. Default values are in bold text.

Bit

Name

Value Type

Description

Register Address: 00

CONTROL0

Default Value=0100 0000

Writing a 1 resets the t_32Stimer; w riting a 0 has no effect.

Reading this bit alw ays returns 0

7

6

TMR_RST

EN_STA T

0

W

Prevents STAT pin from going LOW during charging; STAT pin still pulses to

enunciate faults

0

R/W

1

00

01

10

11

0

Enables STAT pin to be LOW w hen IC is charging

R

Ready

PWM Enabled. Charging is occurring if CE# = 0.

5:4

STAT

Charge done

Fault

R

IC is not in Boost Mode

IC is in Boost Mode

3

BOOST

FAULT

1

2:0

Table 28. Charger Mode Faults

Fault Bit

Fault Description

2

1

0

Normal (No Fault)

VBUS OVP

0

1

0

1

0

1

0

1

0

1

0

1

Sleep Mode

Poor Input Source

Battery OVP

Thermal Shutdow n

Timer Fault

No Battery

For Boost Mode faults, see Table 23

www.onsemi.com

34

Bit

Name

Value Type

Description

CONTROL1

Register Address:01

Default Value=0011 0X00

7:6

I_BUSLIM

R/W Input current limit; defaults to 00 (100 mA), see Table 14

00

01

10

11

0

R/W 3.4 V

3.5 V

5:4

V_LOWV

Weak battery voltage threshold

3.6 V

3.7 V

R/W Disable charge current termination

Enable charge current termination

3

2

TE

1

0

R/W Charging enabled. Default for FAN54040, FAN54042, FAN54047.

Charging disabled. Default for FAN54041, FAN54045 , FAN54046.

R/W Not High-Impedance Mode

CE#

1

0

1

0

HZ_MODE

1

High-Impedance Mode

See Table 21

R/W Charge Mode

0

OPA_MODE

1

Boost Mode

OREG

Register Address:02

Default Value=0000 1000 (08H)

Charger output “float” voltage; programmable from 3.5 to 4.44 V in 20 mV

increments; defaults to 000010 (3.54 V), see Table 4.

7:2

OREG

R/W

Indicates that the IC detected a dead battery after VBUS_POR and that the charger

has not yet completed the three steps to ensure that the battery’s protection sw itch

is closed if a battery is present, as described in the Dead Battery section on page

21. Writing a 0 to this bit is ignored.

0

The IC sets this bit to 1 if any of the follow ing are true:

1

DBAT_B

1. Dead Battery (V_BAT< V_SHORT) w as not detected at VBUS_POR.

2. The IC has completed the three steps to ensure that if the battery is

present, the battery’s protection sw itch has closed, as described in the

Dead Battery section on page 21.

1

If the host sets this bit w hile the IC is charging the battery and DBAT_B is LOW,

the three steps are aborted and normal Pow er Path or PWM charging proceeds.

If no battery is detected w hen a full battery (end of charge) is reached, PWM stops,

R/W Q4 and Q5 remain on, and the charger automatically restarts after tw o seconds w ith

0

TE and CE# bits unchanged.

0

EOC

If no battery is detected w hen a full battery (end of charge) is reached, the PWM

charger stays on, allow ing the host processor to continue to run w ith no battery.

1

IC_INFO

7:6

Register Address:03

Default Value=100X XXXX

Vendor Code

10

R

Identifies ON Semiconductor as the IC supplier

5:3

PN

Part number bits, see the Ordering Info on page 2

2:0

REV

IC Revision, revision 1.X, w here X is the decimal of these three bits

IBAT

Register Address:04

Default Value=1000 0001 (81H)

Writing a 1 resets all registers, except the Safety register (Reg6), to their defaults:

w riting a 0 has no effect; read returns 1

7

RESET

1

W

6:3

2:0

IOCHARGE

ITERM

Table 5

Table 6

R/W Programs the maximum charge current, see Table 5

R/W Sets the current used for charging termination, see Table 6

www.onsemi.com

35

Bit

Name

Value Type

Description

VBUS_CONT ROL

Register Address:05

Default Value=001X X100

7

Reserved

0

1

0

1

R

This bit alw ays returns 0

R/W Charger operates in Normal Mode.

Charger operates in Production Test Mode.

6

PROD

R/W Battery current is controlled by IOCHARGE bits.

Battery current control is set to 340 mA.

5

4

3

IO_LEV EL

1 Indicates that V_BUSis above 4.4 V (rising) or 3.8 V (falling). When VBUS_CON

changes from 0 to 1, a STAT pulse occurs.

VBUS_CON

R

0

1

R

VBUS control loop is not active (V_BUSis able to stay above V_BUSLIM

VBUS control loop is active and V_BUSis being regulated to V_BUSLIM

)

SP

2:0

SAFETY

7:4

VBUSLIM

Table 15 R/W VBUS control voltage reference, see Table 15

Register Address:06

Default Value=0100 0000 (40H)

ISAFE

Table 16 R/W Sets the maximum I_OCHARGEvalue used by the control circuit, see Table 16

Table 17 R/W Sets the maximum V_OREGused by the control circuit, see Table 17

3:0

VSAFE

POST_CHARGING

Register Address:07

Default Value=0000 0001 (01H)

These bits determine w hether a battery absent detection w ill be performed w hen

the NTC reading indicates out-of-range w hen charging.

[7:6]

When NTC goes out-of-range

00

01

10

Always do battery absent detection

7:6

BDET

R/W

Disable detection in Normal Mode

Disable detection w hen Reg FA = B5 (PWM running after charge

done.

11

NTC out-of-range in charge done does not cause battery absent

detection.

After charger termination, in the charge done state, these bits control VBUS loading

to improve detection of AC pow er removal from the AC adapter.

[5:4]

VBUS loading in Charge Done State:

5:4

VBUS_LOAD

0

R/W

00

01

10

11

None

Load VBUS for 4 ms every tw o seconds

Load VBUS for 131 ms every tw o seconds

Load VBUS for 135 ms every tw o seconds

0

1

R/W Post charging or background charging feature is disabled

Post charging or background charging feature is enabled

3

PC_EN

PC_IT

2:0

Table 6

R/W Sets the termination current for post or underground charging, see Table 6

MONITOR0

Register Address:10H (16)

Default Value=XXX0 XXXX (XXH)

7

6

5

ITERM_CMP

R

ITERM comparator output, 1 w hen I_CHARGE> I_TERM reference

Output of VBAT comparator, 1 w hen V_BAT< V_BUS

VBAT_CMP

LINCHG

1 w hen 30 mA linear charger ON (V_BAT< V_SHORT

)

Thermal regulation comparator, 1 w hen the die temperature is greater than 120°C.

During this condition, charge current is limited to 340 mA.

4

T_120

R

3

2

1

ICHG

IBUS

R

0 indicates the ICHARGE loop is controlling the battery charge current.

0 indicates the IBUS (input current) loop is controlling the battery charge current.

1 indicates V_BUShas passed validation and is capable of charging.

VBUS_VALID

1 indicates the constant-voltage loop (OREG) is controlling the charger and all

current limiting loops have released.

0

CV

R

www.onsemi.com

36

Bit

Name

Value Type

Description

MONITOR1

Register Address:11H (17)

GATE pin is LOW, Q5 is driven on.

GATE pin is HIGH, Q5 is off.

Default Value=XX1X XXXX

0

1

0

1

0

1

0

1

0

1

0

R

7

GATE

VBAT

POK_B

V_BAT< V_BATMINin PP charging, V_BAT< V_LOWin PWM charging

V_BAT> V_BATMINin PP charging, V_BAT> V_LOWin PWM charging

POK_B Pin is LOW.

6

5

R/W

R

POK_B Pin is HIGH. Writing to this bit sets the POK_B pin.

DIS pin is LOW.

4

3

2

DIS_LEV EL

NOBAT

DIS pin is HIGH.

R

Battery absence

Battery presence

Post charging (background charging) is under progress.

Post charging (background charging) is not under progress.

These bits alw ays return 0.

PC_ON

1:0

NTC

7:6

Reserved

Register Address:12H (18)

Default Value=000X XXXX

Reserved

TEMP_ DIS

00

These bits alw ays return 0.

0

R/W NTC Temperature measurement results affect charge parameters.

5

NTC Temperature measurement results do not affect charge. Temperature

measurements continue to be updated every second in the NTC1-4 monitor bits.

1

4

3

2

1

0

NTC_OK

NTC4

R

0 if NTC is either shorted to GND, open, or shorted to REF.

1 indicates that NTC is above the T4 threshold.

1 indicates that NTC is above the T3 threshold.

NTC3

See Table 10 – Table 13

NTC2

1 indicates that NTC is above the T2 threshold.

1 indicates that NTC is above the T1 threshold.

Register Address:13H (19)

NTC1

WD_CONTROL

Default Value = 0110 1100

7

6:5

4

Reserved

0

11

0

R/W These bits do not change the function of the IC.

Reserved

3

1

0

V REG is of f

R/W

2

1

EN_VREG

1

V REG is on

0

Watchdog timer (T32S) operation normal

WD_DIS

R/W

1

Watchdog timer (T32S) disabled.

0

Reserved

0

R

This bit alw ays returns 0

RESTART

Register Address:FAH (250)

Default Value = 1111 1111

Writing B5H restarts charging w hen the IC is in the charge done state. This register

reads back FF.

7:0

RESTA RT

W

www.onsemi.com

37

PCB Layout Recommendation

Bypass capacitors should be placed as close to the IC as

possible. In particular, the total loop length for CMID should

be minimized to reduce overshoot and ringing on the SW,

PMID, and VBUS pins. Pow er and ground pins should be

routed directly to their bypass capacitors using the top

copper layer. The copper area connecting to the IC should

be maximized to improve thermal performance. See the

layout recommendations in Figure 54.

Figure 54. PCB Layout Recommendation

Product-Specific Dimensions

Product

D

E

X

Y

FAN5404XUCX

2.40 ±0.030

2.00 ±0.030

0.180

0.380

www.onsemi.com

38

Physical Dimensions

0.03 C

2X

F

E

A

1.60

0.40

B

(Ø0.200)

Cu Pad

A1

BALL A1

INDEX AREA

(Ø0.300)

Solder Mask

1.60

D

0.40

0.03 C

RECOMMENDED LAND PATTERN

(NSMD PAD TYPE)

2X

TOP VIEW

0.06 C

0.625

0.378±0.018

0.208±0.021

0.547

0.05 C

E

C

SEATING PLANE

D

SIDE VIEWS

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

1.60

0.40

0.005

C A B

Ø0.260±0.02

25X

C. DIMENSIONS AND TOLERANCE

PER ASMEY14.5M, 1994.

E

D

C

B

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

1.60

0.40

(Y) ±0.018

F

A

E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS

±39 MICRONS (547-625 MICRONS).

2

3

5

4

1

(X) ±0.018

F. FOR DIMENSIONS D, E, X, AND Y SEE

TABLE BELOW.

BOTTOM VIEW

G. DRAWING FILNAME: MKT-UC025AArev2.

Figure 55. 25-Ball WLCSP, 5X5 Array, 0.4 mm Pitch, 250 µm Ball

www.onsemi.com

39

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40


型号：	FAN54046UCX-T
厂家：	ONSEMI
描述：	USB-OTG，1.55A，锂离子开关充电器，带电源路径和 2.3A 生产测试报告开关测试
文件：	总40页 (文件大小：1513K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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