FAN54110UCX_技术文档

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June 2017

FAN54110

USB-Compatible Single-Cell Li-Ion Linear Charger with DBP

Description

Features

The FAN54110 is a USB-compatible single-cell, linear Li-Ion

charger with support for Dead Battery Provision (DBP).

Fully Integrated, High-Efficiency Charger for Single-Cell Li-

Ion and Li-Polymer Battery Packs

The device employs Over-Voltage Protection (OVP) circuitry

to protect the device, load, and battery. The maximum

charge current is rated at 1 A and can be programmed from

100 mA to 1 A through the I²C interface, optimizing charging

for various battery sizes.

Charge Voltage Accuracy:

0.5% at 25°C

1% from -30 to 85°C

+0/-10% Charge Current Regulation Accuracy

28 V Absolute Maximum Input Voltage

1 A Maximum Charge Current

Dynamic Input Voltage Control ensures weak power sources

can be used to power the FAN54110 without collapsing to an

unusable input voltage for charging.

Support for Dead Battery Provision (DBP) of

USB Battery Charging Specification 1.2

Programmable through I²C Interface with

Fast Mode (400 kHz) Compatibility

Open-drain status pins, STAT and POK_B, provide a status

of charging and input power. The STAT pin also notifies the

system processor when an I²C interrupt occurs so the

processor can take action based on the interrupt.

–

Input Current

Fast-Charge / Termination Current

Charger Voltage

The FAN54110 conforms to the constraints of the Dead

Battery Provision within the BC1.2 specification, including a

30-minute timer that cannot exceed 45 minutes.

Safety Timer with Reset Control

Weak Input Sources Accommodated by Reducing Charging

Current to Maintain Minimum V_BUSVoltage

The FAN54110 is designed to be stable with space-saving

ceramic capacitors. The FAN54110 is available in a 15-

bump, 0.4 mm pitch, WLCSP package.

Low Reverse Leakage to Prevent Battery Drain to VBUS

Applications

VBUS

C_BUS

VBAT

Smart Phones

+

SYSTEM

LOAD

Battery

C_BAT

Tablets

PGND

LDO

Portable Media Players

Li Ion Powered Devices

SDA

SCL

DIS

FAN54110

C_LDO

ILIM

DBP

STAT

D+

POK_B

Figure 1.

Typical Application

www.onsemi.com

FAN54110 • Rev. 2

Ordering Information

Packing

Method

Part Number

PN Reg00h[4:3]

00

Temperature Range

Package

15-Bump, Wafer-Level Chip-Scale

(WLCSP), 0.4 mm Pitch

FAN54110UCX

-40°C to 85°C

Tape and Reel

Recommended External Components

Component

Description

Vendor

Parameter Min. Typ.⁽1⁾Unit

Murata GRM188R61E105K

TDK C1608X5R1E105M

C_BUS

C

0.5

1.0

1.0 F, 10%, 25 V, X5R, 0603

F

Murata GRM188R60J475K

TDK C1608X5R0J475K

(2)

C_BAT

C

2.0

0.4

4.7

1.0

4.7 F, 10%, 6.3 V, X5R, 0603

1.0 F, 10%, 6.3 V, X5R, 0402

F

C_LDO

Murata GRM155R60J105M

Notes:

1. Does not reflect effects of bias, tolerance, and temperature.

2. C_BATis placed as close to the charger IC as possible. A minimum requirement of 30 F distributed system capacitance

(C_SYS) is parallel with C_BAT, but can be located further from the IC.

Block Diagram

VBUS

LDO

C_BUS

Q2

Q3

1F

C_LDO

CHARGE

PUMP

LDO 3.3 V

VBUS

POK/OVP

Q1

CHARGE

CONTROL

Q1A

Q1B

V_CC

V_CCI/O

VBAT

C_BAT

DAC

VREF

+

SYSTEM

LOAD

C_SYS

Battery

SDA

SCL

DBP

ILIM

DIS

I²C

OSC

STAT

INTERFACE

LOGIC

AND

CONTROL

POK_B

D+

Figure 2.

IC and System Block Diagram

www.onsemi.com

FAN54110 • Rev. 2

2

D+

A1

DBP

A2

SCL

A3

SDA

A4

B4

C4

D4

A3

A2

B2

C2

D2

A1

B1

C1

D1

VBUS

STAT

B4

B1

C1

B2

PGND

VBAT LDO

C3

D3

C2

C3

C4

DIS POK_B

ILIM

D4

D1

D2

D3

Bottom View

Top View

Pin Definitions

Pin #

Name

Description

Connect to the USB connector D+ pin

A1

D+

Charger IC sources 0.6 V in CHARGE state when DBP is LOW. Otherwise, this pin is 3-state.

Dead Battery Provision Disable

A2

DBP

Pull HIGH to disable charger D+ output. Internal pull-down resistor.

I²C Interface Serial Clock

I²C Interface Serial Data

A3

A4

SCL

SDA

Charger Input Voltage

B1, B2

VBUS

Bypass with a 1 F capacitor directly to PGND.

Status / Interrupt

Open-drain output indicating charge status. The IC pulls this pin LOW when charge is in process. High

impedance when charging is done or charger is disabled. Also used as system interrupt. 128 s pulse

and then high impedance indicates to the system a fault has occurred.

B4

STAT

Power Ground

C1, C2

C4

PGND

LDO

DIS

Power return for gate drive and power transistors.

3.3 V LDO

3.3 V regulator output.

Active-High Disable

D1

When pulled HIGH, the charger is disabled. Internal pull-down resistor.

VBUS Power-OK Monitor

D2

POK_B

Open-drain output that is pulled LOW when V_BUSis greater than the V_BUSvalidation threshold and lower

than V_BUSOVP. High impedance when outside this range.

Battery Voltage

C3, D3

D4

VBAT

ILIM

Connect to the positive (+) terminal of the battery pack. Bypass locally with a 4.7 F capacitor to

PGND.

Input Current Limit

This pin sets the input current limit for t_30MINcharging. Internal pull-down resistor.

www.onsemi.com

FAN54110 • Rev. 2

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable

above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,

extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute

maximum ratings are stress ratings only.

Symbol

V_BUS

Parameter

Continuous

Min.

-1.2

-0.3

Max.

Unit

V

Voltage on VBUS

Voltage on VBAT

Voltage on Other Pins

28.0

V_BAT

6.5

(3)

V

V_O

V

Human Body Model per ANSI/ESDA/JEDEC JS-001-2012

(All Pins)

2000

Electrostatic Discharge

Protection Level

ESD

V

Charged Device Model per JESD22-C101 (All Pins)

IEC 61000-4-2 System (VBUS and D+ Pins)

JESD78 – Class 1, 25°C

1500

8000

±100

LU

T_J

Latch Up

mA

°C

Junction Temperature

Storage Temperature

-40

-65

+150

+260

T_STG

T_L

Lead Soldering Temperature, 10 Seconds

Note:

3. Lesser of 6.5 V or V_BAT+ 0.3 V.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device. Recommended operating conditions

are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend

exceeding them or designing to absolute maximum ratings.

Symbol

Parameter

Min.

Max.

Unit

V_IN

T_A

T_J

Supply Voltage

4

6

V

Ambient Temperature

Junction Temperature

-30

+85

+125

°C

Thermal Properties

Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer

2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature

T_J(max)at a given ambient temperature T_A. For measured data, see the Evaluation Board Measured JA table.

Symbol

_JA

Parameter

Junction-to-Ambient Thermal Resistance

Junction-to-PCB Thermal Resistance

Typical

60

Unit

°C/W

20

_JB

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FAN54110 • Rev. 2

4

Electrical Specifications

Unless otherwise specified: circuit of Figure 2, recommended operating temperature range for T_Jand T_A, V_BUS=5.0 V, DIS=0

(Charger Mode operation), SCL, SDA=0 or 1.8 V; typical values are for T_J=25°C.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Power Supplies

V_IN(MIN)1V_BUSInput Voltage Rising

V_IN(MIN)2Minimum V_BUSduring Charge

t_{VBUS_VALID}V_BUSValidation Time

To Initiate and Pass VBUS Validation

VBUS Regulation Loop is Off

4.18 4.40 4.65

2.95 3.10 3.35

32

V

ms

%

V_{BUS_REF}V_BUSRegulation Loop Threshold

Relative to VBUS_REF Setting

DIS=1

-5

+5

I_VBUS

I_DIS

V_BUSCurrent

890 1,000

A

mA

V_BUSDischarge Current

VBUS Removal or Validation

40

63

90

V_BAT=4. 2 V, VBUS=Open, SDA=SCL=1. 8 V,

No I²C Traffic, -30°C < T_J< 85°C

5

10

Battery Discharge Current during

SLEEP State

I_BAT

A

V_BAT=4. 2 V, VBUS=Open, SDA=SCL=0 V,

-30°C < T_J< 85°C

3

8

2

I_{BUS_LKG}VBAT to VBUS Leakage Current

Charger Voltage Regulation

Charge Voltage Range

V_BAT=4. 2 V, V_BUS=0 V, -30°C < T_J< 85°C

<1

A

3.38

-0.5

-1

4.44

+0.5

+1

V

T_J=25°C

V_OREG=4. 2 V

-30°C < T_J< 85°C

V_OREGCharge Voltage Accuracy

%

T_J=25°C

3.38 V < V_OREG< 4.44 V

-30°C < T_J< 85°C

-1

+1

-1.5

10

V_BATOvershoot Pulsed Load⁽4⁾

Fast Charging Current Regulation

Output Charge Current Range

See V_BATOvershoot Test

2

mV

100

-10

-15

1,000 mA

I_OCHRG

I_OCHRG> 350 mA

I_OCHRG< 350 mA

-5

-7

0

Charge Current Accuracy

(measured at V_BUS, includes I_CHRG+ I_REG

%

0

)

Logic Levels: DIS, SDA, SCL, ILIM, DBP

V_IH

V_IL

High-Level Input Voltage

Low-Level Input Voltage

1.05

V

0.4

0.01 1.00

0.9 1.4

V

Input Tied to GND or Greater of V_BATor Valid

V_BUS

I_IN

Input Bias Current

A

ILIM, DBP, DIS Pull-Down

Resistance

R_PD

0.6

M

VBAT Overshoot Test

In the figure below, I_OCHARGE=1 A (1111), V_OREG=4.2 V. I_LOADt_R=t_F=1 s. Charge current prior to load transient=

20mV

 100mA

200m

Overshoot is measured as the peak voltage above V_BATlevel prior to the load transient application. C_SYSrepresents the

distributed system capacitance across the VBAT terminals and is assumed to be a minimum of 30 F.

VBAT

C_SYS

30F

C_BAT

1A

FAN54110

I_LOAD

200m

ESR

+

V_CELL

4.18V

BATTERY MODEL

Figure 3.

V_BATOvershoot Test Condition

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FAN54110 • Rev. 2

5

Electrical Specifications

Unless otherwise specified: circuit of Figure 2, recommended operating temperature range for T_Jand T_A, V_BUS=5.0 V, DIS=0

(Charger Mode operation), SCL, SDA=0 or 1.8 V; typical values are for T_J=25°C.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Charge Termination Detection

Termination Current Range

V_BAT> V_OREG– V_RCH, V_BUS> V_{BUS_REF}

I_TERM> 80 mA

20

-10

-20

170

+10

+20

mA

%

I_TERM

Termination Current Accuracy

I_TERM< 80 mA

Battery Recharge Threshold

V_RCHRecharge Threshold

3. 3 V Linear Regulator

V_BATFalling by V_RCHbelow V_OREGThreshold

I_REGfrom 0 to 40 mA

100

mV

V

V_REG

3.3 V Regulator Output

3.10 3.30 3.50

DBP Output

V_{DBP_SRC}Voltage on D+ pin

I_{DBP_OFF}Leakage Current

STAT / POK_B Output

0.51 0.60 0.69

V

DBP=0, I_LOADon D+ from 0 to 250 A

DBP=1, V_D+from 0 to 3. 6 V

-1

+1

µA

V_OL

I_OH

STAT / POK_B Output Low

STAT / POK_B Leakage Current

I=10 mA

V=5 V

0.4

1

V

µA

Battery Detection

Battery Detection Current before

Charge Done (Sink Current)

t_DETECTBattery Detection Time

I_DETECT

Begins after Termination Detected

-1

mA

ms

262

Power Switches (see Error! Reference source not found.)

Q1 R_DS(ON)Q1 On Resistance

175

110

260

170

m

Q2 R_DS(ON)Q2 On Resistance

Protection and Timers

V_BUSOVP Accuracy

Hysteresis

V_BUSRising

V_BUSFalling

V_BATRising

V_BATFalling

V_BAT< V_SHORT

-7

+7

%

mV

V

VBUS_OVP

V_SHORT

100

Battery Short-Circuit Threshold

Hysteresis

2.10 2.27 2.40

120

mV

mA

I_SHORT

Linear Charging Current

85

2.2

130

93

100

Production Test Mode Current

Limit

I_LIM(PTM)

A

Thermal Shutdown Threshold⁽4⁾

Re-Enable Threshold⁽4⁾

Thermal Regulation Accuracy⁽4⁾

32-Second Timer

T_JRising

145

T_CF

160

+10

T_SHUTDWN

°C

T_JFalling

T_CF

t_32S

Relative to T_CFSetting

-10

°C

s

20.5 24.3 28.0

t_30MIN

t_OSC

30-Minute Timer

30

38

45

15

min

%

125 kHz Oscillator Tolerance

Timing in all Sequencing Diagrams

-15

Note:

4. Guaranteed by design; not tested in production.

www.onsemi.com

FAN54110 • Rev. 2

6

I²C Timing Specifications

Guaranteed by design.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Standard Mode

Fast Mode

100

400

kHz

f_SCL

SCL Clock Frequency

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

3400

1700

4.7

Bus-Free Time between STOP

and START Conditions

t_BUF

s

Fast Mode

1.3

Standard Mode

4

s

START or Repeated START

Hold Time

t_HD;STA

Fast Mode

600

160

4.7

1.3

160

320

4

ns

High-Speed Mode

Standard Mode

s

Fast Mode

t_LOW

SCL LOW Period

SCL HIGH Period

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

ns

s

Fast Mode

600

60

t_HIGH

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

ns

120

4.7

600

160

250

100

10

s

t_SU;STA

Repeated START Setup Time

Data Setup Time

Fast Mode

ns

High-Speed Mode

Standard Mode

t_SU;DAT

Fast Mode

ns

s

ns

High-Speed Mode

Standard Mode

0

3.45

900

70

Fast Mode

t_HD;DAT

Data Hold Time

SCL Rise Time

SCL Fall Time

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

150

1000

300

80

20+0.1C_B

10

Fast Mode

t_RCL

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

20

160

300

40

20+0.1C_B

10

Fast Mode

t_FCL

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

20

80

20+0.1C_B

10

1000

300

80

SDA Rise Time

Fast Mode

t_RDA

Rise Time of SCL after a

Repeated START Condition

and after ACK Bit

t_RCL1

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

20

160

Continued on the following page…

www.onsemi.com

FAN54110 • Rev. 2

7

I²C Timing Specifications

Guaranteed by design.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Standard Mode

Fast Mode

20+0.1C_B

300

80

20+0.1C_B

t_FDA

SDA Fall Time

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

10

20

160

4

s

ns

pF

t_SU;STO

Stop Condition Setup Time

Fast Mode

600

160

High-Speed Mode

C_B

Capacitive Load for SDA, SCL

400

Timing Diagram

t_F

t_SU;STA

t_BUF

SDA

t_R

t_SU;DAT

t_HD;STO

t_HIGH

t_HD;DAT

SCL

t_LOW

t_HD;STA

REPEATED

START

STOP

START

Figure 4.

I²C Interface Timing for Fast and Slow Modes

www.onsemi.com

FAN54110 • Rev. 2

8

Typical Characteristics

Unless otherwise specified; circuit of Figure 2, V_OREG=4.2 V, V_BUS=5.0 V, and T_A=25°C.

1.0

0

-2

- 40C

+25C

+55C

+85C

- 30C

+25C

+85C

0.5

-4

0.0

-6

-0.5

-1.0

-8

-10

3.54 3.63 3.72 3.81 3.90 3.99 4.08 4.17 4.26 4.35 4.44

100

200

300

400

500

600

700

800

900

1000

OREG Setpoint (V)

IOCHARGE Setpoint (mA)

Figure 5.

I_OCHRGAccuracy Over-Temperature, 3.7 V_BAT

Figure 6.

OREG Accuracy Over-Temperature,

I_BAT=100 mA

10

8

3.9

3.6

3.3

3.0

2.7

-30C

+25C

+85C

-30C

+25C

+85C

6

4

2

0

2.4

0

2.4

2.7

3.0

3.3

3.6

3.9

4.2

4.5

20

40

60

80

100

Battery Voltage (V)

LDO Load Current (mA)

Figure 7.

LDO Load Regulation, V_OREG=V_BAT=4.2 V

Figure 8.

HZ / Sleep Mode Battery Discharge Current,

V_BUSOpen, DIS=SDA=SCL=0 V

Figure 9.

Charger Startup at V_BUSPlug-In, 500 mA

Figure 10. Charger Startup at VBUS Plug-In Using

150 mA Current Limited Source, 3.2 V_BAT, 500 mA

I_OCHRG, 1 kLDO Load, ILIM=DBP=1.8 V

I_OCHRG, 3.2 V_BAT, 1 k LDO Load, ILIM=DBP=1.8 V

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FAN54110 • Rev. 2

9

Typical Characteristics

Unless otherwise specified; circuit of Figure 2, V_OREG=4.2 V, V_BUS=5.0 V, and T_A=25°C.

Figure 11. Charger Startup Using HZ Bit Reset, 3.7 V_BAT

,

Figure 12. Charger Startup at V_BUSPlug-In with

Dead Battery (Protection Switch Open), 1 kΩ LDO

Load, ILIM=DBP=0 V

500 mA I_OCHRG, 1 kΩ LDO Load, ILIM=DBP=1.8 V

Figure 14. VBUS OVP Response while Charging,

3.7 V_BAT, 500 mA I_OCHRG, 1 kΩ LDO Load,

ILIM=DBP=1.8 V

Figure 13. Charger Startup at V_BUSPlug-In with

No Battery, 300 Ω LDO Load, ILIM=DBP=0 V

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FAN54110 • Rev. 2

10

Typical Characteristics

Unless otherwise specified; circuit of Figure 2, V_OREG=4.2 V, V_BUS=5.0 V, and T_A=25°C.

Figure 15. Battery Removal/Insertion while Charging,

Figure 16. Battery Removal/Insertion while Charging,

3.7 V_BAT, 500 mA _IOCHRG, ILIM=DBP=1.8 V, ITERM_DIS=1

3.7 V_BAT, 500 mA I_OCHRG, ILIM=DBP=1.8 V,

ITERM_DIS=0

Figure 17. 1.2 A Load Pulse, t_R=t_F=5 s, 4.19 V_BAT

,

Figure 18. 1.2 A Load Pulse, t_R=t_F=5 s, 500 mA Current

1.0 A I_OCHRG

Limited Source, 4.2 V_BAT, 1.0 A_IOCHRG,4.32 V_{BUS_REF}

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FAN54110 • Rev. 2

11

Charger Circuit Details

Basic Operation

VBUS Insertion

The FAN54110 is

a USB-compatible single-cell Li-Ion

When the IC detects that V_BUShas risen above V_IN(MIN)1

,

charger with support for Dead Battery Provision (DBP) and a

maximum charge current rated at 1 A.

adapter validation and battery voltage detection will occur

before charging begins. To pass validation, V_BUSmust

remain above VIN(MIN)1 and below VBUSOVP for tVBUS_VALID

before the IC initiates charging. Refer to Figure 20 and

Figure 21 for details.

The FAN54110 conforms to all the requirements for the DBP

within the BC1. 2 specifications, including a 30-minute timer

that cannot exceed 45 minutes.

The FAN54110 is designed to be stable with space-saving

ceramic capacitors and is available in a 15-bump, 0.4 mm

pitch, WLCSP.

If V_BUSis validated, the POK_B pin pulls LOW and an

interrupt is issued to indicate to the system that VBUS is

connected. This point is considered to be VBUS_POR.

If VBUS fails validation, the POK_B pin remains HIGH and

an interrupt is issued. Re-validation is attempted every two

seconds.

Setting the HZ_MODE bit or DIS pin prevents validation from

occurring after VBUS rises above V_IN(MIN)1, but, VBUS

validation will be performed prior to entering Charge State

from any state where the charger is off.

VBUS_OVP

4.4V

VBUS

LDO

STAT

POK_B

VBUS_CON

load_vbat

load_vbus

STATE

WAIT

4ms

CHARGE

SLEEP

DEBOUNCE SYS_CAP DISCHARGE VBUS_VAL

32ms 256ms 32ms

VBUS_POR

Figure 19. VBUS Plug-In Timing: DIS=0, HZ_MODE=0, DBP=1

4.4V

VBUS

LDO

VBUS_CON

STAT

POK_B

SLEEP

DEBOUNCE

32ms

HZ_STATE

VBUS_POR

STATE

Figure 20. VBUS Plug-In Timing:

DIS=1 or (DBP=1 and HZ_MODE=1)

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FAN54110 • Rev. 2

12

The current drawn from VBUS is determined by either the

state of ILIM pin or the I_OCHARGEprogramming.

VBUS POR and DBP Charging

If the DBP pin is HIGH at VBUS_POR, the IC operates in

accordance with its I²C register settings and starts the t_32s

timer when charging begins. This is the normal operating

mode for the FAN54110.

Charging Stages

Figure 21 shows the different charging stages when a

battery is present and discharged below 2.25 V.

If the DBP pin is LOW at VBUS_POR or the DBP pin

transitions from HIGH to LOW when VBUS is valid, the

FAN54110:

PRE-CHARGE is when the battery voltage is below V_SHORT

and a current of I_SHORTis used to charge the battery above

VSHORT. This stage is typically used to recover a deeply

discharge battery with its protection switch open.

.

Resets its registers to default values

CURRENT REGULATION increases charging current

considerably above I_SHORTto a programmable I_OCHARGE(Reg

03h[7:4]) level.

Charges with its charge current limit set by the state of

the ILIM pin:

.

ILIM= LOW, I_OCHRG=100 mA

ILIM= HIGH, I_OCHRG=350 mA

VOLTAGE REGULATION occurs during charging when

VBAT reaches VOREG (Reg4[5:0]). The current charging

the battery is reduced, limited by the battery’s ESR and its

internal cell voltage.

.

Starts the t_30MINtimer

Sources 0.6 V to the D+ pin

.

If ITERM_DIS (Reg03h[0])=0, charging current

decreases to ITERM (Reg03h[3:0]), where Charge

Termination occurs.

BC1.2 and USB 2.0 allow a portable device (defined as a

device with a battery) with a dead battery to take a maximum

of 100 mA from the USB VBUS line for a maximum of 45

minutes as long as the portable device forces the D+ line to

0.6 V typical.

.

If ITERM_DIS=1 (default configuration), charging will

continue past I_TERMuntil current decreases to 0A, where

the part will remain in Charge Mode with the t_32Stimer

running.

Once DBP transitions from LOW to HIGH, D+ is three-stated

and charge parameters may be programmed by the host.

Charge current remains controlled by the state of the ILIM

pin and the t_30MINtimer continues running until the first I²C

write occurs; at which time, charge current is controlled by

the I_OCHARGE(Reg03h[7:4]) bits and the timer changes to

V_OREG

I_CHARGE

I_OCHARGE

t_32S

.

The ILIM and DBP pins are internally pulled down and there is

typically nothing to force them HIGH at this point due to the

processor / system not yet being awake. When the t_30MINtimer

expires, the FAN54110 removes the 0.6 V from D+ and stops

charging. The D+ pin is three-stated when DBP is HIGH.

I_TERM

V_SHORT

I_SHORT

Battery Absent at VBUS Insertion

Before charging begins, if V_BATis below V_SHORT, the

FAN54110 will determine whether the battery is absent or

present.

PRE-

CHARGE

CURRENT REGULATION

VOLTAGE

REGULATION

Figure 21. Typical Charge Profile

To accomplish this, the IC temporarily raises V_OREGto 4.0 V

after V_BAThas risen above V_SHORT. If V_BATremains below

3.7 V for more than 128 ms, the battery is present. If V_BATis

above 3.7 V after 128 ms, the battery is assumed absent.

Charge Termination

During Voltage Regulation, charging continues until the I_BAT

< I_TERM. If ITERM_DIS=0, charging stops and the t_32Stimer

continues counting. The STAT pin remains LOW until the IC

determines whether the I_BAT< I_TERMcondition was caused by

VBUS removal, Battery Removal, or by the battery being

fully charged (Charge Termination).

If battery absence is detected, all registers are reset to their

default values, the NOBAT bit is set, and an interrupt is

generated. Also, it is assumed the DBP pin is LOW since the

system was without a power source prior to plug in. The

FAN54110 will provide power to the system with STAT HIGH

in DBP Mode until otherwise instructed through I²C

commands. This allows the host processor an opportunity to

detect charger type and negotiate with the USB host for

higher current.

During Charge Termination, the t_32Stimer will continue

running, but, if it expires will not reset all registers until

Recharge. Setting the TMR_RST bit (Reg8[7]) during

Charge Termination will reset the t_32Stimer. Refer to the

Timers section for more details.

The IC continues to provide current, provided that:

.

a timer (t_30MINor t_32S) is running

Recharge from Charge Termination

HZ_MODE (Reg=01h[6])=0 and DIS=LOW.

During Charge Termination, if V_BATfalls by V_RCHbelow

V_OREG, charging starts again.

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FAN54110 • Rev. 2

13

A recharge condition de-bounce time of 60 ms is used to

prevent transient battery load currents (such as GSM current

pulses) from triggering auto-recharge unnecessarily.

ceases and the part will enter the IDLE State where all

registers are reset. Only a new VBUS_POR will return the IC

to charging.

During unattended charging, if the DBP pin transitions from

LOW to HIGH (due to the host waking up and controlling the

charger):

Battery Removal during Charging

When ITERM_DIS=0 and the charge current drops below

the I_TERMsetting, a load current (I_DETECT) is placed on V_BATin

order to determine if the battery was removed during

charging. If the battery is determined to be present, the load

is removed, and Charge Done State is entered. If the battery

is determined to be absent, the IC enters a fault state, which

waits with the charger disabled for two seconds, then re-

starts the charger validation process.

1- If V_BAT<V_SHORT, the t_30MINtimer will continue running.

2- If V_BAT>V_SHORT, the t_30MINtimer will continue running

until the first I²C write. Then the t_30MINwill stop and

the t_32Stimer is started.

VBUS Over-Voltage

.

If the battery is determined to be present, the load is

removed, and Charge Termination occurs.

The FAN54110 contains programmable Over-Voltage

Protection (OVP) on VBUS, ranging from 6.5 V to 8.0 V, as

specified in the V_BUSOVP(Reg01h[2:1) bits with a default

setting of 7 V. If OVP is detected, the FAN54110 terminates

charging functionality if charging is active when OVP is

detected. The FAN54110 interrupts the host when the OVP

event occurs and sets the OVP_FLAG bit.

.

If the battery is determined to be absent, charging is

disabled, all registers except ITERM_DIS are reset to

default values, the NOBAT interrupt bit is set, and the

STAT pin rises. After 2s, the charger will restart

validation and if the battery is re-inserted, the IC will

return to Charge State.

Dynamic Input Voltage Control (DIVC)

V_BUSis typically 5 V +5% / -10%, depending on the charging

current. If the FAN54110 is programmed to a higher current

than the charger can support, a regulation control actively

regulates the charging current to maintain at least 4.32V

(typical) on VBUS. This level is controlled via the

VBUS_REF (Reg02h[3:2]) bits. The FAN54110 reduces the

charging current to ensure V_BUSis maintained above the

V_{BUS_REF}setting. The DIVC regulation loop is enabled by

default and disabled with the VBUS_REG (Reg01h[5]) bit.

In response to V_BATcollapsing, though, the system

electronics have likely lowered the DBP pin which will reset

all registers. As a result, the ITERM_DIS bit will be reset to

1, which will set the unloaded VBAT pin to output 3.54V (the

default V_OREGsetting) and place the IC in Charge State with

the NOBAT bit remaining set until the next VBUS_POR

validation.

VBUS Removal and SLEEP

When V_BUSfalls below either V_IN(MIN)2or V_BAT, the IC ceases

charging, the POK_B pin sets HIGH, and an interrupt occurs

to indicate to the system that VBUS has been removed. The

IC then enters the Sleep State.

If DIVC is disabled, the charging cycle stops when V_BUSfalls

below the V_BUSvalid falling threshold (V_INMIN2) or below V_BAT

.

Charging remains stopped until V_BUSrises above the rising

V_BUSvalid threshold (V_INMIN1) and stays above this threshold.

LDO

Thermal Regulation and Shutdown

The FAN54110 provides a regulated 3.3 V LDO output when

a valid V_BUScondition exists to power the USB PHY.

Regulation occurs within 5 ms of valid V_BUSbeing applied.

The thermal regulation loop is enabled if the junction

temperature reaches the threshold defined by the T_CF

(Reg02h[5:4]) bits. When T_CFis reached, the FAN54110

reduces the charging current to 90 mA until the junction

LDO load current is derived from V_BUSand is subject to the

I_OCHARGEsetting / limit. Available battery charging current is

reduced by the LDO load current.

temperature falls below T_CF

. Charge current is then

incremented in 1 ms steps until the I_OCHRGlevel is reached.

This algorithm allows for the fastest recovery from a thermal

regulation event while averaging a current that keeps the

Charger/Battery/System Protections

temperature below T_CF

.

Timers

The FAN54110 terminates charging completely if the

junction temperature exceeds T_SHUTDWN(145°C).

There are two timers on the FAN54110; t_32Sand the t_30MIN

.

The t_32Stimer is for normal operation where the DBP pin is

HIGH. When charging begins after a VBUS_POR with the

DBP pin HIGH, the t_32Stimer is started. If the t_32Stimer is

allowed to expire, charging ceases and the part will enter the

IDLE State where all registers are reset. A write to any

register can return the IC to charging. To avoid a t_32Stimer

fault, the host must reset the timer by periodically setting the

TMR_RST (Reg08h[7]) bit before it expires.

In both cases, the temperature event is indicated via the

TREG_FLAG

and

TSD_FLAG

bits

in

the

FAULT_INTERRUPT (Reg05h) register. Recovery from

either event is indicated via the OT_RECOV bit in the same

register.

Additional _JAdata points, measured using the FAN54110

evaluation board, are given in the table below (measured

with T_A=25°C). Note that as power dissipation increases, the

effective _JAdecreases due to the larger difference between

the die temperature and ambient.

The t_30MINtimer is for unattended charging. If V_BAT<V_SHORT

the device is assumed to be dead and the DBP pin is,

therefore, LOW. When charging begins after a VBUS_POR

with V_BAT<V_SHORTand the DBP pin LOW, the t_30MINtimer is

started. If the t_30MINtimer is allowed to expire, charging

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FAN54110 • Rev. 2

14

STAT Pin

Table 1. Evaluation Board Measured _JA

The STAT pin is used to indicate charging status, as well as

to signal the host processor of a change in the status of the

IC or system.

Power (W)

ϴ_JA

0. 504

0. 844

1. 506

54°C/W

50°C/W

46°C/W

The static state of the STAT pin is determined by whether

the IC is charging a battery:

Table 3. STAT Pin Static State

NOBAT

Production Test Mode

Production Test Mode (PTM) provides power for the system

from the USB port. This eliminates the burden of having an

attached battery during production line testing.

CHARGER

STAT Pin

(Reg05h[0])

ON

OFF

X

0

X

1

LOW

HIGH

PTM is enabled when the PTM_EN bit is HIGH and when

the battery is absent (NOBAT (Reg05h[0])=1). In PTM, Q1

(see Figure 2) is turned on, but it is current limited to about

2.5 A. V_BATis initially regulated to the default V_OREGsetting of

3.54 V in PTM. However, VBAT can be programmed to

output any V_OREGfrom 3.38 V to 4.44 V, as specified in the

VOREG (Reg04h[5:0]) bits.

The STAT pin emits a 128 s LOW pulse whenever an

unmasked interrupt event occurs and the INTERRUPT

(Reg01h[0]) bit is reset to “0”.

Care should be taken to limit the RMS current in PTM Mode.

Thermal regulation (T_CF) and thermal shutdown are enabled

in PTM.

Any interrupt pulse that occurs while STAT is statically LOW

is preceded by 128 s of STAT HIGH, as shown below.

Charging

Interrupt (stops charging)

STAT

Charging Status and Interrupt Reporting

The STAT and POK_B pins are used to indicate to the host

the presence or absence of a valid charging source,

charging status, as well as fault status.

Interrupt (charging resumes)

STAT

Figure 22. STAT Interrupt Pulse Behavior

Masking the STAT Pin Interrupt

The

FAULT_INTERRUPT

(Reg05h[7:0])

and

STATUS_INTERRUPT (Reg07h[7:5]) bits have associated

MASK bits and there is a general INTERRUPT (Reg01h[0])

bit. This bit is set when any interrupt occurs, even if the

occurring fault is masked. While this bit is set to 1, all

subsequent STAT pulses are prevented. Reading this

register clears the bit.

The FAULT_INTERRUPT and STATUS_INTERRUPT

register bits have associated MASK bits located in

Reg06h[7:0] and Reg07h[3:1] that will mask STAT pin

pulses.

The FAULT_INTERRUPT and STATUS_INTERRUPT

registers and the INTERRUPT (Reg01h[0]) bit should be

read and cleared on every STAT pin rising edge and POK_B

pin falling edge to ensure that all faults, masked or

otherwise, as well as adapter presence changes are

immediately available to the host.

When a mask bit is set and an event occurs:

.

The

associated

FAULT_INTERRUPT

or

STATUS_INTERRUPT bit is set

The INTERRUPT bit is set

The STAT pin will not pulse

.

POK_B Pin

The POK_B pin is used to indicate the presence or absence

of a valid charging source to the host processor.

INTERRUPT (Reg01h[0]) Bit

When bits in the FAULT_INTERRUPT

STATUS_INTERRUPT register are set, the INTERRUPT

(Reg01h[0]) bit is set before the falling edge of STAT.

and

Table 2. POK_B Pin State

POK_B

HIGH

Charging Source

absent or not valid

If additional interrupt conditions occur before the host

clears the INTERRUPT bit by reading Reg01h, the STAT

pin does not pulse.

LOW

V_INMIN(1)<V_BUS<VBUS_OVP

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FAN54110 • Rev. 2

15

I²C Interface

A transaction ends with a STOP condition, which is defined

as SDA transitioning from 0 to 1 with SCL HIGH, as shown

in Figure 25.

The serial interface is compatible with Standard Mode and

Fast Mode I²C bus specifications. The SCL line is an input

and the SDA line is a bi-directional open-drain output; it can

only pull down the bus when active. The SDA line only pulls

LOW during data reads and when signaling ACK. All data is

shifted in MSB (bit 7) first.

Slave Releases

Master Drives

t_HD;STO

ACK(0) or

NACK(1)

SDA

SCL

Slave Address

Table 4. I²C Slave Address Byte

Figure 25. Stop Bit

7

6

5

4

3

2

1

0

During a read from the FAN54110, the master issues a

Repeated Start after sending the register address and before

resending the slave address. The Repeated Start is a 1-to-0

transition on SDA while SCL is HIGH, as shown below.

1

0

1

0

1

R/W

In hex notation, the slave address assumes a 0 LSB. The

hex slave address for the FAN54110 is D6.

Slave Releases

t_SU;STA

t_HD;STA

Bus Timing

ACK(0) or

NACK(1)

SLADDR

MS Bit

SDA

SCL

As shown below, data is normally transferred when SCL is

LOW. Data is clocked in on the rising edge of SCL. Typically,

data transitions at or shortly after the falling edge of SCL to

allow ample time for the data to set up before the next SCL

rising edge.

Figure 26. Repeated Start Timing

Read and Write Transactions

The figures below outline the sequences for data read and

write. Bus control is signified by the shading of the packet,

Slave Drives Bus

defined as

and

.

All addresses and data are MSB first.

Figure 23. Data Transfer Timing

Table 5. Bit Definitions for Write and Read

Transactions

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which is

defined as SDA transitioning from 1 to 0 with SCL HIGH, as

shown below.

Symbol

Definition

START, see Figure 24.

S

ACK. The slave drives SDA to 0 to acknowledge

the preceding packet.

T_HD;STA

Slave Address

MS Bit

A

SDA

NACK. The slave sends a 1 to NACK the

preceding packet.

A

SCL

R

P

Repeated START, see Figure 26

STOP, see Figure 25

Figure 24. Start Bit

Figure 27. Write Transaction

Figure 28. Read Transaction

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FAN54110 • Rev. 2

16

Register Descriptions

Table 6. Register Bit Definitions

Default values are in bold text with VBUS removed and VBAT=3.8V.

Bit

Name

Type

Description

IC_INFO

Register Address: 00h

Default= 100X XXXX (XXh)

100: Identifies ON Semiconductor as the supplier

Part number bits, see the Ordering Info on page 2

IC Revision. Revision is 1.X, where X is the decimal of these 3 bits

7:5 VENDOR

4:3 PN

R

2:0 REV

CHARGE_CTRL1

Register Address: 01h

Default=0011 0010 (32h)

Setting this bit to 1 resets all registers to default values and deactivates t_32S, causing the part to

go to into IDLE State until the next I²C write reactivates t_32S

This bit returns 0 when read.

.

7

RESET

W

0: Charging is enabled.

6

5

HZ_MODE

R/W

1: Charging is disabled.

0: V_BUSregulation loop disabled.

1: V_BUSregulation loop enabled.

VBUS_REG

0: V_BUSregulation loop is enabled and is active (V_BUS=V_{BUS_REF}).

1: V_BUS> V_{BUS_REF}or V_BUSregulation loop is disabled.

4

3

VBUS_LOOP

Reserved

R

This bit returns 0 when read.

When V_BUSis at or above this threshold, a V_BUSOVP fault is enunciated and the charger is

disabled until the fault clears.

Table 7. V_BUSOVPThreshold

[2:1]

00

V_BUSOVPThreshold

2:1 V_BUSOVP

R/W

6.5

7.0

7.5

8.0

01

10

11

A 1 indicates that a fault has occurred. See the Charging Status and Interrupt Reporting

section for details.

0

INTERRUPT

RC

While this bit is set to 1, all subsequent STAT pulses are prevented. Reading this register

clears the bit.

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FAN54110 • Rev. 2

17

CHARGE_CTRL2

Register Address: 02h

0: Normal operation

Default=0010 0111 (27h)

7

6

PTM_EN

Reserved

R/W

1: Production Test Mode is enabled if NOBAT (Reg5[0])=1. See the Production Test Mode

section for details.

R

This bit returns 0 when read.

Temperature threshold at which the current is reduced to allow the device to cool. See the

Thermal Regulation and Shutdown section for details.

Table 8. Temperature Threshold Settings

DEC

BIN

00

T_CF

70

5:4 T_CF

R/W

0

1

2

3

01

85

10

100

120

11

Sets the V_{BUS_REF}threshold.

Table 9. V_{BUS_REF}Threshold

DEC

BIN

00

V_{BUS_REF}

4.22

3:2 VBUS_REF

R/W

0

1

2

3

01

4.32

10

4.37

11

4.46

0: Charging re-starts if V_BAT< V_OREG-V_RCH

1: Charging does not re-start automatically if V_BATdrops.

.

1

0

VRCH_DIS

ITERM_DIS

R/W

0: Charging terminates at the programmed I_TERMlevel.

1: Charging does not terminate at the programmed I_TERMlevel.

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FAN54110 • Rev. 2

18

IBAT

Register Address: 03h

Default=0010 0110 (26h)

Charge current, I_OCHRG, is the maximum current drawn from VBUS during charging. Current

consumed by the 3.3 V LDO, therefore, reduces the current available to charge the battery.

Table 10. I_OCHARGESettings

DEC

0

BIN

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

I_OCHARGE(mA)

100

1

300

2

350

3

400

4

450

5

500

7:4 I_OCHARGE

R/W

6

550

7

600

8

650

9

700

10

11

12

13

14

15

750

800

850

900

950

1000

Table 11. ITERM Settings

DEC

0

BIN

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

ITERM (mA)

20

30

1

2

40

3

50

4

60

5

70

6

80

3:0 ITERM

R/W

7

90

8

100

110

120

130

140

150

160

170

9

10

11

12

13

14

15

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FAN54110 • Rev. 2

19

OREG

Register Address: 04h

Default=0000 1000 (08h)

7:6 Reserved

R

These bits return 0 when read.

Table 12. OREG Settings

DEC

0

BIN

HEX

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

V_OREG

3.38

3.40

3.42

3.44

3.46

3.48

3.50

3.52

3.54

3.56

3.58

3.60

3.62

3.64

3.66

3.68

3.70

3.72

3.74

3.76

3.78

3.80

3.82

3.84

3.86

3.88

3.90

3.92

3.94

3.96

3.98

4.00

DEC

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

BIN

HEX

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

V_OREG

4.02

4.04

4.06

4.08

4.10

4.12

4.14

4.16

4.18

4.20

4.22

4.24

4.26

4.28

4.30

4.32

4.34

4.36

4.38

4.40

4.42

4.44

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

5:0 VOREG

R/W

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FAN54110 • Rev. 2

20

FAULT_INTERRUPT Register Address: 05h

Default=0000 0000 (00h)

A 1 for a given bit indicates that a specific fault has occurred as described in the table below.

Items in blue are transient conditions, whose bits are cleared when this register is read. The

other interrupts herein are not cleared unless the underlying condition has been removed.

See the Charging Status and Interrupt Reporting section for details.

Table 13. Charger Interrupt Conditions

Bit #

FLAG

TSD_FLAG

OVP_FLAG

TREG_FLAG

TC_TO

Interrupt

Thermal shutdown (T_J> 145°C).

7

6

5

4

3

2

1

FAULT

VBUS OVP (over-voltage shutdown).

Charger thermal regulation is active.

T32Sec timer has timed out.

7:0

R

_INTERRUPT

DBP_TO

Dead-Battery (DBP) timer (T30) has timed out.

Die temperature has fallen below 120°C.

VBUS OVP recovery has occurred.

OT_RECOV

OVP_RECOV

Battery absence was detected either at VBUS POR or after

Charge Termination.

0

NOBAT

FAULT_MASK

Register Address: 06h

Default=0000 0000 (00h)

A mask bit of 1 prevents an interrupt pulse from being generated on the STAT pin. The

INTERRUPT (Reg01h[0]) bit and corresponding FAULT_INTERRUPT register bit are still

written.

See the Charging Status and Interrupt Reporting section for details.

Bit #

FLAG

Interrupt

Mask thermal shutdown (T_J> 145°C).

Mask VBUS OVP (over-voltage shutdown).

7

6

5

4

3

2

1

0

TSD_FLAG_M

OVP_FLAG_M

7:0 MASK

R/W

TREG_FLAG_M Mask charger thermal regulation.

TC_TO_M

Mask T32Sec timer time out.

DBP_TO_M

OT_RECOV_M

Mask Dead-Battery (DBP) timer (t30) time out.

Mask Die temperature recovery.

OVP_RECOV_M Mask VBUS OVP recovery.

NOBAT_M

Mask battery absence detection.

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FAN54110 • Rev. 2

21

STATUS_INTERRUPT Default=0100 0000 (40h)

Register Address: 07h

Items in blue are transient conditions, whose bits are cleared when this register is read. The

other interrupts herein are not cleared unless the underlying condition has been removed.

See the Charging Status and Interrupt Reporting section for details.

Table 14. VBUS Interrupt Conditions

Bit #

FLAG

Interrupt Generated

VBUS_CON

1 when OVP>V_BUS>V_IIN(MIN)1at VBUS POR from VBUS Insertion.

0 when VBUS is disconnected.

7:5 VBUS_STAT

R

7

VBUS_CON does not de-assert when a VBUS_OVP condition

occurs after VBUS validation is successful.

6

5

POK_B

State of the POK_B pin

VALIDATION

FAIL

1 indicates VBUS validation is attempted and failed. After a

failure, VBUS validation is attempted every two seconds.

4

Reserved

This bit returns 0 when read.

A mask bit of 1 prevents an interrupt pulse from being generated on the STAT pin. The

INTERRUPT (Reg01h[0]) bit and corresponding VBUS_STAT bit are still written.

See the Charging Status and Interrupt Reporting section for details.

Table 15. VBUS Interrupt Mask Bits

3:1 VBUS_MASK R/W

Bit #

Mask

VBUS_CON MASK

POK_B MASK

3

2

1

VALIDATION FAIL MASK

0

Reserved

R

This bit returns 0 when read.

TMR_RST

Register Address: 08h

Default=0000 0000 (00h)

Setting this bit to 1 resets the t_32stimer, allowing the IC to continue charging under control of

the I²C host.

7

TMR_RST

W

R

This bit returns 0 when read

6:0 Reserved

These bits return 0 when read.

MONITOR0

Register Address: 10h

Default=1000 0010 (82h)

0: I_BAT< I_TERMreference

7

6

5

4

ITERM_CMP

R

1: I_BAT> I_TERMreference

0: V_BUS< V_BAT

1: V_BUS> V_BAT

VBUS_VBAT

VSHORT

0: V_BAT> V_SHORTor IC is not charging.

1: V_BAT< V_SHORTand IC is charging.

0: DIS pin is LOW. This bit always reads 0 when VBUS is disconnected.

1: DIS pin is HIGH.

DIS_LEVEL

R

3:2 Reserved

This bit returns 0 when read.

0: ICHG loop is controlling the charge current.

1: ICHG loop is not limiting the charge current.

1

ICHG

0: Charger is not in Constant Voltage (CV) Mode. Charger is either off or another loop

(VBUS or ICHG) is limiting charge current.

0

CV

R

1: Charger is on and in Constant Voltage (CV) Mode.

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FAN54110 • Rev. 2

22

PCB Layout Recommendations

Bypass capacitors should be placed as close to the IC as possible. All power and ground pins should be routed to their bypass

capacitors using top copper. Copper area connecting to the IC should be maximized to improve thermal performance.

Figure 29. Recommended PCB Layout

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FAN54110 • Rev. 2

23

Physical Dimensions

0.03 C

2X

F

E

A

1.20

0.40

B

(Ø0.200)

Cu Pad

A1

BALL A1

INDEX AREA

1.20 0.40

(Ø0.300)

Solder Mask

D

0.03 C

RECOMMENDED LAND PATTERN

(NSMD PAD TYPE)

2X

TOP VIEW

0.06 C

0.378±0.018

0.208±0.021

0.625

0.547

0.05 C

E

C

SEATING PLANE

D

SIDE VIEWS

NOTES

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

1.20

0.005

C A B

C. DIMENSIONS AND TOLERANCE

PER ASMEY14.5M, 1994.

0.40

Ø0.260±0.02

15X

D

C

B

A

0.40

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

1.20

(Y) ±0.018

F

E. PACKAGE NOMINAL HEIGHT IS

2

3

4

1

586 ± 39 MICRONS (547-625 MICRONS).

(X) ±0.018

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

BOTTOM VIEW

G. DRAWING FILNAME: MKT-UC015AArev1.

Figure 30. 15-Ball WLCSP, 0. 4 mm Pitch, 250 m Balls

Product-Specific Dimensions

D

E

X

Y

1. 560 ±0.030

1. 560 ± 0.030

0.180

Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to verify or obtain the

most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms and conditions, specifically the

warranty therein, which covers ON Semiconductor products.

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FAN54110 • Rev. 2

24


型号：	FAN54110UCX
厂家：	ONSEMI
描述：	Battery Charge Controller, Linear, 1 A, for Small Battery and IoT Applications 电池
文件：	总25页 (文件大小：1657K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN54110UCX [ONSEMI]

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