FAN54511 [ONSEMI]
3.2 A Dual Input, Switch Mode Charger with Power Path;
| 型号： | FAN54511 |
| 厂家： | 
ONSEMI |
| 描述： | 3.2 A Dual Input, Switch Mode Charger with Power Path |
| 文件： | 总61页 (文件大小：6841K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAN54511
3.2 A Dual Input, Switch
Mode Charger with Power
Path
Description
www.onsemi.com
2
The FAN5451x family of chargers includes an I C controlled 3.2 A
USB−compliant switch−mode charger.
To facilitate fast system startup, the IC includes an optimized Power
Path circuit which also accurately measures battery currents during
charging and provides low impedance during discharge.
The charging parameters and operating modes are programmable
VIN
2
PMID
REG
LDO
VBUS
CBUS
C
through an I C Interface. Charge status is reported back to the host
IN
2
CMID
through the I C port and the / STAT pin.
D+ /GPO1
CREG
SYS USB
PHY
The FAN5451x provides battery charging in three modes:
Pre−Charge (IPP), Constant Current (CC) and Constant Voltage (CV).
The charger can automatically restart the charge cycle when the
battery falls below a restart voltage threshold. If the input source is
removed, the IC enters a high−impedance mode, blocking battery
current from leaking to either input.
D−/ GPO2
CLDO1
BOOT
VSYS
VSYS
To
System
CBOOT
D1
SW
L1
RD
SYS
/STAT
CSYS
BAT
FAN5451x
CBAT
ILIM
DIS
BATSNS
NTC
SDA
The FAN5451x is available in a 63−bump, 0.4 mm pitch WLCSP
package.
RREF
REF
CREF
SCL
/INT
Battery
T
+
R
PU
/BUSOK
/INOK
To
PMIC
/SHIP
Features
• Fully Integrated, High−Efficiency Charger for Single−Cell Li−Ion
and Li−Polymer Battery Packs
AGND
PGND
• Power Path Circuit ensures Fast System Startup with a Dead Battery
Figure 1. Typical Application
• 95% Charge Efficiency
• Charge Current Programmable up to 3.2 A
• 10 mV Float Voltage Accuracy
ORDERING INFORMATION
•
5% Charge Current Regulation Accuracy
See detailed ordering and shipping information on page 2 of
this data sheet.
• 5 V, 1.5 A Boost Mode for USB OTG
• 22 V DC Withstand Voltage on VBUS
• 13.25 V Maximum Input Operating Voltage
• −2 V Input Reverse Polarity Protection
Benefits
• Secondary Input for Wireless Charging
• Pin or Software Configurable Hardware Reset for
Quick System Restart
• Battery Temperature Sensing Ensures Safe−To−Charge
Operation (JEITA)
• Dynamic Input Voltage Control (DIVC) for Operation
with Weak Adapters
• USB BC1.2 Compatible
• Programmable 10 mA LDO
• Programmable Safety Timer with Reset Control
• Pin Configurable Ship Mode prevents Battery
Discharge to System Load
• Thermal Shutdown and Programmable Thermal
Regulation
2
• High−Speed I C Interface
(3.4 Mb/s) with Fast Mode Plus Compatibility
Applications
• Smart Phones
• Tablets
• e−Books
• Li Ion Powered Devices
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2018 − Rev. 4
FAN54511/D
FAN54511
Table 1. ORDERING INFORMATION
Part Number
Package
Packing Method
FAN54510AUCX
63 − Bump, Wafer−Level Chip_Scale Package (WLCSP)
0.4 mm Pitch
Tape and Reel
FAN54511AUCX
FAN54511APUCX
FAN54512AUCX
FAN54513AUCX
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Table 2. DEVICE ORDERING INFORMATION
BC1.2
CDP/DCP
BC1.2 SDP
I
Current
I
Current
BUS
BUS
I
PN Bits:
IC_INFO[
5:3]
ILIM
Pin
Control
I
Limit
(ILIM Pin =
HIGH)
Limit
(ILIM Pin =
LOW)
BUS
BUS
Slave
BC1.2
Detection
Current
Limit
Current
Limit
Address
Part Number
Safety
Timer
@1500 mA
FAN54510A
(Note 1)
ON
(D+, D−)
2 min.
@500 mA
1101011_
000
OFF
N/A
N/A
OFF
FAN54511A
1101011_
1101010_
001
001
N/A
N/A
N/A
N/A
ON
ON
500 mA
500 mA
1500 mA
1500 mA
(GPO1,GPO2)
OFF
(GPO1,GPO2)
FAN54511AP
Safety
Timer
FAN54512A
(Note 1)
ON
45 min.
1101011_
1101011_
010
011
OFF
ON
N/A
N/A
(D+, D−)
@100 mA
@1500 mA
OFF
(GPO1,GPO2)
FAN54513A
N/A
N/A
100 mA
1500 mA
1. Contact ON for these options.
www.onsemi.com
2
FAN54511
STATE DIAGRAMS
LINEAR CHARGE
Q4Linear Mode
ISHORTcontrolled
ANY CHARGE
STATE
VBAT > VSHORT
PRE CHARGE
Q4Linear Mode
IPP controlled
VBAT > VBATMIN
VBAT < VBATMIN
VBATMIN(HYS)
−
(VBUS or VIN VALI)D&
(VBATMIN< VBAT < VFLOAT
RCHGDIS=0 &
BAT < VFLOAT−VRCHG
STANDBY
(SLEEP)
FAST CHARGE(CC)
)
V
IDLE
Buck On, Q4 Off
Charge
Complete
Q4 On
OCHRGcontrolled
Buck Of,fQ4 On
I
RCHGDIS=0 &
VBAT < VFLOAT
TOP−OFF
CHARGE
Q4 On
FAST CHARGE(CV)
Q4 On
(VBUS or VIN VALID) =
I
OCHRGcontrolled
(VBUS or V ) > VBAT and
IN
(VBUS or V ) > VSOURCE(RISE) and
IN
(VBUS or V ) has passed Source
IN
Validation.
VBUS or VIN VALID &
Battery Absent
Figure 2. Charger State Diagram: State and Mode Transitions
www.onsemi.com
3
FAN54511
SUPPLEMENTAL
Q4 On
Battery Discharge to SYS
CE# = 1 or
PRE expired & CONT=0 or
PRE expired & CONT=0 or
t
t
TJ > TREGTH
tWD expired & WDTEXP=1
IDLE
Buck On, Q4 Off
ANY CHARGE
STATE
THERMAL
REGULATION
TJ < TREGTH
IOCHRG /2 &
VFLOAT
–
STANDBY
Buck Off, Q4 On
Figure 3. Charger State Diagram: Charger/Battery/System Protection
STANDBY
Buck Off, Q4 On, OTG = 0
BOOSTEN = 0 or
BOOSTEN=1 &
T
> T
or
or
J
SHUTDOWN
VBAT > UVLO
BST
VBAT < UVLO
BST
t
expired or
DIS=1
WD
BOOSTEN=0 or
> T
BOOST ENABLED
T
J
or
or
SHUTDOWN
VBAT < UVLO
BST
t
expired or
WD
DIS = 1
OTG=1
OTG=0
OTG
Q3 On
Figure 4. Boost State Diagram
www.onsemi.com
4
FAN54511
BLOCK DIAGRAM AND SYSTEM DIAGRAMS
VBUS
PMID
REG
Q3
REG
PGND
VIN
CHARGE
PUMP
LDO
LDO
Q5
BOOT
SW
IBUS &
VBUS
CONTROL
Q1
Q2
CHARGE
PUMP
PWM
MODULATOR
VBUS/VIN OVP
POWER OK
PGND
SYS
ILIM
/INT
SDA
SCL
CC and CV
Battery
Charger
Q4
Body
Control
DIS
BAT
/STAT
I2C INTERFACE
/BUSOK
/INOK
LOGIC AND CONTROL
USB DETECTION
BATSNS
NTC
/SHIP
D+ or GPO1
TEMP
SENSE
D−or GPO2
REF
AGND
Figure 5. Block Diagram
www.onsemi.com
5
FAN54511
VIN
PMID
REG
LDO
VBUS
CBUS
CIN
CMID
D+
CREG
SYS USB
PHY
D−
CLDO
BOOT
VSYS
VSYS
CBOOT
D1
SW
To
System
L1
RD
SYS
BAT
/STAT
CSYS
FAN54510
FAN54512
μProcessor
CBAT
DIS
SDA
SCL
/INT
BATSNS
NTC
REF
RREF
Battery
CREF
T
/BUSOK
+
RPU
/INOK
ILIM
/SHIP
To
PMIC
AGND
PGND
Figure 6. FAN54510A, FAN54512A System Diagram
VIN
PMID
REG
LDO
VBUS
CBUS
CIN
CMID
AP USB
PHY
GPO1
GPO2
CREG
CLDO
CBOOT
CP USB
PHY
BOOT
VSYS
VSYS
D1
RD
SW
To
System
L1
SYS
BAT
/STAT
ILIM
CSYS
FAN54511
FAN54513
CBAT
BATSNS
NTC
μProcessor
DIS
SDA
RREF
REF
Battery
CREF
SCL
T
+
/INT
/BUSOK
/INOK
RPU
/SHIP
To
PMIC
AGND
PGND
Figure 7. FAN54511A, FAN54511AP, FAN54513A System Diagram
www.onsemi.com
6
FAN54511
RECOMMENDED EXTERNAL COMPONENTS
Table 3. RECOMMENDED EXTERNAL COMPONENTS
Component
Description
Vendor
Parameter
Typ.
1.0
26
Unit
mH
L
DCR
C
1.0 mH, +20/−10%, 4.1 A, 2520 x
L1
SEMCO CIGT252010EH1R0MNE
1.0 mm
mW
C
C
(Note 2)
22 mF, 6.3 V, 20%, X5R, 0603
10 mF, 25 V, 10%, X5R, 0805
TDK C1608X5R0J226M
22
BAT
MID
mF
x 2 (Note 3)
Murata GRM219R61E106M
C
10
Murata GRM188R61E105K
TDK: C1608X5R1E105M
C
C
1.0 mF, 25 V, 10% X5R, 0603
C
1.0
nF
BUS, IN
C
C
C
R
R
(Note 4)
10 mF, 6.3 V, 20%, X5R, 0603
1.0 mF, 10 V, 20%, X5R, 0402
10 nF, 10 V, 10%, X7R, 0201
10 kW
Murata GRM188R60J106M
Murata GRM155R61A105M
Murata GRM033R71A103K
C
C
C
R
R
10
1.0
10
10
1
SYS
C
, C
LDO
mF
REF, REG
BOOT
REF
kW
1 MW
MW
PU
2. A minimum effective capacitance of 3.6 mF is required after accounting for tolerance, temperature, and aging.
3. A minimum effective capacitance of 8 mF is required after accounting for tolerance, temperature, and aging.
4. Including CSYS, a minimum effective system capacitance (distributed) of 20 mF after accounting for tolerance, temperature, and aging is
required.
VIN
PMID
PMID
BOOT
PMID
SW
PGND
A7
B7
C7
D7
E7
F7
G7
H7
J7
A6
B6
C6
D6
E6
F6
A5
B5
C5
D5
E5
F5
G5
H5
J5
A4
B4
C4
D4
E4
F4
G4
H4
J4
A3
B3
C3
D3
E3
F3
G3
H3
J3
A2
B2
C2
D2
E2
F2
A1
B1
C1
D1
E1
F1
G1
H1
J1
A1
A2
A3
A4
A5
A6
A7
VIN
PMID
PMID
PMID
PMID
SW
PGND
B1
B2
B3
B4
B5
B6
B7
VBUS
PMID
PMID
PMID
PMID
SW
PGND
C1
C2
C3
C4
C5
C6
C7
VBUS
PMID
D−/GPO2 D+ / GPO1 AGND
SW
PGND
D1
D2
D3
D4
D5
D6
D7
LDO
REG
AGND
AGND
AGND
AGND
SYS
E1
E2
E3
E4
E5
E6
E7
AGND
AGND
AGND
SDA
SYS
SYS
SYS
F1
F2
F3
F4
F5
F6
F7
AGND
BATSNS
AGND
SCL
BAT
BAT
BAT
G6
H6
J6
G2
H2
J2
G1
G2
G3
G4
G5
G6
G7
AGND
BAT
REF
AGND
ILIM
/SHIP
/INOK
H1
H2
H3
H4
H5
H6
H7
AGND
NTC
DIS
/STAT
/BUSOK
/INT
AGND
J1
J2
J3
J4
J5
J6
J7
Bottom View
Top View
Figure 8. WLCSP−63 Pin Assignments
www.onsemi.com
7
FAN54511
Table 4. PIN DEFINITIONS
Pin #
Name
Type
Description
POWER GROUND (LOCAL PGND) REFERENCED PINS
Wireless Charger Input Voltage. From wireless receiver or second
A1, B1
C1, D1
VIN
P
P
input power source. Bypass VIN to PGND with 1 mF.
Charger Input Voltage. USB adapter input source also used for the USB−OTG output
voltage. Bypass VBUS to PGND with 1 mF.
VBUS
A2, A3, A5, B2−B5,
C2−C5, D2
Power Input Voltage. Power input to the charger regulator, bypass point for the input
PMID
SW
PFP
P
current sense. Bypass PMID to PGND locally with a minimum of 2x C
.
MID
A6, B6, C6, D6
A4
Switching Node. Connect to inductor L1 and CBOOT.
Bootstrap. High side NMOS Driver Bias. Connect a 10 nF capacitor between BOOT and
SW.
BOOT
SYS
BAT
P
E7, F5−F7
G5−G7, H7
P
System Supply. Connect system load here. Bypass SYS to PGND locally with C
.
SYS
Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass BAT to
PGND with C
P
.
BAT
Linear Regulator. LDO is for powering external circuitry. Default output is 4.95 V when
VBUS or VIN is valid.
E1
LDO
AO
PG
Power Ground. Power return for gate drive and power transistors. The connection from
these pins to the ground pads of C
and C
should be as short as possible. Refer to
A7, B7, C7, D7
PGND
MID
SYS
Recommended Component Placement.
ANALOG GROUND (AGND) REFERENCED PINS
E2
G1
REG
AFP
AI
Internal Regulator. Bypass with a 1 mF capacitor to AGND
Battery Voltage Sense. Connect this pin as close to battery terminal as possible using
a single trace. Do not use as a power pin.
BATSNS
Reference Voltage. REF is a 1.8 V regulated output used in conjunction with the NTC pin
H1
J2
REF
NTC
AO
AI
to determine the battery temperature. Connect to a 1 mF capacitor to AGND.
Negative Temperature Coefficient Resistor. Pin is connected to the NTC terminal of the
battery pack with a 10 kW external pull−up resistor to the REF pin. Note: Other values of
the pull/up resistor and NTC may be used. See applications section for more detail.
D5, E3−E6, F1−F3,
G2, G3,
H2, H3, J1, J7
Analog Ground. All IC signals are referenced to this node. Connect to PGND at a single
point. Refer to Recommended Component Placement.
AGND
AGND
SYSTEM GROUND (PGND) REFERENCED PINS
Positive USB data line (FAN54510A, FAN54512A only). Used for BC1.2 adapter detec-
tion of SDP, DCP, or CDP device connection.
D+
GPO1
D−
AI/O
DO
D4
D3
General Purpose Output 1 (FAN54511A, FAN54511AP, FAN54513A only). CMOS output
driver that is sourced from the LDO output.
Negative USB data line (FAN54510A, FAN54512A only). Used for BC1.2 detection of
SDP or DCP/CDP device connection.
AI/O
DO
General Purpose Output 2 (FAN54511A, FAN54511AP, FAN54513A only). CMOS output
driver that is sourced from the LDO output
GPO2
SDA
SCL
2
2
I C Interface Serial Data. Open−drain, Bi−directional I C serial data line. This pin should
F4
DI/O
DI
not be left floating.
2
2
I C Interface Serial Clock. I C communication clock input. This pin should not be left
floating.
G4
Input Current Limit for VBUS (FAN54511A, FAN54511AP, FAN54513A only). Input LOW
sets the input current limit to 1.5 A and HIGH sets to 500 mA (FAN54511A, FAN54511AP
only) or 100 mA (FAN54513A only). This pin is internally pulled down through a 1 MW
resistor.
H4
ILIM
DI
ILIM pin functionality is disabled for FAN54510A and FAN54512A versions where it is
recommended to tie ILIM to AGND or PGND.
www.onsemi.com
8
FAN54511
Ship Mode Enable (Active−Low). If this pin is held LOW for more than t
during
SHIPENTER
any other state, Ship Mode is entered and the battery is fully isolated from the system
load. If /SHIP is held LOW again for more than t , Ship mode is disabled and Q4
SHIPEXIT
H5
H6
/SHIP
/INOK
DI
is configured to allow the battery to discharge to the system load. Ship mode can also be
exited, automatically, by applying a valid input source. Tie this pin to BAT using a 1 MΩ
pull−up resistor for devices with embedded batteries.
VIN Power Okay (Active−Low). Active low, open−drain output indicates that the input
source voltage at VIN has risen above V
and passed validation, and a valid
SOURCE(RISE)
DO
VBUS is not present. /INOK remains low while V
< V < V
and V > V
IN (FALL)
IN
INOVP IN BAT.
/INOK will be HIGH if /BUSOK is LOW.
Status (Active−Low). Open−drain output indicating charge status. The IC pulls this pin
LOW when charging is in progress, and can be used to signal the host processor or
drive an LED.
J4
J5
/STAT
DO
DO
VBUS Power Okay (Active−Low). Active low, open−drain output indicates that the input
source voltage at VBUS has risen above V
and passed validation. /BUSOK
BUS BAT.
/BUSOK
SOURCE(RISE)
remains low while V
< V
< V
and V
> V
BUS (FALL)
BUS
BUSOVP
Interrupt (Active−Low). Active low, open−drain output indicates that an interrupt bit or bits
have been set. This pin is reset to HIGH after all set interrupt register bit(s) are read.
This pin is not pulled LOW when an interrupt occurs that is masked by the associated
mask bit.
J6
J3
/INT
DIS
DO
DI
Disable. If this pin is held HIGH, the PWM converter is disabled, creating a high imped-
ance path between VBUS/VIN and SYS. This pin has an internal 1 MW pull−down.
5. Pin Types−A = Analog, D = Digital, P = Power, I = Input, O = Output, G = Ground, FP = Filter Point
www.onsemi.com
9
FAN54511
ABSOLUTE MAXIMUM RATINGS
Stresses exceeding the absolute maximum ratings may
damage the device. The device may not function or be
operable above the recommended operating conditions and
stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the
recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings
only.
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VBUS, PMID Voltage, Maximum Slew Rate of 2 V/ms (Note 6)
VIN Voltage, Maximum Slew Rate of 2 V/ms (Note 6)
BOOT Voltage
Min
−2.0
−2.0
−0.3
−0.3
−1.0
Max
22.0
16.0
19.0
14.0
17.0
Unit
V
DC
DC
SW Voltage
Transient: < 5 ns
V
6.5
SYS, BAT Voltage
−0.3
−0.3
(Note 7)
6.5
(Note 7)
V
DCO
Voltage on Other Pins
VBUS, PMID, VIN, BOOT, SW
All Other Pins
1250
2000
Electrostatic Discharge Protection Level, HBM
per JESD22−A114
ESD
V
Electrostatic Discharge Protection Level, CDM
per JESD22−C101
All Pins
1500
T
Junction Temperature
−40
−65
+150
+150
+260
°C
°C
°C
J
T
Storage Temperature
STG
T
L
Lead Soldering Temperature, 10 Seconds
6. Positive slew rate applies only to voltages above the VIN_OVP or VBUS_OVP threshold.
7. Lesser of 6.5 V or V + 0.3 V.
BAT
RECOMMENDED OPERATING CONDITIONS
The Recommended Operating Conditions table defines
the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal
performance to the datasheet specifications. On
Semiconductor does not recommend exceeding them or
designing to Absolute Maximum Ratings.
Table 6. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
4.50
−30
−30
3.6
Max.
13.25
+85
Unit
V
V
V
Supply Voltage
BUS, IN
T
A
Ambient Temperature
Junction Temperature
°C
°C
mF
mF
T
J
+100
C
Minimum Effective Capacitance on VBAT
Minimum Effective Capacitance on PMID
BAT
MID
C
V
BST
= 5 V
8
Minimum Effective Capacitance on SYS (includes C
distributed system capacitance)
and
SYS
C
20
mF
SYS_DISTRIBUTED
C
Minimum Effective Capacitance on LDO
Minimum Effective Capacitance on REG
0.4
0.4
mF
mF
LDO
C
REG
www.onsemi.com
10
FAN54511
THERMAL PROPERTIES
Junction−to−ambient thermal resistance is a function of
application and board layout. This data is measured with
four−layer 2s2p boards without vias in accordance to
JEDEC standard JESD51. Special attention must be paid not
to exceed junction temperature T at a given ambient
J(max)
temperature T .
A
Table 7. THERMAL PROPERTIES
Symbol
Parameter
Junction−to−Ambient Thermal Resistance
Junction−to−Board Thermal Characterization Parameter (Evaluation Board)
Typical
40
Unit
°C/W
°C/W
q
JA
Y
JB
4.3
Table 8. ELECTRICAL SPECIFICATIONS
Unless otherwise specified: V
= 5.0 V; V
= 3.7 V; HZMODE = “0”; BOOSTEN = “0” (Charge Mode); TREGTH = 120°C; I
= I
BUS
BAT
REG LDO
= 0 A; SCL, SDA = 0 or 1.8 V; and typical values are for T = 25°C
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
POWER SUPPLIES
V
> V
; V Open;
SYS
BUS
SOURCE(RISE) IN
4
4
mA
mA
mA
mA
mA
PWM Switching; I
= I
= 0 A
BAT
V
IN
> V
; V
BUS
= I
SYS
Open;
= 0 A
SOURCE(RISE)
ISOURCE
V
BUS
or V Current
IN
PWM Switching; I
BAT
HZMODE= “1”; V
>
SOURCE
200
3
400
10
V
, NTC = GND
SOURCE(RISE)
Sleep State; V
= V = Open or 0V;
IN
BUS
V
BAT
= 4.2 V
Ship Mode State; V
or 0 V; V
= V = Open
IN
BUS
0.8
10
= 4.2 V
BAT
DIS = HIGH or HZMODE=“1”;
=5 V; V = Open; V = 4.2V ;
SYS
IBAT_HZ
Battery Discharge Current
V
1
1
10
10
mA
mA
BUS
IN
BAT
I
= 0 A
DIS = HIGH or HZMODE =“1”; V
=
BUS
=
Open; V = 5V; V
= 4.2V; I
IN
BAT
SYS
0 A
Battery Leakage Current to V
in
V
SYS
= 0 V; V = Open; V
= 4.2 V;
= 4.2 V;
BUS
BUS
IN
BAT
0.2
0.2
5.0
5.0
mA
mA
High−Impedance Mode
I
= 0 A
ISOURCE_HZ
Battery Leakage Current to V in
V
SYS
= 0 V; V
= Open; V
IN
IN
BUS
BAT
High−Impedance Mode
I
= 0 A
CHARGER VOLTAGE REGULATION
Charge Voltage Range
3.30
4.72
+6
V
T = 25°C; V
= 4.20 V to 4.50 V
−6
J
FLOAT
VFLOAT
T = 0 to 70°C; V
= 4.20 V to
J
FLOAT
−10
−25
+10
+25
Charge Voltage Accuracy
mV
4.50 V
T = −25 to 85°C; V
J
= All Settings
FLOAT
FAST CHARGE CURRENT REGULATION
Output Charge Current Range
V
I
< V
< V
FLOAT
200
−5
3200
+5
mA
%
BATMIN
BAT
> 500 mA, −30°C <T < 85°C
I
OCHRG
OCHRG
A
OCHRG
Charge Current Accuracy
I
< 500 mA, −30°C <T < 85°C
−10
+10
A
PRE−CHARGE CURRENT CONTROL
Pre−Charge Current Range
200
−15
45
800
+15
65
mA
%
I
pp
Pre−Charge Current Accuracy
I
Linear Charging Current
V
BAT
< V
SHORT
55
mA
SHORT
www.onsemi.com
11
FAN54511
Table 8. ELECTRICAL SPECIFICATIONS (continued)
Unless otherwise specified: V = 5.0 V; V = 3.7 V; HZMODE = “0”; BOOSTEN = “0” (Charge Mode); TREGTH = 120°C; I
= I
LDO
BUS
BAT
REG
= 0 A; SCL, SDA = 0 or 1.8 V; and typical values are for T = 25°C
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
CHARGE TERMINATION DETECTION
Termination Current Threshold
Range
V
BAT
> V
− V
V
> V
BAT
25
600
mA
FLOAT
RCHG; BUS
ITERM Setting > 200 mA
−10
−20
+10
+20
Termination Current Threshold
Accuracy
I
TERM
%
ITERM Setting = 100 mA to 200 mA
Termination Current Deglitch Time
30
ms
WEAK BATTERY DETECTION
Weak Battery Threshold Range
3.0
3.7
+5
V
FAN54512A Only
100
3
Hysteresis
mV
All Other Part Numbers
V
LOWV
Termination Current Threshold
Accuracy
−5
%
Weak Battery Deglitch Time
Rising Voltage; 2 mV Overdrive
30
ms
MINIMUM BATTERY VOLTAGE DETECTION
Pre−charge to Fast Charge
Transition Threshold Range
2.7
3.4
V
Hysteresis
180
265
30
350
+5
mV
%
V
BATMIN
Threshold Accuracy
Deglitch Time
−5
ms
BATTERY RECHARGE THRESHOLD
Recharge Threshold
Below V
; T = 25°C
170
130
mV
ms
FLOAT
J
V
RCHG
Deglitch Time
SHORTED BATTERY THRESHOLD
Battery Short−Circuit Threshold
V
BAT
falling below V
threshold
RCHG
V
V Rising
BAT
1.94
2.00
2.06
V
SHORT
BATTERY FET SUPPLEMENTAL CONTROL
V
V
V
Falling V
−6
−5
−4
SYS − BAT,
SYS
BAT to SYS Threshold for BATFET
Gate transition while charging
V
mV
THSYS
V
Rising V
0
1
2
SYS − BAT,
SYS
BATTERY TEMPERATURE DETECTION
T1
T2
T3
T4
T1 (0°C) Temperature Threshold
T2 (10°C) Temperature Threshold
T3 (45°C) Temperature Threshold
T4 (60°C) Temperature Threshold
71.9
62.6
30.9
21.3
73.9
64.6
32.9
23.3
75.9
66.6
34.9
25.3
% of
VREF
FLOAT Voltage Reduction During
JEITA Region
V
JEITA
(Note 9)
V
FLOAT
= 4.35 V
160
200
240
mV
www.onsemi.com
12
FAN54511
Table 8. ELECTRICAL SPECIFICATIONS (continued)
Unless otherwise specified: V = 5.0 V; V = 3.7 V; HZMODE = “0”; BOOSTEN = “0” (Charge Mode); TREGTH = 120°C; I
= I
LDO
BUS
BAT
REG
= 0 A; SCL, SDA = 0 or 1.8 V; and typical values are for T = 25°C
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
INPUT POWER SOURCE DETECTION
V
V
V
or V Input Voltage Rising
To Initiate Source Validation
4.30
3.55
4.40
3.70
4.52
3.80
V
V
SOURCE(RISE)
BUS
IN
Minimum V
or V
During Charging, V
< 3.6 V
SOURCE(FALL)
BUS
IN
BAT
Sleep−Mode Entry Threshold,
V
V
≤ V
0
40
100
mV
SLP
SOURCE(FALL)
BAT
V
V
V
V
− V
SOURCE
BAT
t
or V Input Qualification Time
32
32
50
ms
ms
mA
SRCQUAL
BUS
BUS
BUS
IN
t
or V Input Validation Time
IN
VSC_VALID
I
or V Input Validation Current
IN
VSOURCE
DIVC CONTROL LOOP
Input Voltage Loop Setpoint
Accuracy
V
−3
+3
%
SOURCE(LIM)
INPUT CURRENT LIMIT
V
BUS
Input Current Limit Range
100
86
3000
100
ILIM = HIGH (100 mA) FAN54513A
Only
93
ILIM = HIGH (500 mA) FAN54511A,
FAN54511AP Only
460
480
500
mA
I
BUSLIM
ILIM = LOW (1.5 A); FAN54511A,
FAN54511AP, FAN54513A Only
1380
1440
1500
V
BUS
Input Current Limit Threshold
IBUSLIM (REG 14h[6:0]) = “00h”
IBUSLIM (REG 14h[6:0]) = “10h”
IBUSLIM (REG 14h[6:0]) = “74h”
86
93
100
500
460
480
2760
325
2880
3000
2000
1000
2000
V
V
Input Current Limit Range
IN
INLIM (REG 16h[6:0]) = “1Bh”
INLIM (REG 16h[6:0]) = “43h”
920
960
I
mA
INLIM
Input Current Limit Threshold
IN
1840
1920
LOW DROP OUT REGULATOR
V
LDO Voltage Accuracy
Current Rating
V
V
≥ V
+ 500 mV; I
= 1 mA
LDO
−5
+5
%
LDOACC
PMID
LDO
I
= V
+ 500 mV
10
mA
LDO
PMID
LDO
VLDO
DROP
Drop Out Voltage
I
= 10 mA
170
mV
OUT
(Note 10)
LDO Pull Down Resistance when
Disabled
kW
mA
RLDO
LDO Off
1.2
20
50
PD
IQ
LDO Quiescent Current
LDO Load Regulation
LDO On, V
= V + 500 mV
LDO
40
LDO
PMID
V
= V
+ 500 mV;
≤ 10 mA
PMID
LDO
OUT
REG
mV
LDO
10 mA < I
www.onsemi.com
13
FAN54511
Table 8. ELECTRICAL SPECIFICATIONS (continued)
Unless otherwise specified: V = 5.0 V; V = 3.7 V; HZMODE = “0”; BOOSTEN = “0” (Charge Mode); TREGTH = 120°C; I
= I
LDO
BUS
BAT
REG
= 0 A; SCL, SDA = 0 or 1.8 V; and typical values are for T = 25°C
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
GPO1, GPO2 (FAN54511A, FAN54511AP, FAN54513A ONLY)
V
Output Low
Output High
I
= 5 mA
SINK
0.3
V
V
(OL)
V
−
LDO
V
(OH)
I
= 5 mA
SOURCE
200 mV
V
REF
BIAS GENERATOR
Bias Regulator Voltage
Short−Circuit Current Limit
/STAT, /BUSOK, /INOK, /INT, SDA
V
> V
1.8
2.5
V
SOURCE
SOURCE(MIN)
V
REF
mA
V
Output Low
I
= 5 mA
0.4
1
V
(OL)
SINK
mA
I
Output High Leakage Current
VDD = 5 V
(OH)
LOGIC LEVELS: SDA, SCL, /SHIP, ILIM, DIS
V
High−Level Input Voltage
Low−Level Input Voltage
Input Bias Current
1.05
V
V
IH
V
0.4
IL
mA
I
IN
Input Tied to GND or V
0.01
1
1.00
BUS
DIS, ILIM
(Note 11)
MW
R
Pull Down Resistance
PD
D+/D− DETECTION (FAN54510A, FAN54512A ONLY)
0 to 300 mA
0 to 300 mA
V
D+ Source Voltage
0.5
0.5
0.25
7
0.6
0.6
0.7
0.7
V
V
DP_SRC
DM_SRC
DAT_REF
DP_SRC
DP_SNK
V
D− Source Voltage
V
I
Data Detect Voltage
Data Contact Detect Current Source
D+ Sink Current
0.40
13
V
mA
mA
mA
V
I
25
25
2
175
175
I
D− Sink Current
DM_SNK
V
Logic High Threshold
Logic Low Threshold
D− Pulldown Resistor
LGC_HI
V
0.8
V
LGC_LO
kW
R
14.25
24.80
DM_DWN
D+, D− = Hi−Z; f = 1 MHz,
= 0.2 V
C
(Note 9)
D+, D− Off Capacitance
4
pF
OFF
V
BIAS
BATTERY ABSENCE DETECTION
I
Battery Detection Current before
Charge Done (Sink Current)
DETECT
−8
mA
ms
Begins after Termination Detected and
before
(Note 12)
V
< V
–V
BAT
FLOAT RCHG
t
Battery Detection Time
262
DETECT
www.onsemi.com
14
FAN54511
Table 8. ELECTRICAL SPECIFICATIONS (continued)
Unless otherwise specified: V = 5.0 V; V = 3.7 V; HZMODE = “0”; BOOSTEN = “0” (Charge Mode); TREGTH = 120°C; I
= I
LDO
BUS
BAT
REG
= 0 A; SCL, SDA = 0 or 1.8 V; and typical values are for T = 25°C
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
POWER SWITCHES
VBUS to PMID; I
= 300 mA
360
82
BUS
BUS
BUS
Resistance of VBUS Blocking FET
(Q3)
VBUS to PMID; I
VBUS to PMID; I
= 900 mA
= 3000 mA
28
Resistance of VIN Blocking FET
(Q5)
VIN to PMID
PMID to SW
SW to GND
135
24
19
55
15
Resistance of Buck High Side FET
(Q1)
mW
R
DS(ON)
Resistance of Buck Low Side FET
(Q2)
SYS to BAT; VBAT = 4.2 V; I
500 mA
=
OCHG
Resistance of BATFET (Q4)
SYS to BAT; VBAT = 4.2 V; I
A
= 1.5
OCHG
CHARGER PWM MODULATOR
f
Oscillator Frequency
Duty Cycle
1.5
MHz
%
SW
D
(Note 9)
0
99.6
UTY
BOOST MODE OPERATION (BOOSTEN (REG 1Ch[5]) = OTG (REG 1Ch[6]) = “1”)
Programmable Boost Output
2.5 V < V
< 4.5 V
4.940
4.85
4.75
5.347
5.25
BAT
Voltage Range
2.5 V < V
LOAD
< 4.5 V; V
= 5 V;
= 5 V;
BAT
BST
5.00
V
V
BOOST
I
from 0 to 900 mA
Boost Output Voltage at VBUS
3.0 V < V
LOAD
< 4.5 V; V
BST
BAT
5.00
300
4.1
5.25
575
5.7
I
from 0 to 1500 mA
mA
I
Boost Mode Quiescent Current
Q2 Peak Current Limit
V
BAT
= 3.6 V; I
= 0 A
BAT(BOOST)
LOAD
I
LIMPK(BST)
(Note 9)
3.3
A
While Boost Active
To Start Boost Regulator
2.32
2.48
UVLO
Minimum Battery Voltage for Boost
Operation
BST
V
2.70
PROTECTION AND TIMERS
V
Rising;
BUS
6.35
10.25
13.4
6.50
6.65
10.75
14.0
VBUSOVP (REG 15h[5:4]) = “00”
V
Rising;
BUS
10.50
V
VBUS Over−Voltage Threshold
V
BUSOVP
VBUSOVP (REG 15h[5:4] = “01”
V
Rising;
BUS
13.7
100
VBUSOVP (REG 15h[5:4] = “10”
V
V
Hysteresis
V
BUS
Falling
mV
BUSOVP(HYS)
BUSOVP
www.onsemi.com
15
FAN54511
Table 8. ELECTRICAL SPECIFICATIONS (continued)
Unless otherwise specified: V = 5.0 V; V = 3.7 V; HZMODE = “0”; BOOSTEN = “0” (Charge Mode); TREGTH = 120°C; I
= I
LDO
BUS
BAT
REG
= 0 A; SCL, SDA = 0 or 1.8 V; and typical values are for T = 25°C
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
PROTECTION AND TIMERS
V
Rising;
IN
6.35
10.25
13.4
6.50
6.65
10.75
14.0
VINOVP (REG 17h[5:4]) = “00”
V
IN
Rising;
10.50
V
V
V
Over−Voltage Threshold
V
INOVP
IN
VINOVP (REG 17h[5:4]) = “01”
V
IN
Rising;
13.7
100
VINOVP (REG 17h[5:4]) = “10”
V
Hysteresis
V
IN
Falling
mV
V
BUSOVP(HYS)
INOVP
BOOSTEN (REG 1Ch[5] = “1”; V
Rising
BUS
Boost Over−Voltage Threshold
Hysteresis
5.8
5.9
6.1
V
BOOST_OVP
V
BUS
Falling
100
mV
V
1.025*
FLOAT
1.050*
FLOAT
1.075*
FLOAT
Battery Over−Voltage Threshold
Rising
Falling relative to Rising Thresh-
V
V
V
V
BAT_OVP
V
BAT
Hysteresis
1
%
A
old
I
High−Side Cycle−by−Cycle Peak
Current Limit (Q1)
LIMPK(CHG)
(Note 9)
Charge Mode
4.6
6.6
4.9
5.4
I
Q4 Short Circuit Current Limit
Q4 Short Circuit Qualification Time
Q4 Short Circuit Recovery Time
Hardware Ship Mode Entry Time
Hardware Ship Mode Exit Time
9.0
1
A
LIMQ4SC
t
ms
sec
sec
sec
SCQUAL
t
2
SCRECOV
t
Not in Ship Mode
In Ship Mode
8
SHIPENTER
t
4
SHIPEXIT
Thermal Shutdown Threshold during
Charging
T Rising
150
J
T
SHUTDOWN
(Note 9)
°C
Hysteresis
T Falling
J
T
REGTH
Thermal Regulation Threshold dur-
ing Charging or Thermal Shutdown
Threshold during Boost Operation
T
(Note 9)
REG 0Fh[6:5]) = ”10”
100
°C
REGTH
Battery Detection Interval while the
Battery is Removed
t
2.1
sec
INT
t
Safety Timer – Fast Range
Safety Timer – Pre Range
Top Off Timer
240
1.667
10
960
36.000
70
min
min
min
sec
min
%
FAST
t
PRE
t
TO
FAN54510A SDP Attached
FAN54512A SDP Attached
100
36
120
45
t
USB Timer
USB
t
Safety Timer Accuracy
−20
80
20
SAFE_ACC
Charger Enabled
Charger Disabled
Charger Inactive
100
100
120
127
27
sec
%
t
Watch Dog Timer
WD
73
Dt
(Note 13) Low−Frequency Timer Accuracy
−27
%
L_F
8. Limits over the recommended temperature operating range (−30 to 85 °C) are correlated by statistical quality control methods.
9. Guaranteed by design and/or Characterization; not tested in production.
10.Dropout voltage is determined by reducing the LDO input voltage until the LDO output voltage falls to 98% of its regulated voltage. Under
this condition, PMID − VLDO (MEASURED) = VLDODROP.
11. In LOW state, the pull−down is present. In HIGH state, the pull−down is released.
12.Negative current is current flowing from the battery to GND (discharging the battery).
13.This tolerance (%) applies to all timers on the IC, including soft−start and deglitch timers.
www.onsemi.com
16
FAN54511
Table 9. I2C TIMING SPECIFICATIONS
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Standard Mode
100
Fast Mode
400
f
SCL Clock Frequency
kHz
Fast Mode Plus
1000
3400
1700
SCL
High−Speed Mode, C < 100 pF
B
High−Speed Mode, C < 400 pF
B
Standard Mode
4.7
Bus−free Time between STOP and
ms
t
Fast Mode
1.3
0.5
BUF
START Conditions
Fast Mode Plus
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ns
ns
ns
ns
ms
ns
ns
ns
Standard Mode
Fast Mode
4
600
260
160
4.7
1.3
0.5
160
320
4
START or Repeated START Hold
Time
t
HD;STA
Fast Mode Plus
High−Speed Mode
Standard Mode
Fast Mode
Fast Mode Plus
t
SCL LOW Period
LOW
High−Speed Mode, C < 100 pF
B
High−Speed Mode, C < 400 pF
B
Standard Mode
Fast Mode
600
260
60
Fast Mode Plus
t
SCL HIGH Period
HIGH
High−Speed Mode, C < 100 pF
B
High−Speed Mode, C < 400 pF
120
4.7
600
260
160
250
B
Standard Mode
Fast Mode
t
Repeated START Setup Time
SU;STA
Fast Mode Plus
High−Speed Mode
Standard Mode
Fast Mode
100
50
t
Data Setup Time
ns
SU;DAT
Fast Mode Plus
High−Speed Mode
10
ms
ns
ns
ns
ns
Standard Mode
Fast Mode
0
0
0
0
0
3.45
900
450
70
Fast Mode Plus
t
Data Hold Time
HD;DAT
High−Speed Mode, C < 100 pF
B
High−Speed Mode, C < 400 pF
150
B
www.onsemi.com
17
FAN54511
Table 9. I2C TIMING SPECIFICATIONS (continued)
Symbol
Parameter
Condition
Min.
Typ.
Max.
1000
300
120
80
Unit
Standard Mode
Fast Mode
20+0.1C
B
B
20+0.1C
Fast Mode Plus
20+0.1C
t
SCL Rise Time
ns
B
RCL
High−Speed Mode, C < 100 pF
10
B
High−Speed Mode, C < 400 pF
20
160
300
300
120
40
B
Standard Mode
Fast Mode
20+0.1C
20+0.1C
20+0.1C
B
B
Fast Mode Plus
t
SCL Fall Time
ns
ns
ns
B
FCL
High−Speed Mode, C < 100 pF
10
B
High−Speed Mode, C < 400 pF
20
10
20
80
B
High−Speed Mode, C < 100 pF
80
B
Rise Time of SCL after a Repeated
START Condition and after ACK Bit
t
RCL1
High−Speed Mode, C < 400 pF
160
1000
300
120
80
B
Standard Mode
Fast Mode
20+0.1C
20+0.1C
20+0.1C
B
B
Fast Mode Plus
t
SDA Rise Time
SDA Fall Time
B
RDA
High−Speed Mode, C < 100 pF
10
B
High−Speed Mode, C < 400 pF
20
160
300
300
120
80
B
Standard Mode
Fast Mode
20+0.1C
20+0.1C
20+0.1C
B
B
Fast Mode Plus
t
ns
B
FDA
High−Speed Mode, C < 100 pF
10
B
High−Speed Mode, C < 400 pF
20
4
160
B
Standard Mode
Fast Mode
ms
ns
ns
ns
pF
600
120
160
t
Stop Condition Setup Time
SU;STO
Fast Mode Plus
High−Speed Mode
C
Capacitive Load for SDA and SCL
400
B
CIRCUIT OVERVIEW
The FAN5451x combines
Additionally, the FET provides a low impedance path from
the battery to the system.
a
highly integrated
synchronous buck regulator for battery charging and
providing system power. The converter can also operate as
a boost regulator, which can supply 5 V to USB On−The−Go
(OTG) peripherals. The regulator employs synchronous
rectification for both the charger and boost operations to
maintain high efficiency over a wide range of adapter input
voltage and battery voltages.
With dual inputs, the charger can quickly switch between
multiple power sources. For example, the charger can be
powered from a wireless power receiver until plugged into
a traditional USB or wall adapter.
OPERATING MODES
The FAN5451x has seven operating modes:
Linear Mode:
When V
< V
(2.0 V), the buck converter
BAT
SHORT
regulates voltage at SYS and provides the system current
enabling instant turn on of the system. The BATFET (Q4)
charges the battery at the I
the battery.
current to safely recover
SHORT
Pre−Charge Mode:
An integrated Power Path FET facilitates fast system
startup. This FET also accurately senses charging current,
thus eliminating the need for an external sense resistor.
Above V
, the buck converter regulates voltage at
SHORT
SYS and provides the system current. The BATFET (Q4) is
operated as a linear current source to pre−charge the battery
under I control.
PP
www.onsemi.com
18
FAN54511
Fast Charge Mode:
Fast Charge Current Regulation (IOCHRG)
The BATFET (Q4) is fully enhanced, charging the battery
under I control either in the Constant Current Mode
Limits the maximum battery charging current when V
BAT
> V . The default setting is 1000 mA.
BATMIN
OCHRG
or Constant Voltage Mode from the output of the buck
regulator.
See IOCHRG (REG 12h[5:0])
Thermal Regulation (TREG
)
Limits charge current to prevent the IC from overheating.
The default setting is 100°C.
System Mode (Idle State):
The buck converter regulates voltage at SYS and provides
the system current, while the battery is not being charged.
This mode can occur if the battery charging has terminated
or charging is disabled.
See TREGTH (REG 0Fh[6:5])
Output Voltage Regulation (VFLOAT
)
Maximum battery charging voltage. The default setting is
4.35 V.
Supplemental Mode
The buck converter cannot produce enough current to
See FLOAT (REG 11h[7:0])
maintain V
above V
The BATFET (Q4) is fully
SYS
BAT.
Charge Termination Threshold (ITERM
)
enhanced to provide supplemental current from the battery
to the system load.
Terminates charging at the desired current when TE
(termination enable)=“1”. The default setting is 300 mA.
See ITERM (REG 13h[7:4])
Boost Mode
Q1 and Q2 operate as a synchronous boost regulator to
provide power to the VBUS pin for USB−On−the−Go
(OTG) applications using the battery as its input. The boost
converter output voltage is programmable.
CONFIGURABLE INPUT POWER PARAMETERS
The following input power parameters can be
2
programmed by the host through I C:
VBUS Input Current Limit (IBUSLIM
Limits the amount of current drawn from the VBUS
source. The default setting is 500 mA.
)
High−Impedance Mode (Standby State)
Both the boost and charging circuits are OFF and the
battery is providing current to the system. Current flow from
VBUS or VIN to the battery or from the battery to VBUS or
VIN is blocked.
See IBUSLIM (REG 14h[6:0])
VIN Input Current Limit (IINLIM
)
Limits the amount of current drawn from the VIN source.
The default setting is 1 A.
See IINLIM (REG 16h[6:0])
CONFIGURABLE CHARGE PARAMETERS
The following charging parameters can be programmed
2
by the host through I C:
Dynamic Input Voltage Control (VSOURCE
)
Pre−Charge Current Regulation (IPP
)
Limits the input current when a current−limited weak
adapter is connected to either of VBUS or VIN. The settings
are configurable from 4.2 V to 8.6 V. The default settings are
4.56 V.
Limits the maximum battery charging current when
< V < V . The default setting is 450 mA.
V
SHORT
BAT
BATMIN
See PRECHG (REG 13h[3:0])
See VBUSLIM (REG 15h[3:0]) and VINLIM (REG
17h[3:0])
Minimum Battery Threshold (VBATMIN
Sets the battery voltage threshold for transitioning
between Pre−Charge and Fast Charge. V should not
be set lower than the minimum required system voltage. The
default setting is 3.4 V.
See VBATMIN (REG 0Ch[2:0])
)
BATMIN
CONFIGURABLE BOOST PARAMETERS
The following boost parameters can be programmed by
2
the host through I C:
Boost Output Voltage (VBOOST
)
Regulated System Voltage (V
)
SYS
Regulates the boost converter output voltage on PMID
when BOOSTEN = “1”. When OTG = “1” VBUS is
connected to PMID. The default setting is 5.0 V.
See VBOOST (REG 1Ch[3:0]).
Regulates the system voltage when V
< V
.
BAT
BATMIN
VSYS should be programmed 200 mV, or more, above the
minimum required system voltage. The default setting is
3.6 V.
See VSYS (REG 0Dh[1:0])
www.onsemi.com
19
FAN54511
CHARGE MODE TYPICAL CHARACTERISTICS
Unless otherwise specified, circuit of Typical Application, using FAN54511A, default register values/settings, V
= 5.0 V, and T = 25°C.
BUS
A
100
95
90
85
80
75
100
95
90
85
80
75
5 VBUS
9 VBUS
12 VBUS
5 VIN
5 VBUS
9 VBUS
12 VBUS
5 VIN
0
500
1000
1500
2000
2500
3000
3500
0
500
1000
1500
2000
2500
3000
3500
Charge Current, I
(mA)
Charge Current, I
(mA)
BAT
BAT
Figure 9. Efficiency vs. IOCHRG, VBAT = 4.3 V,
BUSLIM = 3.0 A, IINLIM = 2.0 A
Figure 10. Efficiency vs. IOCHRG, VBAT = 3.8 V,
BUSLIM = 3.0 A, IINLIM = 2.0 A
I
I
1,600
1,400
1,200
1,000
800
4,000
3,500
3,000
2,500
2,000
1,500
1,000
5 VBUS
9 VBUS
12 VBUS
5 VIN
5 VBUS
9 VBUS
12 VBUS
5 VIN
600
400
3.5
3.7
3.9
4.1
4.3
4.5
3.5
3.7
3.9
4.1
4.3
4.5
Battery Voltage, V
(V)
Battery Voltage, V
(V)
BAT
BAT
Figure 11. Fast Charge Current vs.
BAT, IOCHRG = 3.2 A, IBUSLIM = IINLIM = 500 mA,
FLOAT = 4.5 V
Figure 12. Fast Charge Current vs.
BAT, IOCHRG = 3.2 A, IBUSLIM = IINLIM = 1,500 mA,
FLOAT = 4.5 V
V
V
V
V
www.onsemi.com
20
FAN54511
CHARGE MODE TYPICAL CHARACTERISTICS
(Unless otherwise specified, circuit of Typical Application, using FAN54511A, default register values/settings, V
= 5.0 V, T = 25°C
BUS
A
4,500
4,000
3,500
3,000
2,500
2,000
1,500
6
5
4
3
2
1
0
VBUS
VIN
5 VBUS
9 VBUS
12 VBUS
5 VIN
3.5
3.7
3.9
4.1
4.3
4.5
0
5
10
15
20
Input Voltage (V)
Battery Voltage, V
(V)
BAT
Figure 13. Peak Available Load Current (IBAT + ISYS
vs. VBAT, IBUSLIM = 3.0 A, IINLIM = 2.0 A, VFLOAT = 4.5 V
)
Figure 14. Quiescent Current vs. Input Voltage,
ISYS = 0 A, No Battery, LDO Off, NTC = GND,
V
BUSOVP = 13.7 V, VINOVP = 10.5 V
10
5
4
3
2
1
0
−30C
−30C
+25C
+85C
+25C
8
+85C
6
4
2
0
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
Battery Voltage, V
(V)
Battery Voltage, V
(V)
BAT
BAT
Figure 15. Battery Discharge Current
vs. VBAT, Sleep Mode
Figure 16. Battery Discharge Current
vs. VBAT, Ship Mode
Figure 17. Startup at VBUS Plug−In, VBAT = 3.2 V,
50 ꢀ SYS Load, ILIM = “0”
Figure 18. Startup at VBUS Plug−In, VBAT = 3.8 V,
50 ꢀ SYS Load, ILIM = “0”
www.onsemi.com
21
FAN54511
CHARGE MODE TYPICAL CHARACTERISTICS (continued)
(Unless otherwise specified, circuit of Typical Application, using FAN54511A, default register values/settings, V
= 5.0 V, and T = 25°C)
A
BUS
Figure 19. Startup at VBUS Plug−In, Dead Battery,
50 ꢀ SYS Load, ILIM = “0”
Figure 20. FAN54510 Startup at VBUS Plug−In,
BAT = 3.2 V, 50 ꢀ SYS Load, SDP, No Host Control
V
Figure 21. Startup at VBUS Plug−In, No Battery,
50 ꢀ SYS Load, ILIM = “0”
Figure 22. VBUS Plug−In with VSOURCE Validation
Fail, VBAT = 3.8 V, 50 ꢀ SYS Load
Figure 23. VBUS Un−Plug, 3.8 VBAT
,
Figure 24. Charge Termination, TE = TOEN = “1”,
50 ꢀ SYS Load, ILIM = “0”
ITERM = 300 mA, 100 mA SYS Load
www.onsemi.com
22
FAN54511
CHARGE MODE TYPICAL CHARACTERISTICS (continued)
(Unless otherwise specified, circuit of Typical Application, using FAN54511A, default register values/settings, V
= 5.0 V, and T = 25°C)
A
BUS
Figure 25. Battery Removal/Insertion while
Charging, TE = “0”, VBAT = 3.8 V, 50 mA SYS Load,
Figure 26. VBUS Plug−In OVP Condition, VBAT = 3.8
V, 50 ꢀ SYS Load, ILIM = “0”
IBUSLIM = 1.5 A, IOCHRG = 2.0 A
Figure 27. VBUS OVP Response While Charging,
BAT = 3.8 V, 50 ꢀ SYS Load, ILIM = “0”
Figure 28. Load Pulse Response, 150 mA−2150
mA− 150 mA SYS Load with tR = tF = 10 ꢁsec,
3.8 VBAT, IBUSLIM = 1.5 A, IOCHRG = 3.0 A
V
Figure 29. Load Pulse Response, 150 mA−2150
mA− 150 mA SYS Load with tR = tF = 10 ꢁsec,
4.35 VBAT, IBUSLIM = 1.5 A, IORCHG = 3.0 A, TE = “0”
Figure 30. Input Source Selection, 5.0 VIN Present,
Insert/Remove 5.0 VBUS, 3.8 VBAT, 50 ꢀ SYS Load
www.onsemi.com
23
FAN54511
CHARGE MODE TYPICAL CHARACTERISTICS (continued)
(Unless otherwise specified, circuit of Typical Application, using FAN54511A, default register values/settings, V
= 5.0 V, and T = 25°C)
A
BUS
Figure 31. Battery Discharge Current Limit
Response to SYS Fault, Sleep Mode, 3.8 VBAT
www.onsemi.com
24
FAN54511
CHARGE MODE TYPICAL CHARACTERISTICS
(Unless otherwise specified, using circuit of Typical Application, V
= 3.8 V, V
= 5.00 V, T = 25°C. Boost enabled by writing
BAT
BOOST
A
BOOSTEN = OTG = “1”, simultaneously.)
100
95
90
85
80
75
100
95
90
85
2.7 VBAT
−30C
+25C
+85C
80
3.0 VBAT
3.7 VBAT
4.3 VBAT
75
0
250
500
750
1000
1250
1500
0
250
500
750
1000
1250
1500
V
BUS
Load Current (mA)
V
BUS
Load Current (mA)
Figure 32. Efficiency vs. Load Current
Figure 33. Efficiency vs. Load Current, 3.7 VBAT
5.06
30
25
20
15
2.7 VBAT
3.0 VBAT
3.7 VBAT
4.3 VBAT
5.04
5.02
5.00
4.98
4.96
4.94
10
2.7 VBAT
3.0 VBAT
5
3.7 VBAT
4.3 VBAT
0
0
250
500
750
1000
1250
1500
0
250
500
750
1000
1250
1500
V
BUS
Load Current (mA)
V
BUS
Load Current (mA)
Figure 34. Output Regulation
Figure 35. Output Ripple vs. Load Current
500
450
400
350
300
250
200
3,500
3,000
2,500
2,000
1,500
1,000
500
− 30C
+25C
+85C
− 30C
+25C
+85C
2.5
3.0
3.5
4.0
4.5
2.5
3.0
3.5
4.0
4.5
Battery Voltage, V
(V)
Battery Voltage, V
(V)
BAT
BAT
Figure 36. Quiescent Current
Figure 37. Load Current Limit, 5.00 VBOOST
www.onsemi.com
25
FAN54511
CHARGE MODE TYPICAL CHARACTERISTICS
(Unless otherwise specified, using circuit of Typical Application, V
= 3.8 V, V
= 5.00 V, T = 25°C. Boost enabled by writing
BAT
BOOST
A
BOOSTEN = OTG = “1”, simultaneously.)
3,000
2,500
2,000
1,500
1,000
500
5.000 VBST
5.213 VBST
5.347 VBST
0
2.5
3.0
3.5
4.0
4.5
Battery Voltage, V
(V)
BAT
Figure 38. Load Current Limit vs. VBOOST
Figure 39. Boost Startup, 50 ꢀ Load
Figure 40. Boost Startup, 5 ꢀ || 10 ꢁF Load
Figure 41. Load Transient Response, 100 mA−400
mA−100 mA Load with tR = tF = 100 nsec
Figure 42. Line Transient Response, 500mA Load,
3.8 VBAT −3.2 VBAT −3.8 VBAT with tR = tF = 10 ꢁsec
www.onsemi.com
26
FAN54511
CHARGE MODE TYPICAL CHARACTERISTICS
(Unless otherwise specified, using circuit of Typical Application, V
= 3.8 V, V = 5.00 V, T = 25°C. Boost enabled by writing
BOOST A
BAT
BOOSTEN = OTG = “1”, simultaneously.)
Figure 43. VBUS Output Fault Response
Figure 44. Boost Startup into VBUS Fault
Standby State
NON−CHARGING STATES
The Standby State is an intermediate state where the
PWM Buck is off and the BATFET (Q4) is fully enhanced.
During Standby State, reverse current out of the VBUS or
VIN pin is prevented by turning off the Q3 and Q5 blocking
FETs.
If Standby State is entered for any of the following
conditions, a return to Charge State occurs when the related
condition is removed:
Idle State
During Idle State the PWM Buck continues to regulate
system voltage to V
The battery is not being charged and the BATFET (Q4) is
off.
In the Idle State, the V /V
providing power to the system.
FLOAT
comparator is monitored
BAT SYS
and if V
falls below V
by V , the BATFET (Q4)
THSYS
SYS
BAT
is fully enhanced for Supplemental Mode operation.
If Idle State is entered for any of the following conditions,
a return to Charge State occurs when the related condition is
removed:
1. Sleep State where V
< V
+ V
or
SOURCE
BAT
SLP
V
< V
.
SOURCE
SOURCE(FALL)
2. The device has been put in Hi−Z state by
HZMODE (REG 0Eh[1]) = “1” or DIS = HIGH.
3. The die temperature is in thermal shutdown
1. Charge Complete (CHGCMP = “1”) occurs with
TE = “1”. If RCHGDIS (REG 0Eh[5]) = “0”, the
(T
).
SHUTDOWN
IC will return to Charge State when V
<
BAT
If Standby State is entered for any of the following
conditions, the only way to restart charging is to first remove
V
FLOAT
– V
.
RCHG
2. The Top−Off Timer (t ) expires. If RCHGDIS
TO
V , and then reconnect a valid VIN or VBUS power
SOURCE
(REG 0Eh[5]) = “0”, the IC will return to Charge
State when V
source:
1. The USB Timer (t
< V
– V
.
BAT
FLOAT
RCHG
) expires (FAN54510A and
USB
3. The battery is below T1 or above T4. See JEITA
Charging section for details.
4. The battery is removed and TE = “1”.
5. The BATFET is disabled by the Charge Enable bit,
CE# = “1”.
FAN54512A only).
Sleep State
Sleep State is part of the suite of conditions which make
up the Standby State. The BATFET (Q4) is fully enhanced
while the IC is in the Sleep State. This ensures that the
FAN5451x powers the system from the battery when
operating without a valid input source on either VBUS or
VIN.
If Idle State is entered for any of the following conditions,
the only way to restart charging is to first remove V
and then reconnect a valid VIN or VBUS power source:
1. The Safety Timer (t or t ) expires when
,
SOURCE
PRE
FAST
APPLICABLE STATUS AND INTERRUPT
CONT (REG 0Eh[7]) = “0”.
2. The battery voltage drops below V
charging.
during
Status Bits:
SLEEP (REG 00h[1])
SHORT
3. The Watch Dog Timer (t ) expires and
WD
WDTEXP (REG 30h[7]) = “1”.
www.onsemi.com
27
FAN54511
Source Voltage Validation
CHARGER CIRCUIT DETAILS
After battery capacitor discharge, Source Voltage
Refer to:
Validation occurs with a I
(50 mA) load on PMID.
Charger State Diagram” State and Mode Transitions
and
Charger State Diagram: Charger/Battery/System
Protection
VSOURCE
To pass validation, either V
or V must remain above
BUS
IN
V
and below V
for t
SOURCE(RISE)
SOURCEOVP
VSR_VALID
(32 ms) before the IC initiates charging. T
VSR_VALID
ensures that unfiltered 50/60 Hz chargers and other
non−compliant chargers are rejected.
Plug In: Source Selection and Validation
APPLICABLE STATUS AND INTERRUPT
Source Selection
/BUSOK
/INOK
/INT
Only one input source (VBUS or VIN) can be routed to the
buck converter at any given time. If valid power sources are
connected to both VIN and VBUS, the input selector
automatically opens Q5 and closes Q3, thereby selecting
VBUS as the input source to the buck converter.
The active source is identified by a Status bit.
APPLICABLE STATUS AND INTERRUPT
Pins:
VBUSINT (REG 04h[5])
VININT (REG 04h[6])
Interrupt Bits:
Status Bits:
VBUSPWR (REG 00h[5])
VINPWR (REG 00h[6])
INPUTSEL (REG 02h[7])
If the input source fails validation, the validation period is
extended an additional 32 ms and source validation is
re−tried. A failure will result in an interrupt and the part
returning to Sleep State, where the entire validation routine
Status Bits:
INPUTSEL (REG 02h[7])
Battery Capacitor Discharge
When either V
SOURCE(RISE)
or V rises and remains above
BUS
IN
V
for the t
(32 mS) duration, the IC
will restart when V
> V
.
SRCQUAL
SOURCE
APPLICABLE STATUS AND INTERRUPT
SOURCE(RISE)
applies a I
(−8 mA) load to V
for T
DETECT
BAT DETECT
(262 ms) to ensure that if the battery is not present, or its
discharge protection switch is open, the capacitors on V
Pins:
/INT
BAT
Interrupt Bits:
VALFAIL (REG 04h[7])
will be discharged below the V
threshold.
SHORT
Battery Voltage Measurement
D+/D− Adapter Detection (VBUS only)
See Table 11 and Table 12 for the FAN5451x versions that
have this feature.
The battery voltage is measured if the adapter passes
Source Validation. The IC can identify an absent, shorted,
low, or dead battery, configure the charging parameters
accordingly, and then enter Charge Mode.
Figure 45, Figure 46, and Figure 47 illustrate Plug In
timing under various conditions. The t
When V
rises and remains above V
for
BUS
SOURCE(RISE)
the t
(32 mS) duration, the FAN5451x versions
SRCQUAL
that have this feature perform adapter detection.
SDP, CDP, and DCP adapter types can be uniquely
identified by the Charger IC, which will automatically select
timing
and is described in
DELAY
specification is affected by V
Table 10.
BAT
the appropriate I
current limit per the USB Battery
BUS
Charging Specification (BC1.2), and report the adapter type
in a Status register.
APPLICABLE STATUS AND INTERRUPT
Table 10. TDELAY TIMING vs. VBAT
V
BAT
(V)
T
(ms)
DELAY
69
< V
BATMIN
Status Bits:
CHGDET (REG 01h[6:5])
37
10
V
< V
< V
LOWV
BATMIN
BAT
> V
LOWV
www.onsemi.com
28
FAN54511
4.4V
VBUS_POR
262ms
Battery Discharge
VBUS
32ms Source Validation
ON
32ms Debounce
Load VBUS
OFF
VLOWV
VBATmin
tDELAY
2.0V
VBAT
Precharge
Current
4.4V
50mA
VSOURCE_POR
Current
Source
262ms
Fast
Charge
Battery Discharge
VSOURCE
IBAT 0A
32ms Source Validation
Standby
ON
32ms Debounce
Load V
SOURCEOFF
ON
Load VBAT
OFF
ON
tDELAY
VBATmin
Linear
BATFET, Q4
OFF
Control
BC1.2
Testing
2.0V
VBAT
D+ =0.6V
Precharge
Current
Fast
Charge
50mA
Current
Source
D+/D−Pins
15ms
IBAT 0A
Data Contact
Detection
120ms
ON
Load VBAT
Primary
Detection
OFF
ON
Secondary
Detection
Linear
Control
BATFET, Q4
OFF
Figure 45. VBUS or VIN Plug In, VBAT < VSHORT
Figure 46. VBUS Plug In, SDP, VBAT < VSHORT
4.4V
VBUS_POR
262ms
Battery Discharge
VBUS
32ms Source Validation
ON
32ms Debounce
Load VBUS
OFF
VLOWV
VBATmin
TDELAY
2.0V
Precharge
Current
Fast
Charge
VBAT
50mA
Current
Source
IBAT 0A
ON
Load VBAT
OFF
ON
Linear
Control
BATFET, Q4
OFF
BC1.2
Testing
D+/D−Pins
15ms
Data Contact
Detection
120ms
Primary
Detection
70ms
Secondary
Detection
Figure 47. VBUS Plug In, CDP, VBAT < VSHORT
www.onsemi.com
29
FAN54511
CHARGE MODES
Auto−Charge and Establishing Host Control
The FAN5451x features Auto−Charge, which supports
battery charging prior to Host Control.
where the only way to restart charging is to first remove
then reconnect a valid VIN or VBUS power
V
SOURCE,
After the source voltage has been validated at Plug In, if
source.
If a SDP adapter is detected and V
V
< V , the IC resets all registers to their default
BATMIN
> V
, the
LOWV
BAT
BAT
values. Regardless of battery voltage, the IC then operates
in accordance with its I C register settings except that the
charger will disable the LDO and enter Standby State, where
any I C write to the IC will return it to Charge Mode under
2
2
IBUSLIM (REG 14h[6:0]) settings are ignored until the first
Host Control.
2
I C write after charging begins.
If a SDP adapter is detected and the DIS pin is HIGH, the
LDO will be disabled after validation and remain disabled
until SDP charging occurs when DIS is driven LOW or Host
Control is established.
2
Only after the first I C write after charging begins is Host
Control established.
Prior to Host Control, the I
current limit and the charge
BUS
timer length are as described in Table 11 and Table 12.
Once Host Control has been established, the charge
parameter settings are as described in Table 13.
If a CDP or DCP adapter is detected, Auto−Charge uses
the Safety Timer with the I
current limit set to 1500 mA.
BUS
ILIM Pin Control Auto−Charge Mode
See Table 11 and Table 12 for the FAN5451x versions that
have this feature.
For FAN5451x versions where the BC1.2 adapter
detection circuit is disabled, the ILIM pin is used to set the
For FAN5451x versions where the BC1.2 adapter
detection circuit is enabled, the I
current limit prior to
BUS
establishing Host Control is determined by D+/D− Adapter
Detection at Plug In. If the adapter type cannot be identified
as either CDP or DCP, the charger will be configured to SDP
Auto−Charge.
I
current limit prior to Host Control.
BUS
ILIM Pin Auto−Charge uses the Safety Timer with the
current limit configured as per Table 11.
SDP Auto−Charge uses a dedicated SDP timer (t
) with
USB
I
BUS
the I
current limit configured as per Table 11. If the t
BUS
USB
timer is allowed to expire, the charger enters Standby State,
Table 11. IBUS CURRENT LIMIT (AUTO−CHARGE ONLY)
ILIM Pin Control
(ILIM Pin = HIGH)
ILIM Pin Control
(ILIM Pin = LOW)
Part Number
FAN54510A
FAN54511A
FAN54511AP
FAN54512A
FAN54513A
Configuration
BC1.2 Detection
ILIM Pin Control
ILIM Pin Control
BC1.2 Detection
ILIM Pin Control
BC1.2 SDP
500 mA
N/A
BC1.2 CDP/DCP
1500 mA
N/A
N/A
N/A
500 mA
500 mA
N/A
1500 mA
1500 mA
N/A
N/A
N/A
100 mA
N/A
1500 mA
N/A
100 mA
1500 mA
Table 12. CHARGE TIMER (AUTO−CHARGE ONLY)
Part Number
FAN54510A
FAN54511A
FAN54511AP
FAN54512A
FAN54513A
Configuration
BC1.2 Detection
ILIM Pin Control
ILIM Pin Control
BC1.2 Detection
ILIM Pin Control
BC1.2 SDP
BC1.2 CDP/DCP ILIM Pin Control
t
= 2 min.
N/A
Safety Timer
N/A
N/A
USB
Safety Timer
Safety Timer
N/A
N/A
N/A
t
= 45 min.
N/A
Safety Timer
N/A
USB
Safety Timer
www.onsemi.com
30
FAN54511
Table 13. CHARGE PARAMETER SETTING VS. OPERATING MODE (HOST CONTROL ONLY)
Charger Bit Settings
IINLIM
IBUSLIM
500 mA
500 mA
500 mA
500 mA
500 mA
500 mA
PRECHG
IOCHRG
X
STAT
PWROK
Operating Mode
Linear
V
V
BAT
SOURCE
Valid
< V
1000 mA
1000 mA
1000 mA
1000 mA
1000 mA
1000 mA
50 mA
1
1
1
1
0
1
0
0
0
1
1
1
SHORT
BATMIN
BATMIN
Pre−Charge
FAST Charge
FAST Charge
Top−Off
Valid
Valid
Valid
Valid
Valid
< V
> V
450 mA
X
X
X
X
X
1000 mA
1000 mA
1000 mA
1000 mA
> V
> V
> V
LOWV
LOWV
LOWV
Recharge
Linear Pre−Charge Mode
Good Battery Threshold (VLOWV)
At the beginning of charging, if V
< V
, the
The VLOWV (REG 0Ch[5:3]) bits define a battery
voltage threshold between 3.0 V and 3.7 V where an
interrupt is generated. The system designer can use this
interrupt to indicate that full system power is available or for
any other purpose. Charge parameters are not affected by
VLOWV.
BAT
SHORT
BATFET (Q4) operates as a linear current source with its
current limited to 50 mA (I ) in order to safely recover
SHORT
a battery pack with an open protection switch. Additionally,
the IC delivers power to SYS by regulating V
default VSYS (REG 0Dh[1:0]) setting.
to the
SYS
APPLICABLE STATUS AND INTERRUPTS
Pre−Charge (IPP) Mode
At the beginning of charging, if V
Pins:
/INT
< V
SHORT
<
BAT
from
SHORT
Interrupt Bits:
Status Bits:
VLOWVTH (REG 04h[4])
PWROK (REG 00h[4])
V , or if V
BATMIN
has transitioned above V
BAT
Linear Pre−Charge Mode, the IC enters Pre−Charge Mode
while delivering power to SYS.
During Pre−Charge Mode, the BATFET (Q4) will operate
as a linear current source with its current limited to the
PRECHG (REG 13h[3:0]) setting. The IC will regulate
Constant Voltage (CV) Mode
When V
reaches V , as set by VFLOAT (REG
FLOAT
BAT
11h [7:0]), the charger enters the voltage regulation (CV
Mode) phase of charging. The PWM regulator goes from
regulating current across the BATFET (Q4) to regulating
voltage on the BATSNS pin. This results in charge current
declining.
V
SYS
to the VSYS (REG 0Dh[1:0]) setting and attempt to
charge the battery at less than or equal to the PRECHG
setting without allowing V to drop below V
All registers are programmable in Pre−Charge Mode.
.
BATMIN
SYS
The CV (REG 20h[0]) Monitor bit will be set to a “1”
while the IC is in CV Mode.
APPLICABLE STATUS AND INTERRUPT
/STAT
Pins:
/INT
Termination
Interrupt Bits:
Status Bits:
WKBAT (REG 04h[1])
Charge current termination is enabled when TE (REG
0Eh[3]) = “1”. When charge current falls below I
, as
TERM
PRE (REG 00h[2])
STAT (REG 00h[3])
set by ITERM (REG 13h[7:6]), for longer than the deglitch
time of 30 ms, charging stops, Q4 turns off, an interrupt is
issued, and the IC enters Idle State (Charge Complete) if
TOEN (REG 0Eh[2]) = “0”. The buck converter will
regulate SYS to VFLOAT (REG 11h[7:0]) and the battery
will support Supplemental Mode if required.
Fats Charge (IOCHRG) Mode
At the beginning of charging, if V
> V
, or if
BAT
BATMIN
V
has transitioned above V
from Pre−Charge
BAT
BATMIN
Mode, the IC enters Fast Charge.
During Fast Charge Mode, the BATFET (Q4) is fully
enhanced and acts as a current sense element to limit charge
current per the IOCHRG (REG 12h[5:0]) setting. Battery
charging under constant current (CC) I
continues until the battery voltage reaches V
Recharge occurs after Termination (TE = “1”), if
RCHGDIS (REG 0Eh[5]) = “0”, when V
< V
–
BAT
FLOAT
V
.
RCHG
control
OCHG
Charge termination is blocked unless the I
threshold
TERM
.
FLOAT
is crossed while in CV Mode. If another control loop
(IBUSLIM, IOCHRG, DIVC) or Supplemental Mode
operation exist, termination will be prevented until the CV
condition is met.
APPLICABLE STATUS AND INTERRUPT
/INT
/STAT
Pins:
Interrupt Bits:
CHGMOD (REG 04h[2])
www.onsemi.com
31
FAN54511
APPLICABLE STATUS AND INTERRUPT
APPLICABLE STATUS AND INTERRUPT
/INT
/STAT
/INT
STAT
Pins:
Pins:
Interrupt Bits:
Status Bits:
CHGEND (REG 04h[3])
CHGCMP (REG 01h[4])
CHGEND (REG 04h[3])
TOCMP (REG 06h[7])
Interrupt Bits:
STAT (REG 00h[3])
LOIBAT (REG 01h[7])
TOCHG (REG 01h[3])
If TE = “0”, when the charge current falls below I
charging continues, an interrupt is issued, but the CHGCMP
bit is not set.
,
TERM
Status Bits:
System Current Prioritization
APPLICABLE STATUS, INTERRUPT AND MONITOR
During Charge Mode, if the current available to charge is
less than the programmed charge setting due to an input
current limit setting, source limitations, or system load
requirements, the current to the battery will be reduced to
support the system load.
Pins:
/INT
Interrupt Bits:
Status Bits:
Monitor Bits:
IBATLO (REG 05h[7])
LOIBAT (REG 01h[7])
ITERMCMP (REG 20h[7])
Top−Off Charging Mode
Supplemental Mode
During Charge Mode or Idle State, if the system load
exceeds what the buck converter can provide, V
Top−Off Charging occurs after Termination (TE = “1”) if
TOEN (REG 0Eh[2]) = “1”. The CHGEND interrupt will be
issued and Top−Off Charging begins 400 ms later with the
/STAT pin HIGH. During Top−Off Charging, the Battery
Absence Detection is retried every 5s unless TO_BDETDIS
(REG 1Bh[3]) is set to “1”.
The Top−Off Charging duration is set by the Top−Off
Timer, TOTMR (REG 1Bh[2:0]). See Top−Off Timer for
details.
will
below
SYS
drop. If a falling V
drops more than V
SYS
THSYS
V , the BATFET (Q4) will be fully enhanced to hold the
BAT
system up to V
.
BAT
Then, once a rising V
becomes higher than V
by
SYS
BAT
V , the BATFET (Q4) again serves as the current sense
THSYS
element to limit the charge current.
Table 14. SUMMARY OF BATFET (Q4) OPERATION VS. OPERATING MODE
PWM
OFF
ON
Operating Mode
SLEEP
CE#
X
V
V
BATFET (Q4)
SOURCE
BAT
Both < (VSYS + VSLP)
X
ON
Linear
ON
Linear and Pre−Charge
FAST Charge
0
Valid
Valid
X
> VSHORT & < VBATMIN
ON
0
> VBATMIN & < VSYS
OFF
ON
HZMODE (REG 0Eh[1]) = ”1”
Supplemental
X
X
ON
X
Valid
> VSYS
ON
CE# = “1” (disable Q4 with
Supplemental Mode
ON
ON
1
Valid
Valid
< VSYS
X
OFF
OFF
remaining functional)
PPOFF = ”1” (disable Q4 with
Supplemental Mode disabled)
X
www.onsemi.com
32
FAN54511
Source Plug Out
The IC continuously monitors V
CHARGER/BATTERY/SYSTEM PROTECTIONS
(or V ) during
IN
falls below the higher of
+V , the IC terminates charging
BUS
Dynamic Input Voltage Control
The IC includes a Dynamic Input Voltage Control (DIVC)
loop which automatically limits input current in case a
charging. If
V
SOURCE
V
or V
SOURCE(FALL)
BAT
SLP
and enters Sleep State (Standby).
APPLICABLE STATUS AND INTERRUPT
current−limited source is supplying V
or V . The
BUS
IN
control loop increases the charging current until either:
IBUSLIM / IINLIM or IOCHRG
/BUSOK
/INOK
Pins:
/INT
is reached or
VBUS = VBUSLIM or VIN = VINLIM
/STAT
VLOWTH (REG 04h[4])
VBUSINT (REG 04h[5])
VININT (REG 04h[6])
If an increase in load occurs on VSYS during charging that
causes VBUS or VIN to reduce below VBUSLIM or
VINLIM, the charge current is reduced until VBUS or VIN
Interrupt Bits:
Status Bits:
SLEEP (REG 00h[1])
VBUSPWR (REG 00h[5])
VINPWR (REG 00h[6])
INPUTSEL (REG 02h[7])
rise to the VBUSLIM or VINLIM threshold. At V
SOURCE
plug in, the VBUSLIM (REG 15h[3:0]) and VINLIM (REG
17h[3:0]) bits are always set to their default values.
CHARGING STATUS AND INTERRUPT
REPORTING
High−Impedance Mode and Disable
Setting the HZMODE (REG 0Eh[1]) bit to “1” or setting
the DIS pin to HIGH disables the charger and puts the IC into
High−Impedance Mode (HZ). The Safety Timer and Watch
Dog Timer are reset.
Charging Status
The /STAT pin is used to report the charge status to the
host processor. During charge, the /STAT pin is LOW. After
Termination, the /STAT pin goes HIGH and will remain
HIGH even during Top−Off Charging Mode.
The STAT (REG 00h[3]) bit indicates a “1” when charging
except during Top−Off.
If V
falls below V , with HZMODE set to “1”,
BATMIN
BAT
the HZMODE bit will automatically reset to “0”, and
charging will commence. Setting HZMODE = “1” when
V
BAT
V
BAT
< V
< V
is ignored. The DIS pin is functional when
.
BATMIN
BATMIN
APPLICABLE STATUS AND INTERRUPT
Pins:
/STAT
Safety Timer
Status Bits:
STAT (REG 00h[3])
At the beginning of charging, the IC starts the Safety
Timer. The Safety Timer consists of two segments,
Pre−Charge (PRETMR) and Fast Charge (FCTMR). The
Safety Timer can be programmed using the bits in the
TIMER (REG 19h) register.
Interrupts
The /INT pin is used to indicate that one or more
unmasked interrupt bits have been set.
The pin will remain LOW until all set interrupt bits
(Registers 04h to 06h) are read and cleared. In the event that
another interrupt occurs while the register containing the bit
is read, the interrupt will be stored in a buffer and transferred
to the register after the read. Thus, the /INT pin may remain
LOW until the register is read and cleared again.
APPLICABLE STATUS AND INTERRUPT
The Pre−Charge timer begins at the start of charging of a
battery whose voltage is less than V . Once the
BATMIN
battery voltage has risen above V , the Pre−Charge
BATMIN
Timer is cleared and the Fast Charge Timer begins. If the
battery voltage were to fall below V during Fast
BATMIN
Charge, the Fast Charge Timer will continue to run until the
battery is fully charged or the timer expires.
Pins:
/INT
Charging with the Safety Timer running is used for
charging that is unattended by the host. If the Safety Timer
expires charging ceases, all registers reset to their default
values, the device enters Idle State, and an interrupt is issued.
If the CONT (REG 0Eh[7]) = “1”, charging will continue
if the Safety Timer is allowed to expire.
INT 0 (REG 04h)
INT 1 (REG 05h)
INT 2 (REG 06h)
Interrupt Bits:
Interrupt Masking
Masking an interrupt bit using its corresponding mask bit,
found in registers 08h to 0Ah, prevents a masked interrupt
event from setting the /INT pin to LOW. The associated
interrupt bit will be set to “1”.
APPLICABLE STATUS AND INTERRUPT
/INT
/STAT
Pins:
Interrupt Bits:
Status Bits:
TIMER (REG 06h[0])
TMRTO Status bit (REG 02h[0])
www.onsemi.com
33
FAN54511
Watch Dog Timer (WDT)
Top−Off Timer
Setting WDEN (REG 19h[6]) to “1” enables the WDT and
disables, but does not clear the Safety Timer.
Setting TMRRST (REG19h[7]) to “1” resets the WDT.
The Top−Off timer duration is programmable using the
TOTMR (REG 1Bh [2:0]) bits. When the timer expires
charging stops, the BATFET (Q4) is disabled, an interrupt is
issued, and the device enters Idle State. If RCHGDIS (REG
This bit should be written at a rate more frequent than t
.
WD
If the WDT expires, charging continues on the remainder
of the time left on the Safety Timer. Additionally, all
registers except SAFETY (REG 1Ah[7:0]), are reset to their
default values, and an interrupt is issued. If WDTEXP (REG
30h[7]) = “1” and the WDT expires, the device will instead
immediately enter Idle State.
0Eh[5]) = “0”, the IC will return to Charge State when V
BAT
< V
– V
.
FLOAT
APPLICABLE STATUS AND INTERRUPT
RCHG
Pins:
/INT
Interrupt Bits:
Status Bits:
TOCMP (REG 06h[7])
CHGCMP (REG 01h[4])
APPLICABLE STATUS AND INTERRUPT
/INT
/STAT
Pins:
Interrupt Bits:
Status Bits:
TIMER (REG 06h[0])
WDTTO (REG 02h[1])
Table 15. SUMMARY OF TIMERS
Name
Control Register
19h[4:3]
Range (Minutes)
100 sec to 36 min.
4 hr to 16 hr
Default
On, 36 min.
On, 8 hr
Off
Pre−Charge
Fast Charge
Watch Dog
Top – Off
19h[2:0]
19h[6]
100 sec
1Bh[2:0]
10 min. to 70 min.
On, 30 min.
Thermal Regulation
Thermal Shutdown
When the IC’s junction temperature reaches the
If the junction temperature increases beyond the Thermal
Shutdown threshold, T , charging is suspended
programmable Thermal Regulation threshold, T
, set
REGTH
SHUTDOWN
by TREGTH (REG (0Fh[6:5]), the thermal regulation loop
reduces charge current to the lowest IOCHRG (REG
12h[5:0]) setting (200 mA) to prevent overheating.
and the buck converter is disabled. While suspended, all
timers stop and registers do not reset. Charging resumes only
after the die temperature falls below T
where I
REGTH
OCHRG
The device will attempt to charge the battery at a
maximum average current while maintaining the die
will be stepped back up to the programmed IOCHRG
setting.
temperature at or below T
. This is accomplished by
APPLICABLE STATUS AND INTERRUPT
REGTH
stepping I
from the lowest IOCHRG setting back up
OCHRG
/INT
Pins:
/STAT
to the programmed IOCHRG setting. If T
reached the process is repeated.
During Thermal Regulation, the IBUSLIM and IINLIM
input current limit settings are retained in order to support
the system load from a valid power source.
is again
REGTH
Interrupt Bits:
Status Bits:
ICTEMP (REG (06h[4])
TEMPSD (REG (02h[5])
Register Reset Conditions
2
As an added layer of safety, the I C control bits
automatically reset to their default values under certain
situations. Refer to Table 16 for details.
APPLICABLE STATUS AND INTERRUPT
Pins:
/INT
Interrupt Bits:
Status Bits:
ICTEMP (REG (06h[4])
TEMPFB (REG 02h[4])
www.onsemi.com
34
FAN54511
Table 16. REGISTER RESET SUMMARY
Reset Condition Description
Registers that are Reset
Behavior After Reset Event
VBUS/VIN plug in (from no input connected)
VBUSLIM = 4.56 V
VINLIM = 4.56 V
VBUSLIM and VINLIM only
and any V
voltage
BAT
VBUS/VIN plug in (from no input connected) All registers except STATUS, and IN
and V < V TERRUPT
Pre−Charge with default settings;
Q4 in Linear Region
BAT
SHORT
VBUS/VIN plug in (from no input connected) All registers except SAFETY, STATUS, and
Pre−Charge with default settings;
Q4 in Linear Region
and V
< V
< V
INTERRUPT
SHORT
BAT
BATMIN
V
falls below V
with an input
Pre−Charge at programmed settings;
Q4 in Linear Region
BAT
BATMIN
HZMODE bit only
connected
VFLOAT, IOCHRG, PRECHG, ITERM,
SAFETY
Buck regulates at V ; Q4 Off
FLOAT
Battery Removal Detected (input connected)
Buck regulates at 4.35 V;
Charging stops;
Q4 Off
Pre−Charge / Fast Charge Safety Timer Ex-
piration
Charge Mode Watchdog Timer Expiration
(WDTEXP=”0”)
Charging continues with default settings;
Q4 On
Buck regulates at 4.35 V;
Charging stops;
Q4 Off
Charge Mode Watchdog Timer Expiration
(WDTEXP= “1”)
All registers except SAFETY, STATUS, and
INTERRUPT
Boost Off;
Q3 Off;
Q4 On
OTG Boost Mode Watchdog Timer Expira-
tion
Set RESET (REG 0Fh[7]) = “1”
(Charge Mode)
Charging continues with default settings;
Q4 On
Boost Off;
Q3 Off;
Q4 On
Set RESET (REG 0Fh[7]) = “1”
(OTG Boost Mode)
JEITA Charging
The IC reduces I
To disable the thermistor circuit, tie the NTC pin to GND.
This also disables the REF output. Before enabling the
charger, the IC tests to see if NTC is shorted to GND. If NTC
is shorted to GND, the NTCGND monitor bit (REG 21h[2])
will be set, no thermistor readings will take place, the
NTCOK bit (REG 18h[4]) and NTC4−NTC1 (REG
18h[3:0]) bits will be reset.
and V
if the measured
OCHRG
FLOAT
battery temperature is outside of the fast charging limits
(Between T2 to T3) as described in the JEITA specification.
There are four battery temperature thresholds that change
battery charger operation: T1, T2, T3, and T4.
The IC first measures the NTC immediately prior to
entering any PWM charging state, and then measures the
NTC once per second, updating the result in the
NTC4−NTC1 bits (REG 18h[3:0]).
APPLICABLE STATUS AND INTERRUPTS
Pins:
/INT
Interrupt Bits:
BATTEMP (REG 06h[3])
The Host processor can disable JEITA charging reduction
by setting the TEMPDIS (REG 18h[5]) bit to “1”.
JEITA (REG 02h[3])
TBAT (REG 02h[2])
Status Bits:
Table 17. BATTERY TEMPERATURE THRESHOLDS, FOR USE WITH 10 K NTC, ꢂ = 3380, and RREF = 10 K
Threshold
T
(5C)
% of VREF
73.9
BAT
T1
T2
T3
T4
0°C
10°C
45°C
60°C
64.6
32.9
23.3
www.onsemi.com
35
FAN54511
Table 18. ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
T
(5C)
I
V
FLOAT
NTC4−1
0000
JEITA
TBAT
Notes
BAT
OCHRG
Below T1
Charging disabled (Q4 open)
1
1
1
0
Between T1
and T2
V
V
V
– 200 mV
0001
If IOCHRG is programmed to less than
400 mA, the charge current will be limited
to 200 mA.
FLOAT
FLOAT
FLOAT
I
/ 2
OCHRG
Between T2
and T3
I
0011
0111
1111
0
1
1
0
0
1
OCHRG
Between T3
and T4
I
/ 2
– 200 mV
If IOCHRG is programmed to less than
400 mA, the charge current will be limited
to 200 mA.
OCHRG
Above T4
Charging disabled (Q4 open)
Table 19. TEMPERATURE THRESHOLD WITH VARIOUS THERMISTORS, RREF = RTHRM AT 25 5C
Parameter
Various Thermistors
R
10K
3380
0°C
10K
3940
3°C
47K
4050
6°C
100K
4250
8°C
°
THRM(25 C)
β
T1
T2
T3
T4
10°C
45°C
60°C
12°C
42°C
55°C
13°C
41°C
53°C
14°C
40°C
51°C
VBUS Over−Voltage Protection
APPLICABLE STATUS AND INTERRUPT
When V
> V , the IC stops switching, fully
BUSOVP
BUS
enhances Q4 to support SYS load, and issues an interrupt.
When V falls below V – V ,
BUSOVP(HYS)
charging resumes after VBUS is revalidated, where another
interrupt is issued.
/INOK
/INT
Pins:
BUS
BUSOVP
/STAT
VININT (REG 04h[6])
OVPINPUT (REG 06h[6])
Interrupt Bits:
Status Bits:
If V
> V , VIN cannot be used as a charging
BUSOVP
BUS
INPUTOVP (REG 02h[6])
source.
APPLICABLE STATUS AND INTERRUPT
VBAT Over−Voltage Protection
The FLOAT voltage regulation loop prevents V
/BUSOK
from
if the battery
BAT
/INT
Pins:
overshooting V
by more than V
FLOAT
BAT_OVP
/STAT
is removed during Charge Mode with TE (REG 0Eh[3]) =
“0” or “1”.
Additionally, if the battery is removed during Charge
Mode and TE = “0”, the IC will remain in Charge Mode.
Then if a battery is inserted that is charged to a voltage higher
VBUSINT (REG 04h[5])
OVPINPUT (REG 06h[6])
Interrupt Bits:
Status Bits:
INPUTOVP (REG 02h[6])
VIN Over−Voltage Protection
than 1.05 * V
;
FLOAT
When V > V
, the IC stops switching, opens Q5,
INOVP
IN
1.
2.
3.
PWM pulses stop while V
> V
.
BAT
FLOAT
fully enhances Q4 to support SYS load, and issues an
interrupt.
HIVBAT (REG 20h[3]) monitor bit set to “1”.
BATFET (Q4) remains on to support the
system, thus removing excess charge from the
battery.
When V falls below V
– V
, charging
IN
INOVP
INOVP(HYS)
resumes after VIN is revalidated, where another interrupt is
issued.
If V > V
, VBUS cannot be used as a charging
INOVP
IN
source.
www.onsemi.com
36
FAN54511
Battery Absence Detection while Charging
The IC can detect the presence, absence, or removal of a
battery if TE (REG 0Eh[3]) = “1” and CE# = “0”. During
APPLICABLE STATUS AND INTERRUPT
Pins:
/INT
normal charging, once V
= V
and the charge
BAT
FLOAT
Interrupt Bits:
BATOCP (REG 06h[1])
current falls below I
provide power to SYS, the BATFET (Q4) is turned off
except to support Supplemental Mode, and the IC enters Idle
, the PWM charger continues to
TERM
Safety Register
The IC contains a SAFETY (REG 1Ah) register that
prevents the values in FLOAT (REG 11h[7:0]) and
IOCHRG (REG 12h[5:0]) from being set to unsafe levels.
The VSAFE (REG 1Ah[7:4]) and ISAFE (REG 1Ah[3:0])
register bits within the SAFETY register set a maximum
programmable value for FLOAT and IOCHRG.
State. It then turns on a battery discharge current, I
,
DETECT
for t
. If V
DETECT
is still above V
– V
, the
BAT
FLOAT
RCHG
battery is present and the NOBAT bit is maintained at “0”.
If V is below V – V , the battery is absent and
BAT
FLOAT
RCHG
the IC resets all charging related registers to their default
values (FLOAT, IOCHRG, PRECHG, and ITERM) and
issues an interrupt.
After V
rises above V
, the SAFETY register is
SHORT
BAT
loaded with its default value and may be changed on the first
write to the SAFETY register and only before writing to any
other register. The VSAFE and ISAFE values must be
written to the register at the same time. After first writing to
the SAFETY register or any other register, the SAFETY
register is locked.
By default the IC will retry Battery Absence Detection
every t
(2.1 s) unless NOBATOP (REG 0Eh[4]) = “0”.
INT
APPLICABLE STATUS AND INTERRUPT
Pins:
/INT
Interrupt Bits:
Status Bits:
BATINT (REG 04h[0])
NOBAT (REG. 00h[0])
The SAFETY register will reset to default values when
V
BAT
< V . The SAFETY register does not reset if the
SHORT
Safety Timer or WDT timer expires.
Battery Under−Voltage Protection
The battery voltage falling below V
charging indicates that a catastrophic event has occurred on
the BAT pin. If the battery voltage drops below V
during battery
SHORT
Ship Mode
Ship Mode is a state where the BATFET (Q4) is
configured to isolate the battery from the system load to
minimize battery discharge current to the system. This mode
of operation is useful for preserving the battery life of a
mobile device during extended shipping and storage
durations. Ship Mode is also useful for production testing of
a mobile device without having to drain the battery.
The /SHIP pin controls entry into and exit out of Ship
Mode. To enter Ship Mode, the /SHIP pin must be held LOW
SHORT
during charging, the IC will automatically disable the
BATFET (Q4) to stop current flow to the battery node, and
issue an interrupt. The IC enters the Idle State where the
buck converter continues to provide power to the system. If
the battery voltage recovers above V , Q4 remains off
SHORT
(Idle State is maintained) and BATSHORT is set to “1”. This
implementation is intended to lock out battery charging. The
only way to restart charging is to first remove V , and
SOURCE
for t
. To exit Ship Mode, /SHIP must be first
SHIPENTER
then reconnect a valid VIN or VBUS power source.
APPLICABLE STATUS AND INTERRUPT
released and then held LOW for t . This
SHIPEXIT
configuration prevents accidental entry into and exit out of
Ship Mode with a single key press of a mobile device’s
power button. An alternate method for exiting Ship Mode is
to reapply a valid source to VBUS or VIN. Once the source
has been validated, the charger IC will exit Ship Mode.
Ship Mode can also be programmed using the PPOFF
(REG 0Fh[1]) and PPOFFSLP (REG 0Fh[2]) control bits.
Setting PPOFF to “1” will disable Q4 and isolate the battery
from the system load. As long as there is input power to
/INT
/STAT
Pins:
Interrupt Bits:
Status Bits:
Monitor Bits:
SHORTBAT (REG 06h[5])
LOIBAT (REG 01h[7])
BATSHORT (REG 20h[4])
BATFET (Q4) Over−Current Protection
In order to prevent damage to the charger and battery due
to a potentially dangerous fault on the SYS pin, the IC
prevents its internal BATFET(Q4) from allowing excessive
2
maintain the charger’s I C port, setting PPOFF back to “0”
will re−enable Q4.
battery discharge current for more than T . The Q4
SCQUAL
Setting PPOFFSLP to “1” while there is input power
connected will disable Q4 once power is removed from
VBUS and VIN. Once power is reapplied, the charger IC
will automatically enable Q4.
The PPOFF and PPOFFSLP bits are automatically
controlled by the /SHIP pin. When entering Ship Mode
using the /SHIP pin, PPOFF and PPOFFSLP are set to “1”.
When exiting Ship Mode using the /SHIP pin, PPOFF and
PPOFFSLP are reset to “0”.
short circuit current limit (I ) is set for 9 A (typical).
LIMQ4SC
If the battery is connected and the discharge current through
Q4 exceeds I
time (1 ms), Q4 will be disabled for the t
for more than the t
deglitch
recovery
LIMQ4SC
SCQUAL
SCRECOV
time of 2 seconds. Once the 2 seconds has passed, Q4 will
turn on and check if the over−current condition still exists.
If the over−current condition still exists, Q4 will be disabled
again for 2 seconds. This cycle will repeat until the
over−current condition is removed.
www.onsemi.com
37
FAN54511
Hardware Reset
pull−down. After the 512 ms period has passed, Q4 is
This is a factory configurable option of the /SHIP pin.
The Ship Mode feature can be disabled and the /SHIP pin
can also be reconfigured to perform a Hardware Reset.
When the /SHIP pin is held LOW for 8 s it will disable Q4
for 512 ms and discharge SYS using an internal 200 W
re−enabled and the 200 W pull−down is disconnected from
SYS. This feature allows for a quick system restart of a
mobile device with an embedded battery by eliminating the
time needed for the battery to self−discharge to the point
where its protection switch opens.
VBAT
/SHIP
0V
tSHIPENTER
tSHIPENTER
tSHIPEXIT
tSHIPEXIT
tSHIPENTER
tSHIPENTER
On
Q4 + Diode
Off
SDA/SCL
Figure 48. Ship Mode Control
APPLICABLE STATUS AND INTERRUPT
BOOST CIRCUIT DETAILS
Refer to: Boost State Diagram
Pins:
/INT
Q1 and Q2 operate as a synchronous boost regulator to
provide power to the VBUS pin for USB−On−the−Go
(OTG) applications using the battery as its input. The Boost
output voltage can be programmed using the VBOOST
(REG 1Ch[3:0]) bits.
Interrupt Bits:
Status Bits:
BSTWDTTO (Reg.05h[1])
BOOST (REG 01h[1])
Boost PWM Control
The IC uses a computed off−time and a regulated on−time
(with an enforced minimum) to regulate V . The
PMID
Boost Enable and Programming
regulator achieves excellent transient response by
Boost Mode can be enabled by setting the BOOSTEN
(REG 1Ch[5]) bit to “1”. BOOSTEN starts the boost
operation, regulating VBOOST (REG1Eh[3:0]) at the
PMID node. To provide power out to the VBUS pin, the
OTG bit (REG 1Ch[6]) must also be set to “1”. Whenever
boost mode is disabled, either by a fault or writing
BOOSTEN=”0”, the OTG bit will be automatically reset to
“0”.
The HZMODE (REG 0Eh[1]) bit will be ignored when the
boost is enabled. The device will return to High Impedance
Mode when BOOSTEN is set back to “0” or the DIS pin is
raised HIGH.
employing current−mode modulation.
Since V
is regulated at the PMID node, V
will
BOOST
BUS
exhibit a load−line equal to the R
of Q3.
DS(ON)
Boost PFM Mode
If V
> VREF
(nominally 5.00 V) when the
BOOST
PMID
minimum off−time has ended, the regulator enters PFM
Mode. Boost pulses are inhibited until
VREF . The minimum on−time is increased to enable
V
<
PMID
BOOST
the output to pump up sufficiently with each PFM boost
pulse. Therefore the regulator behaves like a constant
on−time regulator, with the bottom of its output voltage
ripple at V
in PFM Mode.
The boost should not be enabled with a valid VIN present.
If a source is plugged into VIN while the boost is already
running, VIN will be ignored (Q5 will remain off) until the
boost is disabled.
BOOST
Boost Startup
As the device should be in the Standby State when the
boost is enabled, the BATFET (Q4) will already be enabled
to support the system.
Boost Mode and Timer Operation
It is recommended to enable the watchdog timer (t ) by
WD
setting WDEN (REG 19h[6]) bit to “1” to ensure that the
host processor is controlling Boost Mode operation. The
TMRRST (REG 19h[7]) bit must be set by the host before
the t
timer times out. If t
times out in Boost Mode, the
WD
WD
BOOSTEN and OTG bits are reset, and an interrupt is
issued.
www.onsemi.com
38
FAN54511
APPLICABLE STATUS AND INTERRUPT
Status Bits: BOOST (REG 01h[1])
Soft−Start State
By setting BOOSTEN = “1”, the boost regulator begins
switching with a reduced peak current limit of 50% of its
If V
fails to reach V −400 mV within 1 ms, a
PMID
BUS
normal current limit (I
). The output slews up
boost fault state is initiated, and an interrupt is issued.
APPLICABLE STATUS AND INTERRUPT
LIMPK(BST)
until V
is within 5% of its setpoint (V ); at which
PMID
BST
time, the regulation loop is closed and the current limit is set
to 100%.
Pins:
/INT
Interrupt Bits:
BSTFAIL (REG 05h[3])
If the output fails to achieve 95% of its setpoint within
128 ms, the current limit is increased to 100%. If the output
fails to achieve 95% of its setpoint after an additional 1 ms
period, a boost fault state is initiated and an interrupt is
issued.
Boost State
This is the normal operating mode of the boost regulator.
V
V
IN
The minimum t
the regulator’s switching frequency relatively constant in
CCM.
is proportional to OUT , which keeps
OFF
APPLICABLE STATUS AND INTERRUPT
Pins:
/INT
Interrupt Bits:
BSTFAIL (Reg.05h[3])
Boost Alert
Short Check State
When the battery voltage falls below 3.0 V an interrupt is
issued warning that the battery is depleted. The /INT pin is
pulled low to alert the processor of the condition.
BOOSTEN is not reset.
The OTG (REG 1Ch[6]) control bit needs to be set in order
to pass the boost output voltage (PMID) to V for USB
BUS
On−the−Go operation. Once OTG is set to “1”, the Short
Check state enables a resistor from PMIDto V and waits
BUS
APPLICABLE STATUS AND INTERRUPT
for V
to rise to about 1.5 V before proceeding with the
BUS
Pins:
/INT
VBUS Connect State. This prevents high current drain from
the battery, which could occur if Q3 is turned on into a short
circuit.
Interrupt Bits:
Status Bits:
VBATLV (REG 05h[0])
BATLO (REG 01h[0])
If V
fails to rise above 1.5 V within 8 ms, an interrupt
BUS
Boost Faults
If a BOOST fault occurs:
is issued, the resistor is disconnected between PMID and
VBUS, and V remains regulated to V
.
BOOST
PMID
APPLICABLE STATUS AND INTERRUPT
1. The /INT Pin is pulled low for Interrupt faults.
2. BOOSTEN bit is reset to “0”. OTG bit is reset to
“0”. Q3 is opened.
Pins:
/INT
OTGOCP (REG 06h[2])
3. BOOST status bit is cleared.
Interrupt Bits:
4. The power stage is in High−Impedance Mode.
5. Interrupt bits are set per Table 20.
BOOSTEN is reset on boost faults. Boost Mode can only
be re−enabled by setting the BOOSTEN bit.
If the VBUS fault is removed, Short Check State will
automatically retry after 2 seconds, and then proceed to the
VBUS Connect State
VBUS Connect State
Boost Shutdown
If a short is not detected on V
during the Short Check
BUS
When the boost regulator is shut down (BOOSTEN =
State, Q3 will fully turn on and provide a low impedance
path between PMID and VBUS. The resistor between PMID
“0”), current flow is prevented from V
to V , as well
BUS
BAT
as reverse flow from V
to V
.
and VBUS is left connected. This state ends when V
BUS
BAT
BUS
rises above V
−400 mV within a 1 ms period, at which
PMID
point boost regulation is achieved and a Status bit is set.
Table 20. FAULT BITS DURING BOOST MODE
Fault Name
Fault Bit
Fault Description
V > V
PMID
BSTOVP
REG 05h[5]
BOOST_OVP
V
PMID
fails to achieve the voltage required to advance to the next state during soft−start
or sustained ( > 50 ms) current limit during the BST state.
BSTFAIL
REG 05h[3]
BATUVL
BSTTSD
REG 05h[2]
REG 05h[4]
REG 05h[1]
V
< UVLO
BAT BST
Thermal Shutdown (T > T
)
REGTH
BSTWDTTO
Boost Watch Dog Timer Fault
www.onsemi.com
39
FAN54511
Data change allowed
LDO
The FAN5451x provides a 4.95 V (typical), 10 mA LDO
that is sourced by PMID. The LDO is automatically enabled
32 ms after V or V Plug In.
The LDO can be disabled by setting LDO_OFF (REG
0Dh[5]) to “1”. The LDO output voltage can be programmed
using the VLDO (REG 0Dh[4:3]) bits.
Whenever the FAN5451x is operating in boost mode
(BOOSTEN = “1”), the LDO will be disabled. When the
LDO is disabled, an internal switch pulls the output low
through a 1.2 kΩ pull−down resistor.
SDA
SCL
BUS
IN
TH
TSU
Figure 49. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH.
LDO and GPO Configurations
FAN54511A, FAN54511AP, FAN54513A only
The LDO output sources the high side of the GPO1 and
GPO2 CMOS output drivers, while the gate of the output
drivers are controlled by the GPO2 (REG 0Dh [7]) and
GPO1 (REG 0Dh [6]) control bits. LDO and GPO1 are
enabled by default.
THD;STA
Slave Address
SDA
SCL
MS Bit
2
I C INTERFACE
Figure 50. Start Bit
The FAN5451x’s serial interface is compatible with
Standard, Fast, Fast Plus, and High−Speed Mode I2C bus
specifications. The FAN5451x’s SCL line is an input and its
SDA line is a bi−directional open−drain output; it can only
pull down the bus when active. The SDA line only pulls low
during data reads and when signaling ACK. All data is
shifted in MSB (bit 7) first.
A transaction ends with a STOP condition, which is
defined as SDA transitioning from “0” to “1” with SCL high.
Slave Releases Master Drives
tHD;STO
ACK(0) or
NACK(1)
SDA
SCL
Slave Address
Table 21. I2C Slave Address Byte
Figure 51. Stop Bit
7
6
5
4
3
2
1
0
During a read from the FAN5451x, the master issues a
Repeated Start after sending the register address and before
resending the slave address. The Repeated Start is a 1−to−0
transition on SDA while SCL is high.
1
1
0
1
0
1
1
R/W
In hex notation, the slave address assumes a “0” LSB. The
hex slave address is D6H (8−bit write address) for all parts
in the family. Other slave addresses can be accommodated
upon request. Contact your ON Semiconductor
representative.
High−Speed (HS) Mode
The protocols for High−Speed (HS), Low−Speed (LS),
and Fast−Speed (FS) Modes are identical except the bus
speed for HS Mode is 3.4 MHz. HS Mode is entered when
the bus master sends the HS master code 00001XXX after
a start condition. The master code is sent in Fast or Fast Plus
Mode (maximum 1 MHz clock); slaves do not ACK this
transmission.
Bus Timing
As shown in Data Transfer Timing, data is normally
transferred when SCL is low. Data is clocked in on the rising
edge of SCL. Typically, data transitions shortly at or after the
falling edge of SCL to allow ample time for the data to set
up before the next SCL rising edge.
www.onsemi.com
40
FAN54511
Slave Releases
tSU;STA
tHD;STA
The master then generates a repeated start condition that
ACK(0) or
NACK(1)
SLADDR
MS Bit
causes all slaves on the bus to switch to HS Mode. The
master then sends I2C packets, as described above, using the
HS Mode clock rate and timing.
SDA
SCL
The bus remains in HS Mode until a stop bit is sent by the
master. While in HS Mode, packets are separated by
repeated start conditions.
Figure 52. Repeated Start Time
READ AND WRITE TRANSACTIONS
Table 22. BIT DEFINITIONS
Symbol
Definition
S
A
A
R
P
START
ACK. The slave drives SDA to 0 acknowledge the preceding packet.
NACK. The slave sends a 1 to NACK the preceding packet.
REPEATED START
STOP
0
0
0
7 bits
8 bits
8 bits
Data
S
Slave Address
0
A
Reg Addr
A
A
P
Figure 53. Write Transaction
0
0
0
1
7 bits
Slave Address
8 bits
Reg Addr
7 bits
8 bits
Data
S
0
A
A
R
Slave Address
1
A
A
P
Figure 54. Read Transactions
www.onsemi.com
41
FAN54511
SOLUTION DESIGN RECOMMENDATION
Figure 55. Recommended Component Placement and Routing
Figure 56. Recommended GND Connections
www.onsemi.com
42
FAN54511
REGISTER AND BIT DESCRIPTIONS
The default states of the registers are with only the battery connected (VBUS and VIN not connected).
Table 23. I2C REGISTER MAP
REG NAME
STATUS 0
STATUS 1
STATUS 2
INT 0
ADR
00h
01h
02h
04h
05h
06h
08h
09h
0Ah
0Ch
0Dh
0Eh
0Fh
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Fh
20h
21h
2Dh
30h
DEFAULT
1000_0010
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0011_1111
0101_0111
0001_1100
0100_0000
0110_1001
0001_0000
1001_1000
0001_0000
0010_0100
0001_1011
0001_0100
0000_1111
0001_1011
1111_1111
0000_0011
0001_0010
0000_0000
1000_0110
1010_0XXX
10XX_XXXX
0010_0000
Bit 7
RESERVED
LOIBAT
Bit 6
Bit 5
Bit 4
PWROK
Bit 3
STAT
Bit 2
PRE
Bit 1
SLEEP
Bit 0
NOBAT
BATLO
VINPWR
VBUSPWR
CHGDET
CHGCMP
TEMPFB
VLOWTH
BSTTSD
ICTEMP
TOCHG
DIVC
BOOST
INPUTSEL
VALFAIL
IBATLO
INPUTOVP
VININT
TEMPSD
VBUSINT
JEITA
TBAT
WDTTO
TMRTO
BATINT
VBATLV
TIMER
CHGEND
BSTFAIL
BATTEMP
MCHGEND
MBSTFAIL
MBATTEMP
CHGMOD
BATUVL
OTGOCP
MCHGMOD
MBATUVL
MOTGOCP
WKBAT
INT 1
RCHGN
BSTOVP
BSTWDTTO
BATOCP
MWKBAT
RESERVED
MBATOCP
VBATMIN
INT 2
TOCMP
OVPINPUT
MVININT
SHORTBAT
MVBUSINT
MBSTOVP
MSHORTBAT
MINT 0
MVALFAIL
MIBATLO
MTOCMP
MVLOWTH
MBSTTSD
MICTEMP
VLOWV
MBATINT
MVBATLV
MTIMER
MINT 1
MRCHGN
MOVPINPUT
MINT 2
CONTROL 0
CONTROL 1
CONTROL 2
CONTROL 3
VFLOAT
IOCHRG
IBAT
RESERVED
GP02
CONT
RESET
GPO1
LDO_OFF
RCHGDIS
VLDO
RESERVED
TOEN
VSYS
RESERVED
NOBATOP
TE
HZMODE
PPOFF
RESERVED
CE#
TREGTH
RESERVED
FLOAT
PPOFFSLP
RESERVED
IOCHRG
ITERM
PRECHG
IBUS
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TMRRST WDEN
IBUSLIM
IINLIM
NTC4
VBUS
VBUSOVP
VINOVP
VBUSLIM
VINLIM
IIN
VIN
NTC
TEMPDIS
RESERVED
NTCOK
PRETMR
SAFETY
TO_BDETDIS
NTC3
NTC2
NTC1
TIMER
FCTMR
SAFETY
TOPOFF
BOOST
DPLUS
RESERVED
TOTMR
RESERVED
FORCEDET
ITERMCMP
RESERVED
OTG
BOOSTEN
RESERVED
RESERVED
BATSHORT HIVBAT
ISRCCMP
VBOOST
SETTMR0
CV
MONITOR 0
MONITOR 1
IC_INFO
VBATCMP
PMIDVBAT
VLOWVCMP
PPON
IBUS#
ICHG#
DISPIN
REV
BUCKON
PN
NTCGND
ILIMPIN
VENDOR CODE
FEATURE
CONTROL
WDTEXP
RESERVED
DIVCON
DISREF
RESERVED
RESERVED
www.onsemi.com
43
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
STATUS 0 Register Address: 00h Default Value = 1000 0010
Bit
Name
Value
Type
Description
Reserved. This bit should always read “1”.
A “1” indicates that an input source voltage at V has risen above V
7
RESERVED
1
R
and
SOURCE(RISE)
SOURCE(FALL)
IN
passed validation, and a valid VBUS is not present. To maintain a “1” V
< V
IN
6
5
4
VINPWR
0
0
0
R
R
R
< V
and V > V
+ V
BAT SLP.
INOVP
IN
VINPWR will not be set to “1” if VBUSPWR = “1”.
A “1” indicates that an input source voltage at V
passed validation. To maintain a “1”
has risen above V
and
BUS
SOURCE(RISE)
VBUSPWR
PWROK
V
< V
< V
and V
> V
+ V
BAT SLP.
SOURCE(FALL)
BUS
BUSOVP
BUS
A “1” indicates that V
> V
during charging.
BAT
LOWV
If HZ state is entered while PWROK is set to “1” and then V
falls below V
,
BAT
LOWV
PWROK will not reset to “0” until after the source is re−validated and the IC returns to
Charge Mode. Validation occurs whenever the part exits HZ State.
A “1” indicates the /STAT pin is pulled low when charging is being performed. This bit goes
3
2
STAT
PRE
0
0
R
R
to “0” during Top−Off charging.
A “1” indicates that the charger is in Pre−Charge mode and a “0” indicates it is not. In con-
junction with the STAT (REG 00h[3]) bit, the system processor can determine the type of
charging being performed.
A “1” indicates that the charger is in sleep mode. Sleep mode is entered when the highest
available input source voltage drops below the higher of
1
0
SLEEP
NOBAT
1
0
R
R
V
+ V
or
.
BAT
SLP
VSOURCE(FALL)
A “1” indicates that the IC has determined there is no battery connected.
Register Address: 01h Default Value = 0000 0000
STATUS 1
Bit
Name
Value
Type
Description
A “1” indicates that the battery is present but the current has fallen below the I
threshold when TE= “0” or TOEN = “1”.
TERM
7
LOIBAT
0
R
Identifies the type of charger adapter connected to the VBUS input after adapter detection
is completed. (FAN54510A, FAN54512A only).
Binary
00
Adapter Type
6:5
CHGDET
00
R
Detection not completed
01
SDP
CDP
DCP
10
11
A “1” indicates that the battery is charged (I
when TE = “1”.
<
) and that charging has completed
BAT ITERM
4
3
2
CHGCMP
TOCHG
DIVC
0
0
0
R
R
R
This bit remains “0” during Top−Off charging.
A “1” indicates Top−Off charging mode.
A “1” indicates that the Dynamic Input Voltage Control loop is active.
If DIVC = “1”, the INPUTSEL (REG 02h[7]) status bit indicates whether the V
or
BUSLIM
V
INLIM
voltage control loop is active.
1
0
BOOST
BATLO
0
0
R
R
A “1” indicates the device is in boost mode.
A “1” indicates that V < 3.0 V during Boost Operation only.
BAT
www.onsemi.com
44
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
STATUS 2 Register Address: 02h Default Value = 0000 0000
Bit
Name
Value
Type
Description
Indicates which input is routed to PMID whenever a valid source is connected to VBUS or
VIN.
7
INPUTSEL
0
R
Binary
0
1
Input
VBUS
VIN
A “1” indicates that V
and/or V is higher than its OVP threshold. Switching is stopped
IN
BUS
to protect the IC and the BATFET (Q4) is turned on to support the system load.
If INPUTOVP = “1”, the INPUTSEL status bit (REG 02h[7]) state indicates whether the
6
INPUTOVP
0
R
OVP condition exists on V
or V .
BUS
IN
5
4
TEMPSD
TEMPFB
0
0
R
R
A “1” indicates the charger is in thermal shutdown.
A “1” indicates the charger is in thermal regulation.
A “1” indicates the battery temperature is outside the JEITA normal temperature range
during battery charging, charge current and float voltage have been reduced or charging
has stopped, and NTC (REG 18h[3:0]) = “0000”,“0001”,“0111”, or “1111”.
See (REG 18h[5:0]) for details on NTC operation.
3
2
JEITA
TBAT
0
0
R
R
A “1” indicates the battery temperature is unsafe and, therefore, charging has been
stopped and NTC (REG 18h[3:0]) = “0000” or “1111”
See (REG 18h[5:0]) for details on NTC operation.
A “1” indicates the 100sec Watch Dog Timer has timed out in Charge Mode. When the
watch dog timer expires, registers are reset to their default values and the WDEN (REG
19h[6]) control bit is cleared.
Setting WDEN (REG 19h[6]) = “1” or a re−insertion of VBUS or VIN will reset WDTTO
back to “0”.
1
0
WDTTO
TMRTO
0
0
R
R
A “1” indicates the safety timer expired during Pre−Charge or Fast Charge.
A re−insertion of VBUS or VIN will reset WDTTO back to “0”.
INT 0
Register Address: 04h
Default Value = 0000 0000
Bit
Name
Value
Type
Description
or V validation failed.
7
VALFAIL
0
RC
A “1” indicates that V
BUS
IN
VIN Plug In: A “1” indicates V > V
. The bit will remain “0” if VBUS is al-
IN
SOURCE(RISE)
ready present.
VIN Plug Out: A “1” indicates V < V
or V < V
+V
.
6
VININT
0
RC
IN
SOURCE(FALL)
IN
BAT
SLP
VBUS Plug Out with VIN Present: A “1” indicates that V > V
. This VIN in-
+V
IN
SOURCE(RISE)
terrupt will not occur, though, until V
< V
or V
< V
.
SLP
BUS
SOURCE(FALL)
BUS
BAT
VBUS Plug In: A “1” indicates V
> V
BUS
.
BUS
SOURCE(RISE)
5
4
VBUSINT
VLOWTH
0
0
RC
RC
VBUS Plug Out: A “1” indicates V
< V
or V
< V
+V
.
SOURCE(FALL)
BUS
BAT
SLP
A “1” indicates the battery voltage has risen above or fallen below the V
threshold
LOWV
during charging or V
> V
at the start of charging. The interrupt will also occur at
BAT
LOWV
Plug Out if V
> V
.
BAT
LOWV
A “1” indicates that the device has completed a normal charge cycle where I
has fallen
BAT
below the I
threshold if TE = “1”. If configured to do so, the IC may continue charging
3
CHGEND
0
RC
TERM
in Top Off with CHGEND = “1”.
A “1” indicates that the charging mode has changed between Pre−Charge and Fast
2
1
0
CHGMOD
WKBAT
0
0
0
RC
RC
RC
Charge modes.
A “1” indicates the battery is below the V
at Plug In.
threshold set in VBATMIN (REG 0Ch[2:0])
BATMIN
A “1” indicates that the IC has determined the battery presence has changed state.
See NOBAT (REG 00h[0]) status bit.
BATINT
www.onsemi.com
45
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
INT 1 Register Address: 05h Default Value = 0000 0000
Bit
Name
Value
Type
Description
A “1” indicates that the charging current has risen above or fallen below I
when
TERM
TE = “0”. The LOIBAT (REG 01h[7]) status bit should also be read to determine if the actu-
al charging current is above or below the I threshold.
7
IBATLO
0
RC
TERM
A “1” indicates that the battery voltage has fallen by V
has completed.
below V
after charging
RCHG
FLOAT
6
5
4
RCHGN
BSTOVP
BSTTSD
0
0
0
RC
RC
RC
A “1” indicates that VBUS has risen above the boost OVP threshold.
A “1” indicates that the IC junction temperature has exceeded the temperature shutdown
threshold, T , during boost operation.
REGTH
V
fails to achieve the voltage required to advance to the next state during soft−start or
BUS
3
BSTFAIL
0
RC
sustained (>50 ms) current limit during the boost state.
A “1” indicates that the battery voltage fell below UVLO
during boost operation or that
BST
2
1
0
BATUVL
BSTWDTTO
VBATLV
0
0
0
RC
RC
RC
V
< UVLO
when the boost is first enabled.
BAT
BST
A “1” indicates the 100sec Watch Dog Timer has timed out during Boost Operation.
Provides an interrupt bit for indicating that the battery has fallen below 3.0 V during Boost
Operation. Boost operation will continue until either BOOSTEN = “0” or V
< UVLO
BAT
BST.
INT 2
Register Address: 06h
Default Value = 0000 0000
Bit
Name
Value
Type
Description
A “1” indicates that Top−Off charging has completed with the expiration of the Top−Off
timer when both TE=”1” and TOEN=”1”.
7
TOCMP
0
RC
A “1” indicates that the V
or V voltage has risen above or fallen below the OVP
IN
BUS
6
5
OVPINPUT
SHORTBAT
0
0
RC
RC
threshold. See INPUTOVP (REG 02h[6]) Status bit.
A “1” indicates that V has fallen below V during charging.
BAT
SHORT
A “1” indicates that the IC temperature has risen high enough to trigger Thermal Regula-
tion (T ), or Thermal Shutdown (T ).
If ICTEMP = “1”, see TEMPFB (REG 02h[4]) and TEMPSD (REG 02h[5]) Status bits to
determine if the device is in Thermal Regulation or Thermal Shutdown.
REGTH
SHUTDOWN
4
ICTEMP
0
RC
A “1” indicates that the battery temperature has changed status.
If BATTEMP = “1”, see NTC (REG 18h[5:0]) for battery temperature details.
3
BATTEMP
0
RC
2
1
OTGOCP
BATOCP
0
0
RC
RC
A “1” indicates that the boost did not successfully pass the Short Check State.
A “1” indicates that the BATFET (Q4) has exceeded its discharge current limit.
If running from the Safety Timer, a “1” indicates that the safety timer for Pre−Charge or
Fast Charge has expired. See TMRTO (REG 02h[0]) Status bit.
If running from the Watch Dog Timer, a “1” indicates that the watch dog timer has expired
in boost or charge operation.
0
TIMER
0
RC
MINT 0
Register Address: 08h
Default Value = 0000 0000
Bit
7
Name
Value
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
MVALFAIL
MVININT
0
0
0
0
0
0
0
0
Writing a “1” masks VALFAIL = “1” from driving the /INT pin LOW.
Writing a “1” masks VININT = “1” from driving the /INT pin LOW.
Writing a “1” masks VBUSINT = “1” from driving the /INT pin LOW.
Writing a “1” masks LOWTH = “1” from driving the /INT pin LOW.
Writing a “1” masks CHGEND = “1” from driving the /INT pin LOW.
Writing a “1” masks CHGMOD = “1” from driving the /INT pin LOW.
Writing a “1” masks WKBAT = “1” from driving the /INT pin LOW.
Writing a “1” masks BATINT = “1” from driving the /INT pin LOW.
6
5
MVBUSINT
MVLOWTH
MCHGEND
MCHGMOD
MWKBAT
MBATINT
4
3
2
1
0
www.onsemi.com
46
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
MINT 1 Register Address: 09h Default Value = 0000 0000
Name
Bit
7
Value
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
MIBATLO
MRCHGN
MBSTOVP
MBSTTSD
MBSTFAIL
MBATUVL
Reserved
MVBATLV
0
0
0
0
0
0
0
0
Writing a “1” masks IBATLO = “1” from driving the /INT pin LOW.
Writing a “1” masks RCHGN = “1” from driving the /INT pin LOW.
Writing a “1” masks BSTOVP = “1” from driving the /INT pin LOW.
Writing a “1” masks BSSTSD = “1” from driving the /INT pin LOW.
Writing a “1” masks BSTFAIL = “1” from driving the /INT pin LOW.
Writing a “1” masks BATULV = “1” from driving the /INT pin LOW.
6
5
4
3
2
1
0
R/W
Writing a “1” masks VBATLV = “1” from driving the /INT pin LOW.
MINT 2
Register Address: 0Ah
Default Value = 0000 0000
Bit
7
Name
Value
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
MTOCMP
0
0
0
0
0
0
0
Writing a “1” masks TOCMP = “1” from driving the /INT pin LOW.
Writing a “1” masks OVPINPUT = “1” from driving the /INT pin LOW.
Writing a “1” masks SHORTBAT = “1” from driving the /INT pin LOW.
Writing a “1” masks ICTEMP = “1” from driving the /INT pin LOW.
Writing a “1” masks BATTEMP = “1” from driving the /INT pin LOW.
Writing a “1” masks OTGOCP = “1” from driving the /INT pin LOW.
Writing a “1” masks BATOCP = “1” from driving the /INT pin LOW.
6
MOVPINPUT
MSHORTBAT
MICTEMP
5
4
3
MBATTEMP
MOTGOCP
MBATOCP
2
1
Writing a “1” masks TIMER = “1” from driving the /INT pin low if CONT = “1”
(REG 0Eh [7]).
If CONT = “0”, MTIMER will be reset to “0” when a Pre−Charge or Fast Charge timer
expires and will, therefore, not mask /INT bit.
0
MTIMER
0
R/W
CONTROL 0
Register Address: 0Ch
Default Value = 0011 1111
Bit
Name
Value
Type
Description
7:6
Reserved
00
R
This sets the good battery voltage threshold on the BAT pin, above which full system pow-
er is available to the user.
Binary
000
001
010
011
V
(V)
LOWV
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
5:3
VLOWV
111
R/W
100
101
110
111
This sets the voltage threshold on the BAT pin above which Fast Charge begins.
VBATMIN should not be set lower than the minimum required system voltage.
Binary
000
001
010
011
V
(V)
BATmin
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
2:0
VBATMIN
111
R/W
100
101
110
111
www.onsemi.com
47
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
CONTROL 1 Register Address: 0Dh Default Value = 0101 0111
Bit
Name
Value
Type
Description
A “1” enables GPO2 to output logic high. GPO2 is sourced by the LDO. (FAN54511A,
FAN54511AP, FAN54513A only)
7
GPO2
0
R/W
A “1” enables GPO1 to output logic high. GPO1 is sourced by the LDO. (FAN54511A,
FAN54511AP, FAN54513A only)
6
5
GPO1
1
0
R/W
R/W
LDO_OFF
A “1” disables the LDO.
Sets the LDO output voltage. The LDO input is sourced from PMID.
Binary
00
V
(V)
LDO
3.30
3.60
4.95
5.05
4:3
2
VLDO
10
1
R/W
R
01
10
11
Reserved
Regulated system voltage in Pre−Charge Mode (V
< V
). VSYS should be pro-
BAT
BATMIN
grammed 250mV, or more, above the minimum required system voltage. With limited
available input power, V can be up to 250 mV below its programmed target level.
SYS
Binary
00
V
(V)
SYS
1:0
VSYS
11
R/W
3.3
3.4
3.5
3.6
01
10
11
CONTROL2
Register Address: 0Eh
Default Value = 0001 1100
Bit
Name
Value
Type
Description
Writing a “1” ignores a Pre−Charge or Fast Charge Safety Timer expiration fault and al-
lows the IC to continue charging. However, the TMRTO (REG 02h[0]) status bit and
TIMER (REG 06h[0]) interrupt bit will still be set to “1” upon timer expiration.
A “0” will reset all registers except SAFETY and put the charger IC into IDLE State when
the Pre−Charge or Fast Charge Safety Timer expires.
7
CONT
0
W
CONT does not affect the watchdog timer or top−off timer. Reading this bit always returns
“0”.
6
5
Reserved
RCHGDIS
0
0
R
Writing a “1” disables the automatic recharge function with TE = “1” when the battery volt-
R/W
age falls below V
– V
.
FLOAT
RCHG
For a “0”, if no battery is detected during source plug−in or when a Full Battery (end of
charge) is reached, the charger will not perform an additional battery absence test. The
buck converter will stay on and the BATFET turns off allowing the host processor to con-
tinue to run with no battery.
For a “1” if no battery is detected during source plug−in or when a Full Battery (end of
charge) is reached, the charger will perform a battery absence test every 2 seconds until a
battery is connected. The buck converter will stay on and the BATFET (Q4) turns off allow-
ing the host processor to continue to run with no battery.
4
NOBATOP
1
R/W
A “1” enables charge current termination and a “0” allows charging to continue even if I
TERM
BAT
3
2
TE
1
1
R/W
R/W
< I
.
TOEN
A “1” enables the Top−Off charging.
A “1” puts the IC in the High−Z state. This bit will be ignored when BOOSTEN = “1”, but
device will return to HZ state when BOOSTEN is set back to “0”.
1
0
HZMODE
Reserved
0
0
R/W
R
The bit will reset to “0” when V
this bit are ignored.
falls below V
. When V
< V
, writes to
BAT
BATMIN
BAT
BATMIN
www.onsemi.com
48
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
CONTROL3 Register Address: 0Fh Default Value = 0100 0000
Bit
Name
Value
Type
Description
Writing a “1” resets all registers to their defaults: writing a “0” has no effect.
Read returns “0”.
7
RESET
0
R/W
Temperature threshold at which the current is reduced to prevent the device from
overheating.
Binary
00
T
(°C)
REGTH
6:5
TREGTH
10
R/W
70
01
85
100
120
10
11
4:3
2
Reserved
0
0
R
PPOFFSLP is for automatic Ship Mode entry once the input source (VBUS or VIN) is
removed. When PPOFFSLP is set to a “1”, PPOFF will be automatically written to “1”
PPOFFSLP
R/W
when V
or V falls below V
.
BUS
IN
SOURCE(FALL)
PPOFFSLP will be reset to “0” once a valid input power source is connected.
Writing a “1” to this bit turns the BATFET (Q4) off immediately. While PPOFF is set to “1”,
supplemental mode is not allowed.
Bit Reset Behavior
1
0
PPOFF
CE#
0
0
R/W
R/W
PPOFFSLP = “1” (Ship Mode): PPOFF and PPOFFSLP will be reset to “0” when a valid
input source is connected.
PPOFFSLP=”0”: PPOFF will be reset to “0” when a valid input source is either removed or
connected.
During a normal charging condition, a “0” enables the BATFET, Q4 and a “1” disables the
BATFET (Q4) but will allow the battery to supplement the SYS load when V
BAT
falls below
SYS
V
.
www.onsemi.com
49
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
VFLOAT Register Address: 11h Default Value=0110 1001
Name
Bit
Value
Type
Description
Charger output “float” voltage, V
.
FLOAT
Programmable from 3.3 V to 4.72 V in 10 mV increments. Default is 4.35 V
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
V
(V)
Hex
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
V
(V)
Hex
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
V
(V)
FLOAT
FLOAT
FLOAT
3.30
3.31
3.32
3.33
3.34
3.35
3.36
3.37
3.38
3.39
3.40
3.41
3.42
3.43
3.44
3.45
3.46
3.47
3.48
3.49
3.50
3.51
3.52
3.53
3.54
3.55
3.56
3.57
3.58
3.59
3.60
3.61
3.62
3.63
3.64
3.65
3.66
3.67
3.68
3.69
3.70
3.71
3.72
3.73
3.74
3.75
3.76
3.77
3.78
3.79
3.80
3.81
3.82
3.83
3.84
3.85
3.86
3.87
3.88
3.89
3.90
3.91
3.92
3.93
3.94
3.95
3.96
3.97
3.98
3.99
4.00
4.01
4.02
4.03
4.04
4.05
4.06
4.07
4.08
4.09
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
4.22
4.23
4.24
4.25
4.26
4.27
4.28
4.29
4.30
4.31
4.32
4.33
4.34
4.35
4.36
4.37
4.38
4.39
4.40
4.41
4.42
4.43
4.44
4.45
4.46
4.47
4.48
4.49
4.50
4.51
4.52
4.53
4.54
4.55
4.56
4.57
4.58
4.59
4.60
4.61
4.62
4.63
4.64
4.65
4.66
4.67
4.68
4.69
4.70
4.71
4.72
7:0
FLOAT
01101001
R/W
Bits 8Fh − FFh = 4.72 V
www.onsemi.com
50
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
IOCHRG Register Address: 12h Default Value=0001 0000
Name
Reserved
Bit
Value
Type
Description
7:6
00
R
Sets the typical battery charging current, I
, during Fast Charging.
OCHRG
Programmable from 0.200 A to 3.200 A in 50 mA increments. Default is 1.000 A.
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
I
(A)
Hex
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
I
(A)
Hex
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
I (A)
OCHRG
OCHRG
OCHRG
0.200
0.250
0.300
0.350
0.400
0.450
0.500
0.550
0.600
0.650
0.700
0.750
0.800
0.850
0.900
0.950
1.000
1.050
1.100
1.150
1.200
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.450
2.500
2.550
2.600
2.650
2.700
2.750
2.800
2.850
2.900
2.950
3.000
3.050
3.100
3.150
3.200
5:0
IOCHRG
010000
R/W
12
13
14
Bits 3Dh − 3Fh = 3.200 A
IBAT
Register Address: 13h
Default Value = 1001 1000
Bit
Name
Value
Type
Description
Sets the termination current threshold, I
.
TERM
Programmable from 100 mA to 600 mA. Default is 300 mA.
If TE = “1” and the charge current falls below the termination current threshold, charging
will stop.
Binary
0000
0001
0010
0011
0100
0101
0110
0111
I
(A)
Binary
1000
1001
1010
1011
1100
1101
1110
1111
I
(A)
TERM
TERM
Reserved
Reserved
Reserved
0.100
0.250
0.300
0.350
0.400
0.450
0.500
0.550
0.600
7:4
ITERM
1001
R/W
0.125
0.150
0.175
0.200
Sets the typical battery charging current, I , during Pre−Charge Mode.
PP
Programmable from 200 mA to 800 mA. Default is 450 mA.
Binary
0000
0001
0010
0011
0100
0101
0110
0111
I
(A)
Binary
1000
1001
1010
1011
1100
1101
1110
1111
I
(A)
PP
PP
Reserved
Reserved
Reserved
0.200
0.450
0.500
0.550
0.600
0.650
0.700
0.750
0.800
3:0
PRECHG
1000
R/W
0.250
0.300
0.350
0.400
www.onsemi.com
51
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
IBUS
Register Address: 14h
Default Value = 0001 0000
Bit
Name
Value
Type
Description
7
Reserved
0
R
This sets the maximum input current limit, I
, from the VBUS input.
BUSLIM
Programmable from 100 mA to 3.00 A in 25 mA steps. Default is 500 mA.
There are 3 FET segmentation ranges: 00h (100 mA) to 08h (300 mA), 09h (325 mA) to
23h (975 mA), and 24h (1000 mA) to 7Fh (3000 mA). Refer to the Electrical Specifications
table for the associated R
values.
DS(ON)
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
I
(A)
Hex
(A)
Hex
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
I
(A)
Hex
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
I
(A)
BUSLIM
IBUSLIM
0.825
BUSLIM
BUSLIM
0.100
0.125
0.150
0.175
0.200
0.225
0.250
0.275
0.300
0.325
0.350
0.375
0.400
0.425
0.450
0.475
0.500
0.525
0.550
0.575
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
2.025
2.050
2.075
2.100
2.125
2.150
2.175
2.200
2.225
2.250
2.275
2.300
2.325
2.350
2.375
2.400
2.425
2.450
2.475
2.500
2.525
2.550
2.600
2.625
2.650
2.675
2.700
2.725
2.750
2.775
2.800
2.825
2.850
2.875
2.900
2.925
2.950
2.975
3.000
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
6:0
IBUSLIM
0010000
R/W
Bits 75h − 7Fh = 3.000 A
www.onsemi.com
52
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
VBUS Register Address: 15h Default Value = 0010 0100
Bit
Name
Value
Type
Description
7:6
Reserved
00
R
This sets the V
threshold.
BUS_OVP
Binary
00
V
(V)
BUS_OVP
6.5
5:4
VBUSOVP
10
R/W
01
10.5
13.7
10
11
Reserved
This sets the V
voltage, V
, which the Dynamic Input Voltage Control loop will
BUS
BUSLIM
regulate to in a charging scenario where a current−limited weak adapter is connected to
VBUS.
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
V
(V)
BUSLIM
4.240
4.320
4.400
4.480
4.560
4.640
4.720
4.800
7.632
7.776
7.920
8.064
8.208
8.352
8.496
8.640
3:0
VBUSLIM
0100
R/W
www.onsemi.com
53
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
IIN Register Address: 16h Default Value = 0001 1011
Bit
Name
Value
Type
Description
7
Reserved
0
R
This sets the maximum input current limit from the VIN input.
Programmable from 325 mA to 2 A in 25 mA steps. Default is 1 A.
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
I
(A)
Hex
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
I
(A)
Hex
3A
3B
3C
3D
3E
3F
40
I
(A)
INLIM
INLIM
INLIM
0.325
0.350
0.375
0.400
0.425
0.450
0.475
0.500
0.525
0.550
0.575
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
41
42
43
6:0
IINLIM
0011011
R/W
Bits 44h − 7Fh = 2.000 A
www.onsemi.com
54
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
VIN Register Address: 17h Default Value = 0001 0100
Bit
Name
Value
Type
Description
7:6
Reserved
00
R
This sets the V
threshold.
IN_OVP
Binary
00
V
(V)
IN_OVP
6.5
5:4
VINOVP
01
R/W
01
10.5
13.7
Reserved
10
11
This sets the V voltage, V
which the Dynamic Input Voltage Control loop will regu-
IN
INLIM,
late to in a charging scenario where a current−limited weak adapter is connected to VIN.
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
V
(V)
INLIM
4.240
4.320
4.400
4.480
4.560
4.640
4.720
4.800
7.632
7.776
7.920
8.064
8.208
8.352
8.496
8.640
3:0
VINLIM
0100
R/W
NTC
Register Address: 18h
Default Value = 0000 1111
Bit
Name
Value
Type
Description
7:6
Reserved
00
R
This controls whether the NTC circuit affects the charge current. Temperature mea-
surements will continue to be updated every 1 second in the NTC1 − 4 monitor bits.
5
TEMPDIS
0
R/W
Binary
NTC Operation
0
1
NTC measurement affects charge parameters
NTC measurement does not affect charge parameters
4
3
2
1
0
NTCOK
NTC4
NTC3
NTC2
NTC1
0
1
1
1
1
R
R
R
R
R
“0” if NTC is either shorted to ground, open or shorted to REF.
A “1” indicates that NTC is above the T4 threshold. (Note 14)
A “1” indicates that NTC is above the T3 threshold. (Note 14)
A “1” indicates that NTC is above the T2 threshold. (Note 14)
A “1” indicates that NTC is above the T1 threshold. (Note 14)
www.onsemi.com
55
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
TIMER Register Address: 19h Default Value = 0001 1011
Name
Bit
Value
Type
Description
Writing a “1” resets the Watch Dog Timer; writing a “0” has no effect.
Reading this bit always returns “0”.
7
TMRRST
0
W
6
5
WDEN
0
0
R/W
R
Writing a “1” enables the Watchdog timer (t ) and disables the Safety timer.
WD
Reserved
These bits set the Pre−Charge safety timer.
SETTMR0 (REG 1Fh[0] must be set to “1” immediately after the Pre−Charge timer value
is changed to restart the timer in the programmed configuration.
Binary
00
Pre−Charge Safety Timer
Follows FCTMR (REG 19h[2:0]) programming
100 seconds
4:3
PRETMR
11
R/W
01
10
11
15 minutes
36 minutes
This sets the Fast Charge safety timer.
Binary
000
001
010
011
Fast Charge Safety Timer (Hours)
Never Expires
4
6
2:0
FCTMR
011
R/W
8
100
101
110
10
12
14
16
111
SAFETY
Register Address: 1Ah
Default Value = 1111 1111
Bit
Name
Value
Type
Description
These bits set the maximum programmable FLOAT (REG 11h[7:0]) value.
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
V
Max. (Hex)
V
Max. (V)
FLOAT
FLOAT
00
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.40
4.50
4.60
4.70
4.72
0A
14
1E
28
32
3C
46
50
5A
64
6E
78
82
8C
8E − FF
7:4
VSAFE
1111
R/W
These bits set the maximum programmable IOCHRG (REG 12h[5:0]) value.
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
I
Max. (Hex)
I
Max. (A)
OCHRG
OCHRG
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
3.20
3:0
ISAFE
1111
R/W
www.onsemi.com
56
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
TOPOFF Register Address: 1Bh Default Value = 0000 0011
Name
Bit
7:4
3
Value
0000
0
Type
R
Description
Reserved
TO_BDETDIS
R/W
Setting this bit “1” disables the periodic battery check during top−off charging.
This sets the Top−Off charge timer.
Binary
000
001
010
011
Top Off Timer (min.)
Never Expires
10
20
30
40
50
60
70
2:0
TOTMR
011
R/W
100
101
110
111
BOOST
Register Address: 1Ch
Default Value = 0001 0010
Bit
Name
Value
Type
Description
7
Reserved
0
R
Connects PMID to VBUS when the boost is enabled (BOOSTEN = “1”).
This will reset when BOOSTEN = “0”.
6
OTG
0
R/W
This programs the operation of the switch−mode converter to charge or boost mode. If a
fault occurs during boost mode the BOOSTEN bit and the OTG bit will reset.
5
4
BOOSTEN
Reserved
0
1
R/W
R
BOOSTEN
0
1
Switch−Mode Converter
Charge Mode
Boost Mode
This sets the boost converter output voltage, V
.
BOOST
Programmable from 4.947 V to 5.347 V in 26.67 mV steps. Default is 5.00 V.
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
V
(V)
BOOST
4.947
4.973
5.000
5.027
5.053
5.080
5.107
5.133
5.160
5.187
5.213
5.240
5.267
5.293
5.320
5.347
3:0
VBOOST
0010
R/W
DPLUS
Register Address: 1Fh
Default Value = 0000 0000
Bit
7
Name
Value
0
Type
R/W
R
Description
FORCEDET
Reserved
Setting this bit to “1” forces a BC1.2 detection on D+ and D−.
6:1
000000
While operating on the Safety Timer a “1” restarts the timer. During Pre−Charge,
SETTMR0 must be set to “1” immediately after the Pre−Charge timer (PRETMR (REG
19h [4:3]) value is changed in order to restart the timer in the programmed configuration.
Reading this bit always returns “0”.
0
SETTMR0
0
W
www.onsemi.com
57
FAN54511
Table 24. I2C REGISTER DESCRIPTIONS (continued)
This table defines the operation of each register bit for all IC versions. Default values are with VBAT = 3.8 V and VBUS = VIN = open.
MONITOR 0
Register Address: 20h
Default Value = 1000 0110
Bit
7
Name
Value
Type
R
Description
> ITERM reference or VBUS/ VIN not present.
BAT
ITERMCMP
VBATCMP
1
0
I
comparator output: “1” when I
TERM
6
R
Output of VBAT comparator: “1” when V
> V
BAT BATMIN.
Output of VLOWV comparator. In Fast Charge mode, a “1” indicates when V
> V
.
BAT
LOWV
5
4
VLOWVCMP
BATSHORT
0
0
R
R
In Pre−Charge mode, a “1” indicates when V
> V
. In Boost mode, a “1” indi-
SYS
BATMIN
cates when V
> VBATLV threshold.
BAT
A “1” indicates that V
> V
BST
in any charge mode or HZ. In Boost mode, a “1” indi-
BAT
SHORT
cates that V
> UVLO
.
SYS
3
2
1
HIVBAT
IBUS#
ICHG#
0
1
1
R
R
R
A “1” indicates that V
≥ V
when charge termination, TE bit is set to “0”.
BAT
FLOAT
A “0” indicates the I
A “0” indicates the I
or I loop is controlling the battery charge current.
IN
BUS
loop is controlling the battery charge current.
OCHRG
A “1” indicates the constant−voltage (CV) loop is controlling the charger and all current
loops have released.
0
CV
0
R
MONITOR 1
Register Address: 21h
Default Value = 1010 0XXX
Bit
7
Name
Reserved
PMIDVBAT
PPON
Value
Type
R
Description
1
0
1
0
6
R
A “1” indicates that V
> V
.
PMID
BAT
5
R
A “1” if charging and V
> V
or if the IC is in Standby or HZ.
BAT
SHORT
4
BUCKON
R
A “1” indicates the buck converter is on.
A “1” indicates that either V or V has risen above V and is currently
SOURCE(RISE)
BUS
IN
above V
.
3
ISRCCMP
0
R
SOURCE(RISE)
A “0” indicates that both V
and V are below V
SOURCE(FALL)
.
BUS
IN
2
1
0
NTCGND
DISPIN
X
X
X
R
R
R
A “1” indicates that the NTC pin was tied to ground at V
_POR.
BUS
A “1” indicates that the DIS pin has been externally driven HIGH.
A “1” indicates that the ILIM pin has been externally driven HIGH.
ILIMPIN
IC_INFO
Register Address: 2Dh
Default Value = 10XX XXXX
Bit
7:6
5:3
2:0
Name
Vendor Code
PN
Value
10
Type
R
Description
Identifies ON Semiconductor as the IC supplier.
Part numbers bits, see the Ordering Info in Table 2.
IC Revision
XXX
XXX
R
REV
R
FEATURE CONTROL
Register Address: 30h
Default Value = 0010 0000
Bit
Name
Value
Type
Description
A “1” will reset all registers except SAFETY and put the charger IC into IDLE State when
the Watch Dog Timer (WDT) expires.
7
WDTEXP
0
R/W
6
5
4
3
2
1
0
Reserved
DIVCON
DISREF
0
1
0
0
0
0
0
R
R/W
R/W
R
A “0” disables Dynamic Input Voltage Control (DIVC).
A “1” will disable the REF output and NTC functionality. JEITA not enforced.
Reserved
Reserved
Reserved
Reserved
R
R
R
14.Without power from VBUS or VIN, the reference will not be powered and the NTC pin will be at ground. See applications section for more
detail.
www.onsemi.com
58
FAN54511
PRODUCT−SPECIFIC DIMENSIONS (MM)
Product
E
D
X
Y
FAN5451xAUCX
3.63 0.03
2.83 0.03
0.195
0.195
www.onsemi.com
59
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP63 3.63x2.83x0.522
CASE 567TM
ISSUE O
DATE 31 MAR 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13339G
WLCSP63 3.63x2.83x0.522
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
ON Semiconductor Website: www.onsemi.com
◊
www.onsemi.com
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明