FAN604HMX [ONSEMI]
Offline Quasi-Resonant PWM Controller;
| 型号： | FAN604HMX |
| 厂家： | 
ONSEMI |
| 描述： | Offline Quasi-Resonant PWM Controller |
| 文件： | 总23页 (文件大小：1366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FAN604H
Offline Quasi-Resonant PWM
Controller
The FAN604H is an advanced PWM controller aimed at achieving power
density of ≥10W/in3 in universal input range AC/DC flyback isolated
power supplies. It incorporates Quasi-Resonant (QR) control with
proprietary Valley Switching with a limited frequency variation. QR
switching provides high efficiency by reducing switching losses while
Valley Switching with a limited frequency variation bounds the frequency
band to overcome the inherent limitation of QR switching.
FAN604H features mWSaver® burst mode operation with extremely low
operating current (300 μA) and significantly reduces standby power
consumption to meet the most stringent efficiency regulations such as
Energy Star’s 5-Star Level and CoC Tier II specifications.
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MARKING DIAGRAM
10
ZXYTT
604H
TM
FAN604H includes several user configurable features aimed at optimizing
efficiency, EMI and protections. FAN604H has a wide blanking
frequency range that improves light load efficiency and eliminating audio
noise for adaptive application. It incorporates user-configurable constant
current reference, which allows controlling the maximum output current
from primary-side, thereby optimizing transformer design to improve the
overall efficiency. It also includes several rich programmable protection
features such as over-voltage protection (OVP), precise constant output
current regulation (CC).
1
Z: Assembly Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: Package Type (M=SOIC)
M: Manufacture Flow Code
PIN CONNECTIONS
Features
Higher Average Efficiency by Quasi-Resonant Switching Operation
with Wide Blanking Time Range
HV
1
2
3
4
5
10 GND
NC
CS
9
8
7
6
FB
Wide Input and Output Conditions Achieve High Power Density
Power Supply
FAN604HMX
SD
Optimization Transformer Design for Adaptive Charger
Application
User Configurable Constant Current Reference (CCR) to Limit
the Maximum Output Current
Precise Constant Output Current Regulation with Programmable
Line Compensation
GATE
VDD
CCR
VS
(Top View)
ORDERING INFORMATION
mWSaver® Technology for Ultra Low Standby Power Consumption
(<20 mW)
See detailed ordering and shipping information in the
package dimensions section on page 20 of this data sheet.
Forced and Inherent Frequency Modulation of Valley Switching for
Low EMI Emissions and Common Mode Noise
Built-In and User Configurable Over-Voltage Protection (OVP),
Under-Voltage Protection (UVP) and Over-Temperature Protection
(OTP)
Programmable Over-Temperature-Protection through External NTC
Resistor
Fully Programmable Brown-In and Brownout Protection
Built-In High-Voltage Startup to Reduce External Components
Typical Applications
Battery Charges for Smart Phones, Feature Phones, and Tablet PCs
AC-DC Adapters for Portable Devices or Battery Chargers that
Require CV/CC Control
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
May 2017- Rev. 1
FAN604H
FAN604H
RSNS CSNP
TX
LF
DR
CO
Np
Ns
VO
CSNP
RSNP
Fuse
XC
Choke
RHV1
CBLK1
CBLK2
Bridge
AC IN
DSNP
RBias1
Photo
RBias2
RHV2
CComp2
coupler
RF1
RGR
HV
GATE
R
Comp CComp1
Shunt
FB
Regulator
RGF DG
FAN604H
SD
CS
VDD
VS
RF2
Na
RCS_COMP
CCSF
CCR
RCS
Photo
coupler
CFB
GND
NTC
RSD
DAUX
RCCR
CCCR
RVS1
CVDD
RVS2
CVS
Figure 1 FAN604H Typical Application
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2
FAN604H
HV
1
HV
Start-up
Burst/Green
Mode
HV
VFB
Brown IN
VDD UVLO
VDD UVLO
17.2V/5.5V
VDD UVLO
VNVS
Brown OUT
VDD OVP Fault
VS UVP Fault
VS OVP Fault
Auto-Restart
Protection
OTP Fault
VCS Fault
SD Fault
VDD
5
Debounce
VDD OVP Fault
VVDD-OVP
GND 10
VS OVP Fault
VS UVP Fault
VS_SH
S/H
VS Protection
VDD
Maximum
On Time
S/H = Sampling and Hold
Driver
Control
4
GATE
D
Q
Q
VD
Forced Frequency
Modulation
OSC
CLK
6
VS
SD
Valley
Detection
VFB
C
VNVS
tDIS
5V
ISD
VCS-LIM
CS
5V
5V
8
VCS Fault
Protection
SD Fault
VSD-TH
ICOMP
VCS
3
7
CS
LEB
5.25V
ZFB
VCS
Peak Current
VCS
tDIS
AV-CC
IO Estimator
ICCR
9
AV
FB
VCCR
CCR
Figure 2 FAN604H Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
High Voltage. This pin connects to DC bus for high-voltage startup.
No Connect.
1
2
HV
NC
Current Sense. This pin connects to a current-sense resistor to sense the MOSFET current for Peak-Current-Mode
control for output regulation. The current sense information is also used to estimate the output current for CC
regulation.
3
CS
PWM Signal Output. This pin has an internal totem-pole output driver to drive the power MOSFET. The gate
driving voltage is internally clamped at 14.5V.
4
5
GATE
VDD
Power Supply. IC operating current and MOSFET driving current are supplied through this pin. This pin is typically
connected to an external VDD capacitor.
Voltage Sense. The VS voltage is used to detect resonant valleys for quasi-resonant switching. This pin detects
the output voltage information and diode current discharge time based on the auxiliary winding voltage. It also
senses input voltage for Brown-out protection.
6
VS
Constant Current Reference. This pin connects to external resistor to program the reference voltage of constant
output current.
7
8
CCR
SD
Shut Down. This pin is implemented for external over-temperature-protect by connecting NTC thermistor.
Feedback. Typically Opto-Coupler is connected to this pin to provide feedback information to the internal PWM
comparator. This feedback is used to control the duty cycle in CV regulation.
9
FB
10
GND
Ground.
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3
FAN604H
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Maximum Voltage on HV Pin
DC Supply Voltage
VHV
500
V
VVDD
VGETE
Vmax
PD
30
V
V
Maximum Voltage on GATE Pin
-0.3 to 30
-0.3 to 6
850
Maximum Voltage on Low Power Pins (Except Pin 1, Pin 4, Pin 5)
Power Dissipation (TA=25C)
V
mW
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Top)
Operating Junction Temperature
θJA
ΨJT
TJ
140
13
C/W
C/W
C
-40 to +150
-40 to +150
Storage Temperature Range
TSTG
C
Human Body Model, JEDEC:JESD22_A114
(Except HV Pin)
Charged Device Model, JEDEC:JESD22_C101
(Except HV Pin)
2.0
ESD
kV
0.75
1. All voltage values, except differential voltages, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD ratings including HV pin: HBM=2.0 kV, CDM=0.75kV.
RECOMMENDED OPERATING RANGES
Rating
Symbol
Min
Max
Unit
HV Pin Supply Voltage
VHV
50
400
V
VDD Pin Supply Voltage
VS Pin Supply Voltage
CS Pin Supply Voltage
FB Pin Supply Voltage
CCR Pin Supply Voltage
SD Pin Supply Voltage
Operating Temperature
VVDD
VVS
VCS
VFB
VCCR
VSD
TA
6
0.4
0
25
3.0
0.9
5.25
1.7
5
V
V
V
0
V
0.2
0
V
V
-40
+85
C
4. The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions
are specified to ensure optimal performance. ON does not recommend exceeding them or designing to Absolute Maximum Ratings.
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4
FAN604H
ELECTRICAL CHARACTERISTICS
For typical values TJ = 25°C, for min/max values TJ = -40°C to 125°C, VDD = 15 V; unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
HV Section
Supply Current Drawn from HV Pin
Leakage Current Drawn from HV Pin
Brown-In Threshold Voltage
VDD Section
VHV=120 V, VDD=0 V
IHV
1.2
0
2.0
0.8
110
10
10
mA
μA
V
VHV=500 V, VDD=VDD-OFF+1 V
IHV-LC
RHV=150kΩ, VIN =80VAC
VBrown-IN
100
120
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Threshold Voltage for HV Startup
Startup Current
VDD Rising
VDD-ON
VDD-OFF
VDD-HV-ON
IDD-ST
15.3
5.0
4.1
-
17.2
5.5
18.7
5.7
V
V
VDD Falling
4.7
5.4
V
TJ = 25C
VDD=VDD-ON-0.16 V
300
450
μA
VCS=5.0 V, VVS=3 V, VFB=3 V
CGATE=1nF
Operating Supply Current
IDD-OP
-
-
2
3
mA
VCS=0.3 V, VVS=0 V, VFB=0 V;
VDD=VDD-ONVDD-OVP10 V,
CGATE=1nF
Burst-Mode Operating Supply Current
IDD-Burst
300
600
μA
VDD Over-Voltage-Protection Level
VDD Over-Voltage-Protection Debounce Time
Oscillator Section
VVDD-OVP
tD-VDDOVP
27.5
-
29.0
70
29.5
105
V
TJ = 25C
μs
Maximum Blanking Frequency
Minimum Blanking Frequency
Minimum Frequency
VFB > VFB-BNK-H
VFB < VFB-BNK-L
VVS = 1V
fBNK-MAX
fBNK-MIN
fOSC-MIN
125
16.5
15
130
18.5
17
135
20.5
19
kHz
kHz
kHz
Forced Frequency Modulation Range
ΔtFM-Range
ΔtFM-Period
210
2.1
265
2.5
310
2.9
ns
VFB> VFB-Burst--H
Forced Frequency Modulation Period
Feedback Input Section
ms
FB Pin Input Impedance
ZFB
39
42
45
kΩ
V/V
V
Internal Voltage Attenuator of FB Pin (Note 5)
FB Pin Pull-Up Voltage
AV
1/3
1/3.5
5.25
2.25
1.25
0.75
0.70
1/4
FB Pin Open
TJ = 25C
TJ = 25C
VFB Rising
VFB Falling
VFB-Open
VFB-BNK-H
VFB-BNK-L
VFB-Burst-H
VFB-Burst-L
4.55
2.10
1.10
0.65
0.60
5.90
2.40
1.40
0.85
0.80
V
Frequency Foldback Starting/Stopping VFB
V
V
FB Threshold to Enable/Disable Gate Drive in
Burst Mode
V
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5
FAN604H
ELECTRICAL CHARACTERISTICS (CONTINUED)
For typical values TJ = 25°C, for min/max values TJ = -40°C to 125°C, VDD = 15 V; unless otherwise noted.
Parameter
Voltage-Sense Section
Test Conditions
Symbol
Min
Typ
Max
Unit
Maximum VS Source Current Capability
IVS-MAX
-
-
3
mA
VS Sampling Blanking Time 1 after GATE Pin
Pull-Low
VFB Falling and VFB < 2.0V
VFB Rising and VFB > 2.2V
VVS=0V, CGATE=1nF
tVS-BNK1
0.84
1.0
1.23
μs
VS Sampling Blanking Time 2 after GATE Pin
Pull-Low
tVS-BNK2
1.45
1.8
2.15
μs
Delay from VS Voltage Zero Crossing to PWM
ON (Note 5)
tZCD-to PWM
175
ns
VS Source Current Threshold to Enable
Brown-out
IVS-Brown-Out
tD-Brown-Out
VVS-OVP
360
12.5
2.9
450
16.5
3.0
530
21
μA
ms
V
Brown-Out Debounce Time
Output Over-Voltage-Protection with Vs
Sampling Voltage
3.1
Output Over-Voltage-Protection Debounce Pulse
Counts
NVS-OVP
VVS-UVP
-
2
0.400
2
-
Pulse
V
Output Under-Voltage-Protection with Vs
Sampling Voltage
0.375
0.425
TJ = 25C
Output Over-Voltage-Protection Debounce Pulse
Counts
NVS-UVP
-
25
-
-
55
-
Pulse
ms
Output Under-Voltage Protection Blanking Time
at start-up
tVS-UVP-BLANK
NVDD-Hiccup
40
Auto-Restart Cycle Counts when Extend Auto-
Restart Mode is triggered
VVS < VVS-UVP
2
Cycle
Over-Temperature Protection Section
Threshold Temperature for Over-Temperature-Protection (Note 5)
TOTP
-
140
-
C
Current-Sense Section
Current Limit Threshold Voltage
FB Pin Open
VCS-LIM
VCS-IMIN-H
VCS-IMIN-M
VCS-IMIN-L
tPD
0.865
0.39
0.30
0.21
-
0.890
0.44
0.35
0.25
50
0.915
0.51
0.40
0.29
100
V
V
High Threshold Voltage of Current Sense
Middle Threshold Voltage of Current Sense
Low Threshold Voltage of Current Sense
GATE Output Turn-Off Delay (Note 5)
Leading-Edge Blanking Time (Note 5)
VFB > VFB-BNK-L
V
VFB = 1V, TJ = 25C
VFB < VFB-Burst-H, TJ = 25C
V
ns
ns
tLEB
-
250
350
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6
FAN604H
ELECTRICAL CHARACTERISTICS (CONTINUED)
For typical values TJ = 25°C, for min/max values TJ = -40°C to 125°C, VDD = 15 V; unless otherwise noted.
Parameter
Shut-Down Function Section
SD Pin Source Current
Test Conditions
Symbol
Min
Typ
Max
Unit
ISD
90
0.95
200
8.5
103
1.00
400
10
110
1.05
600
11
μA
V
Threshold Voltage for Shut-Down Function
Enable
VSD-TH
tD-SD
Debounce Time for Shut-Down Function
μs
kΩ
Ratio between threshold voltage and source
current
ZSD-TH
Hysteresis of Threshold Voltage for Shut-
Down Function Enable
VSD-TH-ST
tSD-ST
1.30
0.4
1.35
1.0
1.40
1.6
V
Duration of VSD-TH-ST at startup
Constant Current Correction Section
High Line Compensation Current
Low Line Compensation Current
Constant Current Estimator Section
CCR Pin Source Current
ms
VIN = 264 Vrms
ICOMP-H
ICOMP-L
90
32
100
36
110
40
μA
μA
VIN = 90 Vrms
ICCR
18.2
20
21.8
μA
Constant Current Control Reference Offset
Voltage (Note 5)
VREF_CC_Offset
0.8
V
Peak Value Amplifying Gain (Note 5)
FB CC Pull-Up Voltage CC (Note 5)
Internal Voltage Attenuator of FB CC (Note 5)
GATE Section
APK
VFB-CC-Open
AV-CC
3.6
4.0
V/V
V
0.444
V/V
Gate Output Voltage Low
VGATE-L
VDD-PMOS-ON
VDD-PMOS-OFF
tr
0
-
1.5
8.0
V
V
Internal Gate PMOS Driver ON
Internal Gate PMOS Driver OFF
Rising Time
VDD Falling
7.0
9.0
70
7.5
9.5
110
VDD Rising
10.0
150
V
VCS=0 V, VS=0 V, CGATE=1nF
ns
VCS=0 V, VS=0 V, CGATE=1nF
Falling Time
tf
30
50
70
ns
TJ = 25C
Gate Output Clamping Voltage
VDD=25 V
VGATE-CLAMP
tON-MAX
13.6
20
14.5
22
15.0
25
V
Maximum On Time
VFB=3V, VCS=0.3V
μs
5. Design guaranteed.
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7
FAN604H
TYPICAL CHARACTERISTICS
1.1
1.05
1
1.1
1.05
1
0.95
0.9
0.95
0.9
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
Temperature ( C)
Temperature ( C)
Figure 4 Turn-Off Threshold Voltage
(VDD-OFF) vs. Temperature
Figure 3 Turn-On Threshold Voltage
(VDD-ON) vs. Temperature
1.1
1.05
1
1.1
1.05
1
0.95
0.95
0.9
0.9
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
Temperature ( C)
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
Temperature ( C)
Figure 5 VDD Over Voltage-Protection Level
(VVDD-OVP) vs. Temperature
Figure 6 Brown-In Threshold Voltage
(VBrown-IN) vs. Temperature
1.1
1.1
1.05
1
1.05
1
0.95
0.95
0.9
0.9
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
Temperature ( C)
Temperature ( C)
Figure 8 Minimum Blanking Frequency
(fBNK-MIN) vs. Temperature
Figure 7 Maximum Blanking Frequency
(fBNK-MAX) vs. Temperature
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8
FAN604H
1.1
1.05
1
1.1
1.05
1
0.95
0.95
0.9
0.9
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
Temperature ( C)
Temperature ( C)
Figure 9 Frequency Foldback Starting VFB
(VFB-BNK-H) vs. Temperature
Figure 10 Frequency Foldback Stopping VFB
(VFB-BNK-L) vs. Temperature
1.1
1.1
1.05
1
1.05
1
0.95
0.95
0.9
0.9
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
Temperature ( C)
Temperature ( C)
Figure 11 VS Sampling Blanking Time 1
(tVS-BNK1) vs. Temperature
Figure 12 VS Sampling Blanking Time 2
(tVS-BNK2) vs. Temperature
1.1
1.05
1
1.1
1.05
1
0.95
0.95
0.9
0.9
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
Temperature ( C)
Temperature ( C)
Figure 14 Output Under-Voltage Protection
(VVS-UVP) vs. Temperature
Figure 13 Output Over-Voltage-Protection
(VVS-OVP) vs. Temperature
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9
FAN604H
1.1
1.05
1
1.1
1.05
1
0.95
0.95
0.9
0.9
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
Temperature ( C)
Temperature ( C)
Figure 15 Current Limit Threshold Voltage
(VCS-LIM) vs. Temperature
Figure 16 High Threshold Voltage of Current Sense
(VCS-IMIN-H) vs. Temperature
1.1
1.1
1.05
1
1.05
1
0.95
0.95
0.9
0.9
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
Temperature ( C)
Temperature ( C)
Figure 17 Ratio between Threshold Voltage
and Source Current (ZSD-TH) vs. Temperature
Figure 18 During of VSD-TH-ST at startup
(tSD-ST) vs. Temperature
1.1
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
-40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃
Temperature ( C)
Temperature ( C)
Figure 19 CCR Pin Source Current
(ICCR) vs. Temperature
Figure 20 Maximum On Time
(tON-MAX) vs. Temperature
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10
FAN604H
APPLICATIONS INFORMATION
FAN604H is an offline PWM controller which operates
in quasi-resonant (QR) mode and significantly
upper limit of the blanking frequency varies from fBNK-
as load decreases where the blanking frequency
a
MAX
enhances system efficiency and power density. Its control
method is based on the load condition (valley switching
with fixed blanking time at heavy load and valley
switching with variable blanking time at medium load) to
maximize the efficiency. It offers constant output voltage
(CV) regulation through opto-coupler feedback circuitry.
Line voltage compensation gain can be programmed by
using an external resistor to minimize the effect of line
voltage variation on output current regulation due to turn-
off delay of the gate drive circuit.
FAN604H incorporates HV startup and accurate brown-
in through HV pin. The brown-in voltage is programmed
by using an external HV pin resistor. The constant
current regulation (CCR), which sets the maximum
output current level, is programmable via an external
resistor connected to the CCR pin.
reduction stop point is fBNK-MIN. For the light load
condition (5%~25%)), the blanking time for the valley
detection is fixed such that the switching time is between
fBNK-MIN and fBNK-MIN + tresonance and primary side peak
current will be modulated by the function of VCS-IMN
modulation, as shown in Figure 22
Burst Mode Operation
Figure 21 shows when VFB drops below VFB-Burst-L, the
PWM output shuts off and the output voltage drops at a
rate which is depended on the load current level. This
causes the feedback voltage to rise. Once VFB exceeds
VFB-Burst-H, FAN604H resumes switching. When the FB
voltage drops below the corresponding VCS-IMIN-L, the
peak currents in switching cycles are limited by VCS-IMIN-
L regardless of FB voltage. Thus, more power is delivered
to the load than required and once FB voltage is pulled
low below VFB-Burst-L, switching stops again. In this
manner, the burst mode operation alternately enables and
disables switching of the MOSFET to reduce the
switching losses.
Protections such as VDD Over-Voltage Protection (VDD
OVP), VS Over-Voltage Protection (VS OVP), VS Under-
Voltage Protection (VS UVP), internal Over-Temperature
Protection (OTP), Brownout protection and externally
triggered shut-down (SD) function improve reliability.
Output Voltage
Basic Operation Principle
Quasi-resonant switching is a method to reduce primary
MOSFET switching losses low line is more effective. In
order to perform QR turn-on of the primary MOSFET,
the valley of the resonance occurring between
transformer magnetizing inductance (Lm) and MOSFET
effective output capacitance (Coss-eff) must be detected.
VCS-IMIN-L
VFB-Burst-H
VFB-Burst-L
VFB
COSS-eff COSSMOSFET Ctrans Cparasitic
(eq. 1)
Figure 21 Burst-Mode Operation
tresonance 2 Lm COSSeff
(eq. 2)
Deep Burst Mode
For heavy load condition (50%~100% of full load), the
blanking time for the valley detection is fixed such that
the switching time is between 1/fBNK-MAX and 1/fBNK-MAX
+ tresonance and primary side peak current will be
modulated by voltage level of feedback. For the medium
load condition (25%~50% of full load), the blanking time
is modulated as a function of load current such that the
FAN604H enters deep burst mode if FB voltage stays
lower than VFB-Burst-L for more than tDeep-Burst-Entry (640 µs).
Once FAN604H enters deep burst mode, the operating
current is reduced to IDD-Burst (300 μA) to minimize power
consumption. Once feedback voltage is more than VFB-
Burst-H, power-on-reset occurs within a time period of tDeep-
(25 μs) and IC resumes switching with normal
Burst-Exit
operating current, IDD-OP
.
VFB
IPK
fBNK-MIN = 1/tBNK-MAX
tEXT
tBNK
fBNK-MAX =1/ tBNK-MIN
tEXT
tBNK
tBNK
tEXT
VDS
Fixed Blanking Time
Modulated Blanking Time
Fixed Blanking Time
Figure 22 Frequency Fold-back Function
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11
FAN604H
Valley Detection
Inherent and Forced Frequency Modulation
There will be a logic propagation delay from VS Zero-
Crossing Detection (VS-ZCD) to IC GATE turn on and a
MOSFET gate drives propagation delay from GATE pin
to MOSFET turn on. We can assume the sum of these
propagation delays to be tZCD-to-PWM (175ns), as shown in
Typically, the bulk capacitor of flyback converter has a
longer charging time in low line than in high line. Thus,
the voltage ripple (∆ VDC) in low line is higher as shown
in Figure 24. This large ripple results in 4~6% variation
of the switching frequency in low line for a valley
switched converter, the switching frequency could vary
accordingly. This frequency variation scatters EMI noise
nearby frequency band, this is helpful to meet EMI
requirement easily. Hence, the EMI performance in low
line is satisfied. However, in high line, the ripple is very
small and consequently the EMI performance for high
line may suffer. In order to maintain good EMI
performance for high line, forced frequency modulation
is provided. FAN604H varies the valley switching point
from 0 to ΔtFM-Range (265 ns) in every ΔtFM-Period (2.5 ms)
as shown in Figure 25. Since the drain voltage at which
the switching occurs does not change much with this
variation, there is minimum impact on the efficiency.
Figure 23. However, if 1/2 tF is longer than tZCD-to-PWM
,
the switching occurs away from the valley causing higher
losses. The time period of resonant ringing is dependent
on Lm and Coss-eff. Typically, the time period of resonance
ringing is around 1~1.5 μs depending on the system
parameters. Hence, the switching may occur at a point
different from the valley depending on the system. When
PCB layout is poor, it may cause noise on the VS pin.
The VS pin needs to be in parallel with the capacitor (CVS)
less than 10 pF to filter the noise.
VAux
VS
VAUX
VS Zero-Crossing Detect
0V
RVS1
NA
Zero-Crossing
Detection
VD
VS
tZCD-to-PWM
tD
tON
RVS2
CVS
tF/2
tF
GATE
CVS < 10pF
Figure 23 The Valley Detection Circuit and Behaior
VDC
LF
VDC
Bridge
Diode
AC IN
CBLK1 CBLK2
Figure 24 Inherent Frequency Modulation
VDS
½ tresonance
nVO
IPK VDS
265ns
VDC
Figure 25 Forced Frequency Modulation
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12
FAN604H
Output Voltage Detection
VBLK NA
RVS1 NP
IVS
(eq. 4)
Figure 26 shows the VS voltage is sampled (VS-SH) after
tVS-BNK of GATE turn-off so that the ringing does not
introduce any error in the sampling. FAN604H
dynamically varies tVS-BNK with load. At heavy load, tVS-
BNK=tVS-BNK1 (1.8 µs) when VFB > VFB-BNK-H. At light-load,
tVS-BNK=tVS-BNK2 (1.0 µs) when VFB < VFB-BNK-L. This
dynamic variation ensures that VS sampling occurs after
ringing due to leakage inductance has stopped and before
secondary current goes to zero.
The IVS current, reflecting the line voltage information, is
used for brownout protection and CC control correction
weighting.
CV / CC PWM Operation Principle
Figure 27 shows a simplified CV / CC PWM control
circuit of the FAN604H. The Constant Voltage (CV)
regulation is implemented in the same manner as the
conventional isolated power supply, where the output
voltage is sensed using a voltage divider and compared
with the internal reference of the shunt regulator to
generate a compensation signal. The compensation signal
is transferred to the primary side through an opto-coupler
and scaled down by attenuator AV to generate a COMV
signal. This COMV signal is applied to the PWM
comparator to determine the duty cycle.
NA
RVS 2
VS-SH VO
(eq. 3)
NS RVS1 RVS 2
GATE
tVS-BNK
VS-SH
The Constant Current (CC) regulation is implemented
internally with primary-side control. The output current
estimator calculates the output current using the
transformer primary-side current and diode current
discharge time. By comparing the estimated output
current with internal reference signal, a COMI signal is
generated to determine the duty cycle.
These two control signals, COMV and COMI, are
compared with an internal sawtooth waveform (VSAW) by
two PWM comparators to determine the duty cycle.
Figure 27 illustrates the outputs of two comparators,
combined with an OR gate, to determine the MOSFET
turn-off instant. Either of COMV or COMI, the lower
signal determines the duty cycle. During CV regulation,
COMV determines the duty cycle while COMI is
saturated to HIGH level. During CC regulation, COMI
determines the duty cycle while COMV is saturated to
HIGH level.
VS
Figure 26 Output Voltage Detection
Line Voltage Detection
The FAN604H indirectly senses the line voltage through
the VS pin while the MOSFET is turned on, as illustrated
in Figure 27 MOSFET turn-on period, the auxiliary
winding voltage, VAUX, is proportional to the input bulk
capacitor voltage, VBLK, due to the transformer coupling
between the primary and auxiliary windings. During the
MOSFET conduction time, the line voltage detector
clamps the VS pin voltage to VS-Clamp (0 V), and then the
current IVS flowing out of VS pin is expressed as:
VBLK
CC
CV
Vo
NP
NS
ON TRIG
COMI
GATE
4
OSC
PWM Control Logic
Block
OFF TRIG
COMV
CS
ZCOMP
VSAW
5V
COMV
GATE
VAUX
VSAW
AV
FB
0.8V
VAUX
RVS1 NA
IVS
CCR
COMI
0V
Line Voltage
Detector
Z
Line
signal
-VAUX = VBLK (NA/NP)
IO
Estimator
RVS2
Zero Current Detector
VS
VS
VS-Clamp
Figure 27 Simplified PWM Control Circuit and PWM Operation for CV/CC Regulation
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13
FAN604H
Primary-Side Constant Current Operation
Line Voltage Compensation
Figure 28 shows the key waveforms of a flyback
converter operation in DCM. The output current is
estimated by calculating the average of output diode
current in one switching cycle:
The output current estimation is also affected by the turn-
off delay of the MOSFET as illustrated in Figure 29. The
actual MOSFET’s turn-off time is delayed due to the
MOSFET gate charge and gate driver’s capability,
resulting in peak current detection error as
VREF _ CC
VCSPK Tdis NP
NP
1 1
1 1
IO
Eff
Eff
(eq. 5)
VBLK
2 RCS
TS
NS
2 RCS APK NS
PK
DS
I
tOFF.DLY
(eq. 7)
Lm
When the diode current reaches zero, the transformer
winding voltage begins to drop sharply and VS pin
voltage drops as well. When VS pin voltage drops below
the VS-SH by more than 500 mV, zero current detection of
diode current is obtained. The output current can be
programmed by setting the resistor as of CCR:
Where Lm is the transformer’s primary side magnetizing
inductance. Since the output current error is proportional
to the line voltage, the FAN604H incorporates line
voltage compensation to improve output current
estimation accuracy. Line information is obtained
through the line voltage detector as shown in Figure 27.
ICOMP is an internal current source, which is proportional
to line voltage. The line compensation gain is
NS
1
1
RCCR
(2 IO RCS APK
VREF _ CC _ Offset )
(eq. 6)
ICCR
NP Eff
When PCB layout is poor, it may cause noise on the CCR
pin. The CCR pin needs to be in parallel with the
capacitor (CCCR) less than 4.7nF stabilizing the voltage
against noise.
programmed by using CS pin series resistor, RCS_COMP
,
depending on the MOSFET turn-off delay, tOFF.DLY. ICOMP
creates a voltage drop, VOFFSET, across RCS_COMP. This
line compensation offset is proportional to the DC link
capacitor voltage, VBLK, and turn-off delay, tOFF.DLY
.
Figure 29 demonstrates the effect of the line
compensation.
TS
TON
Tdis
TQR
VBLK
Gate
Vo
NP
NS
OSC
ON TRIG
GATE
VCS-PK
Idiode
PWM Control
Logic Block
4
ICCR
VREF_CC
RCS_COMP
OFF TRIG
CS
ZCOMP
VS-SH
VS-SH
VCCR
RCS
500mV
500mV
1.8µs
CCR
1.8µs
COMI
CCCR
Z
RCCR
VCS-PK
S/H
VS
CCCR : 1nF ~ 4.7nF
VAUX
IO
APK
Estimator
Zero Current Detect
RVS1 NA
APKVCS-PK
Tdis
Zero Current
Detector
RVS2
VS
VREF_CC
IO_ESTM
Figure 28 Waveforms for Estimate Output Current
ICOMP
VGS
IDS
CS
tOFF.DLY
+
VOFFSET
-
IDSRCS
RCS_COMP
RCS
IDSRCS
IDSRCS
VCS
CCSF
PK
IDS
R
CS
CCSF < 20pF
IDS-SHRCS
IDSRCS
IDSRCS
Actual diode current
Estimated diode current
IDSRCS
IDSRCS
IDSPKNP/NS
IDS-SHNP/NS
tOFF.DLY
tOFF.DLY
Tdis
GATE
VGS
VCS
VCS
VOFFSET-H
VOFFSET-L
VGS
VGS
Low Line
High Line
Figure 29 Effect of MOSFET Turn-off Delay and Line Voltage Compensation
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14
FAN604H
CCM Prevention
Once switching starts, the internal HV startup circuit is
disabled. During normal switching, the line voltage
information is obtained from the IVS signal. Once the HV
startup circuit is disabled, the energy stored in CVDD
supplies the IC operating current until the transformer
auxiliary winding voltage reaches the nominal value.
Therefore, CVDD should be properly designed to prevent
VDD from dropping below VDD-OFF threshold (typically
5.5 V) before the auxiliary winding builds up enough
voltage to supply VDD. During startup, the IC current is
limited to IDD-ST (300 μA).
The constant current calculation logic is based on flyback
converter operation in DCM. The output current is
estimated by calculating the average of output diode
current in one switching cycle. If flyback converter goes
into CCM operation, the discharge time of magnetizing
current will be fixed. Once this discharge time is fixed, it
will increase the average of output diode current.
During the CC region, when output voltage becomes
lower, the time that the magnetizing current decreases
down to zero is longer, as shown in Figure 30. FAN604H
provides the lower operation frequency that can be down
to 17 kHz (fOSC-MIN) to prevent the system goes into CCM
operation.
RHV
HV
8
ILm
RJFET=6.4kΩ
S1
5
+
VDD
Good
VDD
-
S2
CX2
CX1
CV-CC Curve
tD
CDD
VDD.ON/ VDD.OFF
VO
tON
CV Region
tD
tD
VDD=VDD-ON(17.2V)
RLS=1.2kΩ
nVO
nVO
nVO
VIN
+
AC Line
CC Region
UVP
Brown IN
Vref = 0.845V
-
IO
VDS
Figure 31 HV Startup Circuit
IHV
fOSC-MIN
Figure 30 The Minimum Operation Frequency
10mA
HV Startup and Brown-In
Figure 31 shows the high-voltage (HV) startup circuit.
An Internal JFET provides a high voltage current source,
whose characteristics are shown in Figure 32. To
improve reliability and surge immunity, it is typical to
use a RHV resistor between the HV pin and the bulk
capacitor voltage. The actual current flowing into the HV
pin at a given bulk capacitor voltage and startup resistor
value is determined by the intersection point of
characteristics I-V line and the load line as shown in
Figure 32.
During startup, the internal startup circuit is enabled and
the bulk capacitor voltage supplies the current, IHV, to
charge the hold-up capacitor, CVDD, through RHV. When
the VDD voltage reaches VDD-ON, the sampling circuit
shown in Figure 31 is turned on for tHV-det (100 µs) to
sample the bulk capacitor voltage. Voltage across RLS is
compared with reference which generates a signal to start
switching. If brown-in condition is not detected within
this time, switching does not start. Equation 8 can be
used to program the brown-in of the system. If line
voltage is lower than the programmed brown-in voltage,
FAN604H goes in auto-restart mode.
VBLK
RHV
2mA
1.2mA
100V
200V
300V
400V
500V
VHV
VBLK
Figure 32 Characteristics of HV pin
RLS RJEFT RHV
VIN
VREF
(eq. 8)
RLS
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15
FAN604H
Power On
Protections
VDS
The FAN604H protection functions include VDD Over-
Voltage Protection (VDD-OVP), brownout protection,
VS Over-Voltage Protection (VS-OVP), VS Under-
Voltage Protection (VS-UVP), and IC internal Over-
Temperature Protection (OTP). The VDD-OVP,
brownout protection, VS-OVP and OTP are implemented
with Auto-Restart mode. The VS-UVP is implemented
with Extend Auto-Restart mode.
VDD
Vs UVP
Occurs
Extend Auto-Restart
VDD-ON
When the Auto-Restart Mode protection is triggered,
switching is terminated and the MOSFET remains off,
causing VDD to drop because of IC operating current
IDD-OP (2 mA). When VDD drops to the VDD turn-off
voltage of VDD-OFF (5.5 V), operation current reduces to
IDD-Burst (300 µA). When the VDD voltage drops further
to VDD-HV-ON, the protection is reset and the supply
current drawn from HV pin begins to charge the VDD
hold-up capacitor. When VDD reaches the turn-on
voltage of VDD-ON (17.2 V), the FAN604H resumes
normal operation. In this manner, the Auto-Restart mode
alternately enables and disables the switching of the
MOSFET until the abnormal condition is eliminated as
shown in Figure 33. When the Extend Auto-Restart Mode
protection is triggered via VS under-voltage protection
(VS-UVP), switching is terminated and the MOSFET
remains off, causing VDD to drop. While VDD drops to
VDD-HV-ON for HV startup circuit enable, then IC enters
Extend Auto-Restart period with two cycles as shown
Figure 34. During Extend Auto-Restart period, VDD
voltage swings between VDD-ON and VDD-HVON without
gate switching, and IC operation current is reduced to
IDD-Burst of 300 μA for slowing down the VDD capacitor
discharging slope. As Extend Auto-Restart period ends,
normal operation resumes.
VDD-OFF
VDD-HV-ON
Operating Current
IDD-OP
IDD-Brust
Figure 34 Extend Auto-Restart Mode Operation
VDD Over-Voltage-Protection (VDD-OVP)
VDD over-voltage protection prevents IC damage from
over-voltage stress. It is operated in Auto-Restart mode.
When the VDD voltage exceeds VDD-OVP (29.0 V) for the
de-bounce time, tD-VDDOVP (70 μs), due to abnormal
condition, the protection is triggered. This protection is
typically caused by an open circuit of secondary side
feedback network.
Brownout Protection
Line voltage information is used for brownout protection.
When the IVS current out of the VS pin during the
MOSFET conduction time is less than 450 μA for longer
than 16.5 ms, the brownout protection is triggered. The
input bulk capacitor voltage to trigger brownout
protection is given as
Power On
VDS
RVS1
VBLK.BO 1.2450A
(eq. 9)
N A
NP
IC Internal Over-Temperature-Protection (OTP)
Fault
Occurs
VDD
VDD-OVP
The internal temperature-sensing circuit disables the
PWM output if the junction temperature exceeds 140°C
(TOTP) and the FAN604H enters Auto-Restart Mode
protection.
Fault
Removed
VDD-ON
VDD-OFF
VDD-HV-ON
Operating Current
IDD-OP
IDD-Brust
Figure 33 Auto-Restart Mode Operation
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16
FAN604H
VS Over-Voltage-Protection (VS-OVP)
VAUX
0.4V
VS over-voltage protection prevents damage caused by
output over-voltage condition. It is operated in Auto-
Restart mode. Figure 35 shows the internal circuit of VS-
OVP protection. When abnormal system conditions
occur, which cause VS sampling voltage to exceed VVS-
RVS1
NA
D
Q
VS
S/H
RVS2
PWM
(3.0V) for more than 2 consecutive switching cycles
Extend
Auto
Restart
OVP
VS-UVP
Debounce time
(NVS-OVP), PWM pulses are disabled and FAN604H
enters Auto-Restart protection. VS over-voltage
conditions are usually caused by open circuit of the
secondary side feedback network or a fault condition in
the VS pin voltage divider resistors. For VS pin voltage
divider design, RVS1 is obtained from Equation 9, and
RVS2 is determined by the desired VS-OVP protection
function as
Counter
Figure 36 VS-UVP Protection Circuit
Externally Triggered Shutdown (SD)
When VDD is VDD-ON, Shut-Down comparing level is VSD-
(1.35V), after the startup time tSD-ST (1ms), the
TH-ST
1
RVS 2 RVS1
comparing level is changed to VSD-TH (1.0 V). By pulling
down SD pin voltage below the VSD-TH (1.0 V) shutdown
can be externally triggered and the FAN604H will enter
Auto-Restart mode protection. It can be also used for
external Over-Temperature-Protection by connecting a
NTC thermistor between the shutdown (SD)
programming pin and ground. An internal constant
current source ISD (103 µA) creates a voltage drop across
the thermistor. The resistance of the NTC thermistor
becomes smaller as the ambient temperature increases,
which reduces the voltage drop across the thermistor.
VOOVP NA
VVS OVP NS
(eq. 10)
1
VAUX
3.0V
RVS1
D
Q
NA
VS
S/H
RVS2
PWM
VS-OVP
Auto
Restart
Debounce time
Counter
SD pin voltage is sampled every gate cycle when VFB
>
VFB-Burst-H and sampled continuously when VFB < VFB-Burst-
L. When the voltage at SD pin is sampled to be below the
threshold voltage, VSD-TH (1.0 V), for a de-bounce time of
tD-SD (400 µs), Auto-Restart protection is triggered. A
capacitor may also be placed in parallel with the NTC
thermistor to further improve the noise immunity. The
capacitor should be designed such that SD pin voltage is
Figure 35 VS-OVP Protection Circuit
VS Under-Voltage-Protection (VS-UVP)
In the event of an output short, output voltage will drop
and the primary peak current will increase. To prevent
operation for a long time in this condition, FAN604H
incorporates under-voltage protection through VS pin.
Figure 36 shows the internal circuit for VS-UVP. By
sampling the auxiliary winding voltage on the VS pin at
the end of diode conduction time, the output voltage is
indirectly sensed. When VS sampling voltage is less than
VVS-UVP (0.4 V) and longer than de-bounce cycles NVS-
UVP, VS-UVP is triggered and the FAN604H enters
Extend Auto-Restart Mode.
To avoid VS-UVP triggering during the startup sequence,
a startup blanking time, tVS-UVP-BLANK (40 ms), is included
for system power on. For VS pin voltage divider design,
RVS1 is obtained from Equation 9 and RVS2 is determined
by Equation 10. VO-UVP can be determined by Equation
11.
more than VSD-TH-ST within the time of tSD-ST
.
5V
Debounce
103μA
CSD : 1nF ~ 20nF
SD
Auto-Restart
VDD-ON
VDD
NTC
Thermistor
CSD
tSD-ST
VSD-TH-ST
VSD-TH
VSD
VS Blanking
VFB < VFB-BURST-L
Figure 37 External OTP using SD Pin
NS
R
VOUVP
(1 VS1 )VVS UVP
RVS 2
(eq. 11)
NA
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17
FAN604H
Pulse-by-Pulse Current Limit
Current Sense Short Protection
During startup or overload condition, the feedback loop
is saturated to high and is unable to control the primary
peak current. To limit the current during such conditions,
FAN604H has pulse-by-pulse current limit protection
which forces the GATE to turn off when the CS pin
voltage reaches the current limit threshold, VCS-LIM
(0.89 V).
Current sense short protection prevents damage caused
by CS pin open or short to ground. After two switching
cycle, it will operate in Auto-Restart mode. Figure 38
shows the internal circuit of current sense short
protection. When abnormal system conditions occur,
which cause CS pin voltage lower than 0.2 V after de-
bounce time (tCS-short) for more than 2 consecutive
switching cycles, PWM pulses are disabled and
FAN604H enters Auto-Restart protection. The ICS-Short is
an internal current source, which is proportional to line
Secondary-Side Diode Shot Protection
When the secondary-side diode is damaged, the slope of
the primary-side peak current will be sharp within
leading-edge blanking time. To limit the current during
such conditions, FAN604H has secondary-side diode
short protection which forces the GATE to turn off when
the CS pin voltage reaches 1.6 V. After one switching
cycle, it will operate in Auto-Restart mode as shown in
voltage. The de-bounce time (tCS-short) is created by ICS-short
capacitor (2 pF) and threshold voltage (3.0 V). This de-
bounce time (tCS-short) is inversely proportional to the DC
,
link capacitor voltage, VBLK
.
Figure 38.
VBLK
GATE
ICS-Short
tCS-Short
Np
3.0V
2pF
GATE
D
Q
IDS
0.2V
1.6V
CS
PWM
RCS_COMP
RCS
Auto
Restart
CCSF
Counter
D
Q
PWM
Auto
Restart
Counter
0.89V
Pulse-by-Pulse
LEB
Figure 38 Current Sense Protection Circuit
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18
FAN604H
PCB Layout Guideline
.
.
.
.
.
As indicated by 2, the area enclosed by the
Print circuit board (PCB) layout and design are very
import for switching power supplies where the voltage
and current change with high dv/dt and di/dt. Good PCB
layout minimizes excessive EMI and prevent the power
supply from being disrupted during surge/ESD tests. The
following guidelines are recommended for layout designs.
transformer auxiliary winding, DAUX and CVDD
should also be small.
,
Place CVDD, CVS, RVS2, CFB, RCCR, CCCR
,
RCS_COMP and CCSF close to the controller for
good decoupling and low switching noise.
As indicated by 3, the ground of the control
circuits should be connected as a single point
first, then to other circuitry.
Connect ground by 3 to 2 to 4 to 1 sequence.
This helps to avoid common impedance
interference for the sense signal.
Regarding the ESD discharge path, use the
shortcut pad between AC line and DC output
(most recommended). Another method is to
discharge the ESD energy to the AC line
through the primary-side main ground 1.
Because ESD energy is delivered from the
secondary side to the primary side through the
transformer stray capacitor or the Y capacitor,
the controller circuit should not be placed on the
discharge path. 5 shows where the point-
discharge route can be placed to effectively
bypass the static electricity energy.
For the surge path, select fusible resistor of wire
wound type to reduce inrush current and surge
energy and use π input filter (two bulk
capacitors and one inductance) to share the
surge energy.
.
To improve EMI performance and reduce line
frequency ripples, the output of the bridge
rectifier should be connected to capacitors CBLK1
and CBLK2 first, then to the transformer and
MOSFET.
.
The primary-side high-voltage current loop is
CBLK2 - Transformer - MOSFET - RCS - CBLK2
The area enclosed by this current loop should be
as small as possible. The trace for the control
signal (FB, CS, VS and GATE) should not go
across this primary high-voltage current loop to
avoid interference.
.
.
.
Place RHV for protection against the inrush spike
on the HV pin (150kΩ is recommended).
RCS should be connected to the ground of CBLK2
directly. Keep the trace short and wide (Trace 4
to 1) and place it close to the CS pin to reduce
switching noise. High-voltage traces related to
the drain of MOSFET and RCD snubber should
be away from control circuits to prevent
unnecessary interference. If a heat sink is used
for the MOSFET, connect this heat sink to
ground.
.
RSNS CSNP
5
TX
LF
DR
CO
Np
Ns
VO
CSNP
RSNP
Fuse
XC
Choke
RHV1
CBLK1
CBLK2
Bridge
AC IN
DSNP
RBias1
RBias2
RHV2
Photo
coupler
1
CComp2
RF1
RGR
HV
GATE
R
Comp CComp1
Shunt
Regulator
FB
FAN604H
SD
RGF DG
CS
VDD
VS
RF2
Na
RCS_COMP
RCS
CCR
Photo
coupler
5
CY
CFB
4
GND
NTC
RSD
DAUX
RVS1
RCCR
CCCR
2
3
RVS2
CCSF
CVDD
CVS
Figure 39 Recommended Layout for FAN604H
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19
FAN604H
ORDERING INFORMATION
Device
Operating Temperature Range
Package
Shipping †
10-Lead, Small Outline Package (SOIC), JEDEC
MS-012, .150-Inch Narrow Body
FAN604HMX
Tape & Reel
-40C to +125C
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D
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20
FAN604H
PACKAGE DIMENSIONS
4.90±0.1
4.00
A
B
10
6
1.75
0.65
5.60
PIN#1
IDENT
3.90±0.05 6.00±0.10
1.00
1
5
0.20 C
(0.25)
1.00
2X
0.375±0.075
LAND PATTERN RECOMMENDATION
0.475±0.435 X 45°
TOP VIEW
(R0.10)
GAGE
0.36
(R0.10)
PLANE
1.25 MIN
1.75 MAX
0.10 C
0.835±0.435
0.175±0.075
SIDE VIEW
C
(1.04)
4°±4°
SEATING
PLANE
DETAIL A
NOTES:
A. THIS PACKAGE DOES NOT FULLY CONFORM
TO JEDEC REGISTRATION, MS-012.
B. ALL DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D. LAND PATTERN STANDARD:
0.175±0.075
SOIC127P600X175.10M
SEE DETAIL A
E. DRAWING FILENAME: MKT-M10ArevB
FRONT VIEW
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21
FAN604H
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22
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