FAN6240M6X [ONSEMI]

Secondary-Side Synchronous Rectifier Controller for Flyback Converters;


型号：	FAN6240M6X
厂家：	ONSEMI
描述：	Secondary-Side Synchronous Rectifier Controller for Flyback Converters
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中文：	中文翻译
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July 2016

FAN6240

Secondary-Side Synchronous Rectifier Controller for

Flyback Converters

Features

Description

The FAN6240M6X is a secondary-side synchronous

rectifier (SR) controller for an isolated flyback converter

operating in Discontinuous Conduction Mode (DCM).

The adaptive dead-time control algorithm minimizes the

body diode conduction of SR MOSFET while

guaranteeing stable and robust SR operation against

noise and disturbance caused by the circuit parasitic.

30 V rated input voltage LDO and Low VDD Under-

Voltage Lockout (UVLO) voltage allow FAN6240M6X to

be used for wide ranges of switched mode power supply

output voltage without additional circuit.

Works in Discontinuous Conduction Mode (DCM).

Adaptive Turn-off Trigger Blanking Time for easier

use

Turn-on Trigger Blanking Time (Minimum-OFF

Time) for Improved Noise Immunity

Supports High-Frequency Applications up to

200 kHz

Minimum Turn-on Delay (20 ns)

Adaptive Turn-off Threshold Control for Minimized

SR MOSFET Body Diode Conduction (Dead-Time

is independent of SR MOSFET)

Applications

Battery Chargers for Smart Phones, Feature

Phones, and Tablet PCs

Wide Voltage Range for LDO Input up to 30 V

Small Footprint: SOT-23 6 Pin Package

AC-DC Adapters for Portable Devices that Require

CV/CC Control

Ordering Information

Operating

Temperature Range

Packing

Part Number

Package

Method

6-Lead, SOT23, JEDEC MO-178 Variation AB,

1.6 mm Wide

FAN6240M6X

Tape & Reel

-40C to +125C

www.fairchildsemi.com

FAN6240 • Rev. 1.0

Application Diagram

V_o(+)

T_X1

L₁

R₃

C₃

BR1

C₇

N_P

N_S

R₁₂

C₆

L_CM

C₁

C₂

R₄

D₁

AC IN

R₁

R₂

Fuse

Q₁

R₁₅

R₅

R₁₆

R₁₃

R₁₇

R₆

R₁₄

Gate

R₁₈

C₈

R₇

R₈

IMIN

GATE

GND

DRAIN

FAN602

D₂

VDD

10 ^GND

SOURCE

FAN6240M6X

Photo

R₁₉

R₉

C₅

FMAX

R₁₁

VDD

VIN

N_A

C₉

C₄

R₁₀

C_Y

GATE

Figure 1.

Typical Application

Internal Block Diagram

VDD

VIN

LDO

Turn-on

Trigger

V_{IN_ON}/ V_{IN_OFF}

SR_COND

Blanking

Adaptive Dead

Time Control

T_ARM

Slope

Detection

V_{TH_ARM}

V_{TH_ON}

SET

GATE

DRAIN

Turn-on

210mV

CLR

Turn-off

V_{TH_OFF}

10mV

SOURCE

Turn-off

Trigger

Blanking

SR_COND

SKIP

Minimum Turn

On Time

SR_COND

GND

Figure 2.

Function Block Diagram

www.fairchildsemi.com

FAN6240 • Rev. 1.0

Marking Information

Axx:

TT:

ACD: FAN6240M6X

Wafer Lot Code

• • • •

: Year Code

_ _ _:

AXXTT

Week Code

- - -

Figure 3.

Top Mark

Pin Configuration

GATE

GND

VDD

DRAIN

SOURCE

VIN

Figure 4.

Pin Configuration

Pin Definitions

Pin #

Name

Description

GATE

GND

Gate drive output

Ground

Internal regulator 5 V output and gate drive power supply rail. Bypass with 1uF capacitor to

GND.

VDD

VIN

LDO input, supports up to 30 V operation. An integrated 5 V LDO generates the internal VDD

power supply rail for the low-voltage control circuitry.

SOURCE Synchronous rectifier source sense input.

DRAIN Synchronous rectifier drain sense input.

www.fairchildsemi.com

FAN6240 • Rev. 1.0

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Min. Max. Unit

V_IN

V_DD

Power Supply Input Pin Voltage

-0.3

-1

6.5

100

6.5

Internal Regulator Output Pin Voltage

Drain Sense Input Pin Voltage

Gate Drive Output Pin Voltage

V_DRAIN

V_GATE

-0.3

-1

V_SOURCESource Sense Input Pin Voltage

P_D

Θ_JA

T_J

Power Dissipation (T_A=25°C)

°C/W

°C

Thermal Resistance (Junction-to-Ambient Thermal)

Operating Junction Temperature

235

150

260

-40

-60

T_STG

T_L

Storage Temperature Range

Lead Temperature (Soldering) 10 Seconds

Human Body Model, ANSI / ESDA /

JEDEC JS-001-2012

2.5

1.5

ESD

Electrostatic Discharge Capability

Charged Device Model, JESD22-C101

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

2. All voltage values are with respect to the GND pin.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance. Fairchild does not recommend exceeding them or

designing to Absolute Maximum Ratings.

Symbol

Parameter

Power Supply Input Pin Voltage

Min.

Typ.

Max.

Unit

V_IN

V_DD

2.8

Internal Regulator Output Pin Voltage

Drain Sense Input Pin Voltage

Gate Drive Output Pin Voltage

Source Sense Input Pin Voltage

V_DRAIN

V_GATE

V_SOURCE

-0.3

100

www.fairchildsemi.com

FAN6240 • Rev. 1.0

Electrical Characteristics

V_IN= 12 V and T_J= -40°C to 125°C unless otherwise specified.

Symbol

Input Voltage

V_{IN_ON}

Parameter

Conditions

Min. Typ. Max. Unit

Turn-On Threshold

V_INRising

V_INFalling

3.1

2.8

3.4

2.9

3.7

3.0

V_{IN_OFF}

Turn-Off Threshold

f_SW= 100 kHz, C_GATE= 3.3 nF,

V_IN= 5 V

I_{IN_OP}

Operating Current

3.5

Power Supply Section

V_DD

Internal LDO Output Voltage

V_IN= 20 V

5.00 5.25 5.50

Drain Voltage Sensing Section

Maximum of adaptive offset current

(15 steps, 6 µA resolution)

I_OFFSET

105

µA

R_DRAIN= 0 Ω (includes comparator

input offset voltage)

V_{TH_ON}

Turn-On Threshold

-235 -210 -185 mV

(3)

T_ON.DLY

Turn-On Delay

(3)

V_{TH_OFF}

Turn-Off Threshold

(3)

T_OFF.DLY

Turn-Off Delay

V_{TH_ARM}

Gate Re-arming Threshold

V_IN= 5 V, (Typically 0.7*V_DD

)

3.3

3.5

3.7

Gate Re-arming Time for Slope

Detection

(3)

T_ARM

ns

(3)

V_{TH_HGH}

SR OFF Detection Threshold

0.5

Minimum On-Time and Minimum Off-Time

Ratio between minimum on time

Adaptive Minimum On-Time Ratio and SR conduction of previous

switching cycle

(3)

K_TON

t_{ON_MIN.LL}

Minimum On-Time Lower Limit

Minimum On-Time Upper Limit

300

1.0

400

500

1.4

µs

(3)

t_{ON_MIN.UL}

Default Option for Medium

t_{OFF_MIN}

Minimum Off-Time

Frequency

1.2

µs

Output Driver Section

V_OL

V_OH

Output Voltage Low

V_IN= 6 V

0.25

V

Output Voltage High

5.0

V_IN= 6 V, C_L=3300 pF,

GATE = 1 V~4 V

t_R

t_F

Rise Time

V_IN=6 V, C_L= 3300 pF,

GATE = 4 V~1 V

Fall Time

Adaptive Dead-Time Control

From GATE OFF to V_DRAINrising

above V_{TH_HGH}

(3)

t_DEAD

Dead-Time Self-Tuning Target

290

Note:

3. Not tested and guaranteed by design.

www.fairchildsemi.com

FAN6240 • Rev. 1.0

Functional Description

Theory of SR Control Operation

For an ideal circuit operation, the SR control algorithm

of FAN6240 is very straightforward. FAN6240 controls

the SR MOSFET based on the instantaneous drain-to-

source voltage as illustrated in Figure 5. When the body

diode starts conducting, the drain-to-source voltage

V_DS.SR

V_{TH_OFF}

GND

V_{TH_ON}

drops below the turn-on threshold (V_{TH_ON}

) which

T_ON.DLY

V_GS.SR

T_DEAD

triggers the turn-on of the gate. Then the drain-to-source

voltage is determined by the product of R_DSONand

instantaneous SR current. When the drain-to-source

voltage reaches the turn-off threshold (V_{TH_OFF}) as SR

MOSFET current decreases to near zero, FAN6240

turns off the gate. If the turn off threshold (V_{TH_OFF}) is

very close to zero, the turn off dead time can be

minimized.

I_SD.SR

Figure 5.

SR MOSFET Operation Waveforms

(Ideal Case)

SR Turn-On Algorithm

As the diagram shown in Figure 6, the turn-on of SR GATE is triggered by the three input signals of AND gate. The

first input signal is TURN_ON_ALLOW signal, which is given after t_{OFF_MIN}from the falling edge of V_GS.SRsignal. The

second input is the TURN_ON_TRG signal, which is enabled after DRAIN pin voltage drops below V_{TH_ON}. The third

signal is T_ARMwhich allows turn-on trigger only when SR drain voltage drops fast with a large slope, preventing SR

from triggering by the drain resonance voltage in DCM operation.

V_{TH_ARM}

V_{TH_OFF}

GND

V_DS.SR

V_{TH_ON}

T_ARM

ARM

T_ARM

t_{OFF_MNI}

TURN_ON_ALLOW

TURN_ON_TRG

V_GS.SR

I_DS.SR

Figure 6.

SR Turn-On Algorithm

www.fairchildsemi.com

FAN6240 • Rev. 1.0

SR Turn-Off Algorithm

As diagram shown in Figure 7, the turn-off of SR GATE is triggered by the two input signals of AND gate. The first

input signal is turn off signal, which is enabled when V_DS.SR>V_{TH_OFF .}The second input is TURN_OFF_ALLOW signal

given from the adaptive turn-off blanking. The blanking time is adaptively determined as half of SR conduction time

(SR_COND) of the previous switching cycle for better noise immunity.

V_{TH_OFF}

GND

V_DS.SR

V_{TH_ON}

Turn off

K_TON*SR_COND

TURN_OFF_ALLOW

SR_COND

V_GS.SR

I_SD.SR

Figure 7.

SR Turn-Off Algorithm

SR Skipping Mode Algorithm

As diagram shown in Figure 8, FAN6240 disables SR gate signal (SR skipping) at next cycle when previous cycle SR

conduction time V_GS.SRsignal is smaller than the minimum ON time t_{ON_MIN.LL}in order reduce power consumption. This

operation occurs only when the burst mode entry level of the primary side PWM controller is extremely low.

V_{TH_OFF}

GND

V_DS.SR

SR condition

time

V_GS.SR

I_SD.SR

Figure 8.

SR Skipping Diagram

www.fairchildsemi.com

FAN6240 • Rev. 1.0

REVISIONS

LTR

DESCRIPTION

DATE

11/4/2006

5 JULY 07

E.C.N.

BY/APP'D

H.ALLEN

RELEASE TO DOCUMENT CONTROL

DWG UPDATED TO CONFORM TO MO178

L.HUEBENER

0.15 C A-B

SYMM

2.9

1.9

(0.95)

(1.00MIN)

1.4

1.6

2.8

(2.60)

(0.70MIN)

0.15 C D

0.15 C

PIN 1 INDEX AREA

2X 3 TIPS

0.95

(1.90)

2X 0.3-0.5

0.20

C A-B D

LAND PATTERN RECOMMENDATION

SEE DETAIL A

1.45 MAX

1.30

0.90

0.08

0.22

0.10

0.15

0.05

R0.10MIN

NOTES:

GAGE PLANE

0.25

A. THIS PACKAGE CONFORMS TO JEDEC MO-178,

VARIATION AB.

B. ALL DIMENSIONS ARE IN MILLIMETERS.

C. DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS

OR GATE BURRS.

R0.10MIN

8°

0°

D. DOES NOT INCLUDE INTERLEAD FLASH OR

PROTRUSIONS.

E. DIMENSIONS AND TOLERANCING AS PER ASME

Y14.5M-1994

0.60

0.30

SEATING PLANE

0.60 REF

F. DRAWING FILE NAME: MA06EREV2

DETAIL A

SCALE: 2:1

APPROVALS

L.HUEBENER

DATE

5 JULY 07

17 JULY 07

H.ALLEN

6LD,SOT23,JEDEC

MO-178 VARIATION AB,

1.6MM WIDE

MKT-MA06E

1:1 NA

FORMERLY:

SHEET :

N/A

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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FAN6240M6X [ONSEMI]

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