FAN6248HD [ONSEMI]
Advanced Synchronous Rectifier Controller for LLC Resonant Converter;型号: | FAN6248HD |
厂家: | ONSEMI |
描述: | Advanced Synchronous Rectifier Controller for LLC Resonant Converter |
文件: | 总15页 (文件大小:281K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FAN6248HC/HD/LC/LD
Advanced Synchronous
Rectifier Controller for LLC
Resonant Converter
The FAN6248 is an advanced synchronous rectifier (SR) controller
that is optimized for LLC resonant converter topology with minimum
external components. It has two driver stages for driving the SR
MOSFETs which are rectifying the outputs of the secondary
transformer windings. The two gate driver stages have their own
sensing inputs and operate independently of each other. The adaptive
parasitic inductance compensation function minimizes the body diode
conduction maximizing the efficiency. The advanced control
algorithm allows stable SR operation over entire load range.
According to the operating frequency and turn-off threshold voltage,
FAN6248 has four different versions − FAN6248HCMX,
FAN6248HDMX, FAN6248LCMX, FAN6248LDMX.
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SOIC−8
CASE 751EB
MARKING DIAGRAM
ON
ZXYTT
Features
FAN6248UV
• Highly Integrated Self-contained Control of Synchronous Rectifier
with a Minimum External Component Count
• Optimized for LLC Resonant Converter
• Anti Shoot-through Control for Reliable SR Operation
• Separate 100 V Rated Sense Inputs for Sensing the Drain and Source
Voltage of each SR MOSFET
U
V
Z
X
Y
= Frequency, H: High, L: Low
= V
Level, C or D
TH_OFF
= Assembly Plant Code
= Year Code
= Two Week Code
= Die Run Code
• Adaptive Parasitic Inductance Compensation to Minimize the Body
Diode Conduction
TT
• SR Current Inversion Detection under Light Load Condition
• Light Load Detection to Increase Dead Time Target
PIN CONNECTIONS
• Adaptive Minimum on Time for Noise Immunity
• Operating Voltage Range up to 30 V
1
2
3
4
8
7
6
5
GATE1
GND
VD1
GATE2
VDD
VD2
• Low Start-up and Stand-by Current Consumption
• Operating Frequency Range from 25 kHz up to 700 kHz
• SOIC−8 Package
VS1
VS2
• High Driver Output Voltage of 10.5 V to Drive All MOSFET Brands
(Top View)
to the Lowest R
DS_ON
• Low Operating Current in Green Mode (typ. 350 mA)
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
Applications
• High Power Density Laptop Adapter
• High Power Density Adapter
• Large Screen LCD−TV, PDP−TV, RP−TV Power
• High-efficiency Desktop and Server Power Supplies
• Networking and Telecom Power Supplies
• High Power LED Lighting
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
January, 2018 − Rev. 2
FAN6248HC/D
FAN6248HC/HD/LC/LD
M2
Optional
Roffset2
Bridge
Diode
Q1
Q2
EMI
Filter
PFC
Stage
VAC
Cin
Cr
Lr
VO
Lp
RO
CO
Optional
M1
LLC
Controller
Shunt
Regulator
Figure 1. Typical Application Schematic of FAN6248
VDD
7.2V
4.5/4.2V
VD1_HGH
GREEN
VD2_HGH
IOFFSET1
IOFFSET2
VTH_HGH
DLY_EN
DLY_EN
VTH_HGH
D
Q
Q
Q
Q
D
Adaptive
turn−on
debounce
Adaptive
turn−on
debounce
VD1
VD2
VS2
VTH_ON
VTH_ON
Turn−on
Turn−on
CLR
CLR
Turn−off
Turn−off
VTH_OFF1,2
VTH_OFF1,2
VS1
Turn−off
Trigger
Turn−off
Trigger
SRC_INV
SRC_INV
Blanking
Blanking
GATE2
GATE1
GATE1
GATE2
VD1_HGH
SR Current
Inversion detect
SRC_INV
Green Mode
DLY_EN
VD1_HGH
GREEN
VD2_HGH
Light Load
Detection
IOFFSET1
GND
Figure 2. Internal Block Diagram of FAN6248
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2
FAN6248HC/HD/LC/LD
PIN DESCRIPTION
Pin Number
Pin Name
Description
1
2
3
GATE1
GND
Gate drive output for SR1
Ground
VD1
Synchronous rectifier drain sense input. A I
current source flows out of the DRAIN pin such
OFFSET1
that an external series resistor can be used to adjust the synchronous rectifier turn-off threshold.
The I current source is turned off when V is under-voltage or when switching is disabled in
OFFSET1
DD
green mode
4
5
6
VS1
VS2
VD2
Synchronous rectifier source sense input for SR1
Synchronous rectifier source sense input for SR2
Synchronous rectifier drain sense input. A I
current source flows out of the DRAIN pin such
OFFSET2
that an external series resistor can be used to adjust the synchronous rectifier turn-off threshold.
The I current source is turned off when V is under-voltage or when switching is disabled in
OFFSET2
DD
green mode
7
8
VDD
Supply Voltage
GATE2
Gate drive output for SR2
ORDERING AND SHIPPING INFORMATION
†
Ordering Code
FAN6248HCMX
FAN6248HDMX
FAN6248LCMX
FAN6248LDMX
Device Marking
FAN6248HC
FAN6248HD
FAN6248LC
FAN6248LD
V
/ V
Package
SOIC−8
SOIC−8
SOIC−8
SOIC−8
Shipping
TH_OFF1
TH_OFF2
25 mV / 50 mV
0 mV / 25 mV
25 mV / 50 mV
0 mV / 25 mV
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
FAN6248HC/HD/LC/LD
MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
−1
Max
30
Unit
V
V
Power Supply Input Pin Voltage
Drain Sense Input Pin Voltage
Gate Drive Output Pin Voltage
DD
V
V
100
30
V
D1, D2
V
−0.3
V
GATE1,
V
GATE2
V
V
Source Sense Input Pin Voltage
−0.4
0.4
0.625
165
150
150
260
4
V
W
S1, S2
P
Power Dissipation (T = 25°C)
D
A
Q
Thermal Resistance (Junction-to-Ambient Thermal)
Operating Junction Temperature
°C/W
°C
JA
T
−40
−60
J
T
Storage Temperature Range
°C
STG
T
Lead Temperature (Soldering) 10 Seconds
°C
L
ESD
Electrostatic Discharge
Capability
Human Body Model, ANSI / ESDA / JEDEC
JS−001−2012
kV
Charged Device Model, JESD22−C101
1.75
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All voltage values are with respect to the GND pin.
THERMAL CHARACTERISTICS
Symbol
Rating
Value
22
Unit
_C/W
_C/W
R
Thermal Characteristics
Thermal Characteristics
y
JT
R
165
q
JA
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
27
Unit
V
V
DD
VDD Pin Supply Voltage to GND (Note 2)
Drain Sense Input Pin Voltage
0
V ,V
D1 D2
−0.7
−0.4
−40
100
0.4
V
V
V
Source Sense Input Pin Voltage
V
S1 S2
T
A
Operating Ambient Temperature (Note 3)
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Allowable operating supply voltage V can be limited by the power dissipation of FAN6248 related to switching frequency, load capacitance
DD
and ambient temperature.
3. Allowable operating ambient temperature can be limited by the power dissipation of FAN6248 related to switching frequency, load
capacitance on GATE pin and V
.
DD
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FAN6248HC/HD/LC/LD
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to +125°C unless otherwise specified)
DD
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
INPUT VOLTAGE
V
Turn-On Threshold
V
V
V
rising
falling
rising
4.2
4.0
4.5
4.2
7.2
8.5
4.7
4.4
V
DD_ON
DD
V
Turn-Off Threshold
DD_OFF
DD_GATE_ON
DD
*
V
SR Gate Enable Threshold Voltage
Operating Current
V
DD
I
f
= 100 kHz, C = 3.3 nF
GATE
7
10
mA
mA
mA
DD_OP
DD_SRARTUP
SW
I
V
= V
− 0.1 V
200
500
DD
DD
DD_ON
I
Operating Current in Green Mode
V
= 12 V (no switching)
350
DD_GREEN
DRAIN VOLTAGE SENSING SECTION (V = V
)
D1
D2
*
V
Comparator Input Offset Voltage
and I
−1
0
1
mV
OSI
*
I
I
Maximum of adaptive offset
112.5
135
157.5
mA
OFFSET
OFFSET1
OFFSET2
current (15 steps, 9 mA resolution)
I
=I
OFFSET OFFSET_STEP15
V
Turn-On Threshold
R
= 0 W (includes
DRAIN
−290
−240
80
−190
mV
ns
TH_ON
comparator input offset voltage)
*
t
Turn on delay for de-bounce time
when turn-on delay mode is disabled
by detecting normal SR current
From V falling below V to
ON_DLY
D1
TH_ON
(With
= 0 nF
V
GATE
rising above V
G_HG
50 mV overdrive), C
GATE
*
t
Turn on delay for de-bounce time
when turn-on delay mode is enabled
by detecting SR current inversion for
HC and HD version
From V falling below V to
TH_ON
850
ns
ns
ON_DLY2_H
D1
V
rising above V
(With
= 0 nF
GATE
G_HG
50 mV overdrive), C
GATE
*
t
Turn on delay for de-bounce time
when turn-on delay mode is enabled
by detecting SR current inversion for
LC and LD version
From V falling below V to
TH_ON
1100
ON_DLY2_L
D1
V
GATE
rising above V
(With
G_HG
50 mV overdrive), C
= 0 nF
GATE
*
V
V
V
V
First Level Turn-Off Threshold
for HC and LC version
R
= 0 W (includes
DRAIN
25
50
0
mV
mV
mV
mV
ns
TH_OFF1_C
TH_OFF2_C
TH_OFF1_D
comparator input offset voltage)
R = 0 W (includes
DRAIN
comparator input offset voltage)
R = 0 W (includes
DRAIN
*
*
*
Second Level Turn-Off Threshold
for HC and LC version
First Level Turn-Off Threshold
for HD and LD version
comparator input offset voltage)
Second Level Turn-Off Threshold
for HD and LD version
R
= 0 W (includes
25
50
TH_OFF2_D
DRAIN
comparator input offset voltage)
From V rising above V to
TH_OFF
*
t
Comparator Delay of V
OFF_DLY
TH_OFF1
D1
V
falling below V
(With
= 0 nF
GATE
G_LW
10 mV overdrive), C
GATE
V
Drain Voltage High Detect Threshold
V
D1
Rising
0.80
1
1.20
V
TH_HGH
*
t
V
Detection Blanking Time for From V falling below V
540
ns
DB_HGH_H
TH_HGH
D1
TH_ON
TH_ON
HC and HD version
*
t
V
Detection Blanking Time for From V falling below V
1
1
ms
DB_HGH_L
TH_HGH
D1
LC and LD version
*
V
Forced Turn-off Threshold
V
D1
> V
= V
V
OFF_FORCE
OFF_FORCE
TH_HGH_EN
MINIMUM ON-TIME AND MAXIMUM ON-TIME
*
K
TON
Adaptive Minimum On Time Ratio
Ratio between t
and SR
25
%
ON_MIN
conduction time of previous
switching cycle
*
t
Minimum On-Time Lower Limit
for HC and HD version
t
t
< t <
ON_MIN
200
1.2
ns
ON_MIN_LH
ON_MIN_LH
ON_MIN_UH
t
Minimum On-Time Upper Limit
for HC and HD version
0.96
1.44
ms
ON_MIN_UH
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FAN6248HC/HD/LC/LD
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to +125°C unless otherwise specified) (continued)
DD
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MINIMUM ON-TIME AND MAXIMUM ON-TIME
*
t
Minimum On-Time Lower Limit
for LC and LD version
t
t
< t <
ON_MIN
0.4
4
ms
ms
ns
ms
ms
ms
ON_MIN_LL
ON_MIN_LL
ON_MIN_UL
t
Minimum On-Time Upper Limit
for LD and LD version
3.2
380
0.85
4.8
820
1.65
ON_MIN_UL
SR_CNDT_H
t
Minimum SR Conduction Time to
enable SR for HC and HD version
The duration from turn-on trigger
to V rising above V
600
1.2
15
DS
TH_HGH
t
Minimum SR Conduction Time to
enable SR for LC and LD version
The duration from turn-on trigger
to V rising above V
SR_CNDT_L
DS
TH_HGH
*
t
Maximum SR Turn-on Time
for HC and HD version
SR_MAX_H
*
t
Maximum SR Turn-on Time
for LC and LD version
30
SR_MAX_L
REGULATED DEAD TIME
*
t
Dead time regulation target
for HC and HD version
From V
falling below V
280
320
ns
ns
DEAD_H
GATE
G_LW
TH_HGH
to V rising above V
DS
*
t
Dead time regulation target under
light load condition for HC and HD
version
From V
falling below V
DEAD_H_LIGHT
GATE
G_LW
TH_HGH
to V rising above V
DS
*
t
Dead time regulation target
for LC and LD version
From V
falling below V
320
360
ns
ns
DEAD_L
GATE
G_LW
TH_HGH
to V rising above V
DS
*
t
Dead time regulation target under
light load condition for LC and LD
version
From V
falling below V
DEAD_L_LIGHT
GATE
G_LW
TH_HGH
to V rising above V
DS
*
t
Too small dead time threshold to
From V
falling below V
50
ns
%
TSDT
GATE
G_LW
to V rising above V
DS TH_HGH
speed up I
change
OFFSET
(Speed up 2 times)
*
K
Adaptive SR current inversion
detection time Ratio between T
V > V
GATE
V
TH_OFF
and V >
DS
6.25
INV
G_HG
INV
and SR conduction time of previous
switching cycle
K
INV
= 0.25 × K
TON
*
h
Normal switching cycles without
capacitive current spike to exit SR
current inversion detection state
31
cycle
INV_EXT
which has t
ON_DLY2
GREEN MODE CONTROL
t
Non-Switching Period to Enter Green
Mode for HC and HD version
Non switching cycles between
burst switching bundles
60
120
130
240
30
80
160
180
320
40
100
200
230
400
50
ms
ms
ms
ms
ms
GRN_ENT_H
t
Non-Switching Period to Enter Green
Mode for LC and LD version
Non switching cycles between
burst switching bundles
GRN_ENT_L
t
De-bounce time to Enter Green Mode De-bounce time after t
for HC and HD version
GRN_ENT_DBNC_H
GRN.ENT_H
t
De-bounce time to Enter Green Mode De-bounce time after t
for LC and LD version
GRN_ENT_DBNC_L
GRN_ENT_L
t
Non-Switching Period to Exit Green
for HC and HD version
Non switching cycles between
burst switching bundles
GRN_EXT_H
t
Non-Switching Period to Exit Green
Mode for LC and LD version
Non switching cycles between
burst switching bundles
60
4
80
7
100
10
ms
GRN_EXT_L
h
Continuous switching cycles to exit
Green Mode for HC, HD, LC and LD
version
cycle
CSW_EXT
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FAN6248HC/HD/LC/LD
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to +125°C unless otherwise specified) (continued)
DD
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
GREEN MODE CONTROL
t
Switching period to be recognized as
normal switching for HC and HD
version
13
20
27
ms
S_NORMAL_H
t
Switching period to be recognized as
normal switching for LC and LD
version
27
40
53
ms
S_NORMAL_L
OUTPUT DRIVER SECTION
Gate Clamping Voltage
V
12 V < V < 25 V
V
V
9
7
10.5
12
GATE_MAX
DD
V
OL
Output Voltage Low
V
= 12 V, V = V = 2 V,
= 50 mA
1.5
DD
D1
D2
I
GATE
V
OH
Output Voltage High
V
V
V
= 12 V, I = −50 mA
GATE
V
A
DD
DD
DD
DD
*
I
Peak Source Current for Turning On
Peak Sink Current for Turning Off
Rise Time
= 12 V, V
= 12 V, V
= 2 V
= 7 V
0.7
1.4
50
SOURCE
GATE
GATE
*
I
A
SINK
*
t
R
V
V
= 12 V, C = 3.3 nF,
ns
L
= 2 V ³ 7 V
GATE
*
t
F
Fall Time
V
V
= 12 V, C = 3.3 nF,
30
4
ns
V
DD
L
= 7 V ³ 2 V
GATE
*
*
V
V
Gate voltage considered as turned off Gate falling
for adaptive dead time control
G_LW
Gate voltage considered as turned on Gate rising
for adaptive dead time control
6
V
G_HG
SWITCHING FREQUENCY
*
f
Maximum Switching Frequency
Minimum Switching Frequency
700
kHz
kHz
MAX
*
f
25
MIN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
*Not tested but guaranteed by design
KEY DIFFERENT PARAMETERS FOR FAN6248 OPTIONS
Item
FAN6248HC
850 ns
540 ns
200 ns
1.2 ms
FAN6248HD
850 ns
540 ns
200 ns
1.2 ms
FAN6248LC
1100 ns
1 ms
FAN6248LD
1100 ns
1 ms
t
ON_DLY2
t
DB_HGH
t
400 ns
4 ms
400 ns
4 ms
ON_MIN_L
ON_MIN_U
t
t
0.6 ms
0.6 ms
1.2 ms
30 ms
1.2 ms
30 ms
SR_CNDT
t
15 ms
15 ms
SR_MAX
t
280 ns
320 ns
80 ms
280 ns
320 ns
80 ms
320 ns
360 ns
160 ms
80 ms
320 ns
360 ns
160 ms
80 ms
DEAD
DEAD_LIGHT
t
t
GRN_ENT
t
40 ms
40 ms
GRN_EXT
t
20 ms
20 ms
40 ms
40 ms
S_NORMAL
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FAN6248HC/HD/LC/LD
TYPICAL CHARACTERISTICS
4.7
4.5
5.0
4.8
4.6
4.4
4.3
4.1
4.2
4.0
3.9
3.7
−40 −30 −15
0
25
50
75
85 100 125
85 100 125
85 100 125
−40 −30 −15
0
25
50
75
85 100 125
Temperature [5C]
Temperature [5C]
Figure 3. VDD_ON
Figure 4. VDD_OFF
9.0
8.6
8.2
7.8
7.4
7.0
480
440
400
360
320
280
240
200
−40 −30 −15
0
25
50
75
85 100 125
−40 −30 −15
0
25
50
75
Temperature [5C]
Temperature [5C]
Figure 5. IDD_OP
Figure 6. IDD_GREEN
1.3
1.1
−200
−220
−240
−260
−280
−300
0.9
0.7
0.5
0.3
−40 −30 −15
0
25
50
75
−40 −30 −15
0
25
50
75
85 100 125
Temperature [5C]
Temperature [5C]
Figure 7. VTH_HIGH
Figure 8. VTH_ON
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FAN6248HC/HD/LC/LD
TYPICAL CHARACTERISTICS
1100
1050
1000
950
1500
1400
1300
1200
1100
1000
900
850
−40 −30 −15
0
25
50
75
85 100 125
85 100 125
85 100 125
−40 −30 −15
0
25 50
75
85 100 125
85 100 125
85 100 125
Temperature [5C]
Temperature [5C]
Figure 10. tON_DLY2_L
Figure 9. tON_DLY2_H
700
620
540
1.7
1.5
1.3
460
380
1.1
0.9
300
0.7
−40 −30 −15
0
25
50
75
−40 −30 −15
0
25 50
75
Temperature [5C]
Temperature [5C]
Figure 11. tSR_CNDT_H
Figure 12. tSR_CNDT_L
90
86
82
180
172
164
78
74
156
148
70
140
−40 −30 −15
0
25
50
75
−40 −30 −15
0
25
50
75
Temperature [5C]
Temperature [5C]
Figure 13. tGRN_ENT_H
Figure 14. tGRN_ENT_L
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FAN6248HC/HD/LC/LD
TYPICAL CHARACTERISTICS
48
44
40
90
86
82
36
32
78
74
28
70
−40 −30 −15
0
25
50
75
85 100 125
85 100 125
85 100 125
−40 −30 −15
0
25
50
75
85 100 125
85 100 125
85 100 125
Temperature [5C]
Temperature [5C]
Figure 15. tGRN_EXT_H
Figure 16. tGRN_EXT_L
12
10
8
15
13
11
6
4
9
7
2
5
−40 −30 −15
0
25
50
75
−40 −30 −15
0
25
50
75
Temperature [5C]
Temperature [5C]
Figure 17. hCSW_EXT
Figure 18. VGATE_MAX
15
13
11
0.40
0.32
0.24
9
7
0.16
0.08
5
0
−40 −30 −15
0
25
50
75
−40 −30 −15
0
25
50
75
Temperature [5C]
Temperature [5C]
Figure 19. VOH
Figure 20. VOL
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FAN6248HC/HD/LC/LD
APPLICATION INFORMATION
Present information
=instantaneous Vdrain type
Present information+Previous cycle information
= Mixed type control
Basic Operation Principle
FAN6248 controls the SR MOSFET based on the
instantaneous drain-to-source voltage sensed across DRAIN
and SOURCE pins. Before SR gate is turned on, SR body
diode operates as the conventional diode rectifier. Once the
body diode starts conducting, the drain-to-source voltage
Gate
Q
SR on
SR off
S
R
VDrain
VSAW
S
Voffset
control
Voffset
=Roffset x Ioffset
Q
VTH_off
drops below the turn-on threshold voltage V
triggers the turn-on of the SR gate. Then the drain-to-source
voltage is determined by the product of turn-on resistance
which
TH_ON
Previous cycle information
=Prediction type
R
of SR MOSFET and instantaneous SR current. When
Figure 21. SR Turn-off Algorithm
Adaptive Dead Time Control
ds_on
the drain-to-source voltage reaches the turn-off threshold
voltage V as SR MOSFET current decreases to near
TH_OFF
The stray inductances of the lead frame of SR MOSFET
and PCB pattern induce positive voltage offset across
drain-to-source voltage when SR current decreases. This
makes drain-to-source voltage of SR MOSFET larger than
zero, FAN6248 turns off the gate. If a SR dead time is larger
or smaller than the dead time regulation target t
FAN6248 adaptively changes internal offset voltage to
compensate the dead time. In addition, to prevent cross
conduction SR operation, FAN6248 has 200 ns of turn-on
blocking time just after alternating SR gate is turned off.
,
DEAD
the product of R
and instantaneous SR current, which
ds_on
results in premature turn-off of SR gate. Since the induced
offset voltage changes as load condition changes, the dead
time also changes with load variation. To compensate the
induced offset voltage, FAN6248 has a adaptive virtual
turn-off threshold voltage as shown in Figure 22 with
a combination of variable internal turn-off threshold
SR Turn-off Algorithm
Since a SR turn-off method determines SR conduction
time and stable SR operation, the SR turn-off method is one
of important feature of SR controllers. The SR turn-off
method can be classified into two methods. The first method
uses present information by an instantaneous drain voltage.
This method is widely used and easy to realize, and can
prevent late turn-off. However, it may show premature
turn-off by parasitic stray inductances caused by PCB
pattern and lead frame of SR MOSFET. The second method
predicts SR conduction time by using previous cycle drain
voltage information. Since it can prevent the premature
turn-off, it is good for the system with constant operating
frequency and turn-on time. However, in case of the
frequency varying system, it may lead late turn-off so that
negative current can flow in the secondary side.
voltages V
and V
(2 steps) and modulated
TH_OFF1
TH_OFF2
offset voltage V
(16 steps). The virtual turn-off
offset
threshold voltage can be expressed as:
Virtual VTH_OFF + VTH_OFF * Voffset
(eq. 1)
In FAN6248HC(D) version, if a dead time T
is larger
DEAD
than 280 ns of t
, as shown in Figure 23, V
is
DEAD_H
offset
decreased by one step in next switching cycle. As a result,
the dead time is decreased by increase of virtual V
,
TH_OFF
and becomes close to t
, as shown in Figure 24. If the
DEAD_H
dead time is smaller than t
, the dead time is increased
DEAD_H
by the virtual V
decrease. Thus, the dead time is
TH_OFF
maintained at around t
regardless of parasitic
DEAD_H
To achieve both advantages, FAN6248 adopts mixed type
control method as shown in Figure 21. Basically the
inductances.
instantaneous drain voltage V
is compared with
Drain
V
to turn off SR gate. Then, the offset voltage V
,
TH_OFF
offset
V TH_ON
SR on
which is determined by the product R
and I
, is added
offset
offset
to V
in order to compensate the stray inductance effect
Drain
SR gate
and maintain 280 ns of t
regardless of parasitic
DEAD
S
R
Q
Q
VDrain
inductances. R
is an external resistor in Figure 1 and
offset
I
is an internal modulation current in Figure 2.
offset
SR off
Virtual VTH_OFF
Therefore, FAN6248 can show robust operation with
minimum dead time.
=VTH_OFF −Voffset
Figure 22. Virtual VTH_OFF
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11
FAN6248HC/HD/LC/LD
magnetizing inductance of the transformer is smaller than
ISD_SR
the reflected output voltage. Thus, the secondary side SR
body diode conduction is delayed until the magnetizing
inductor voltage builds up to the reflected output voltage.
However, the primary side switching transition can cause
capacitive current spike and turn on the body diode of SR
MOSFET for a short time as shown in Figure 26, which
induces SR mis-trigger signal. Finally, the SR mis-trigger
makes inversion current in the secondary side. If a proper
algorithm is not provided to prevent the mis-trigger by the
capacitive current spike, severe SR current inversion can
happen.
VDrain
Virtual VTH_OFF
VTH_ON
VGATE_SR
TDEAD > 280 ns
To prevent the SR mis-trigger, FAN6248 has a capacitive
current spike detection method. When SR current inversion
occurs by the mis-trigger signal, the drain sensing voltage of
Figure 23. Premature SR Gate Turn-off
(TDEAD > tDEAD_H
)
SR MOSFET becomes positive. In this condition, if V
DS_SR
ISD_SR
is higher than V
for (T × K ), SR current
SRCOND INV
TH_OFF
inversion is detected. After then, FAN6248 turns off SR
immediately and increases turn-on delay to t
next
ON_DLY2
cycle.
V Drain
Virtual VTH_OFF
VDS_SR
Turn−off trigger is prohibited
during TON_MIN
VTH_HGH
VTH_OFF
V TH_ON
VGATE_SR
VTH_ON
TDEAD 280 ns
9
T
ON_MIN = 25% of TSRCOND of previous cycle
SR conduction time = TSRCOND
Figure 24. Dead Time Control to Maintain
TDEAD 9 tDEAD_H
tON_DLY
TDEAD
VGS.SR
Minimum Turn-on Time
IDS_SR
When SR gate is turned on, there may be severe oscillation
in drain-to-source voltage of SR MOSFET, which results in
several mis-triggering turn-off as shown in Figure 25. To
provide stable SR control without mis-trigger, it is desirable
to have large turn-off blanking time (= minimum turn-on
time) until the drain voltage oscillation attenuates. However,
too large blanking time results in problems at light load
condition where the SR conduction time is shorter than the
minimum turn-on time. To solve this issue, FAN6248 has
adaptive minimum turn-on time where the turn-off blanking
time changes in accordance with the SR conduction time
ISD.SR
Figure 25. Minimum Turn-on Time
IDS_SR
Capacitive current spike
Capacitive current spike
t
VDS_SR
T
measured in previous switching cycle. The SR
SRCOND
VTH_ON
VGATE
conduction time is measured by the time from SR gate rising
edge to the instant when drain sensing voltage V is
DS_SR
VGATE_SR1
VGATE_SR1
higher than V
. From the previous cycle T
TH_HGH
SRCOND
measurement result, the minimum turn-on time is defined by
25% of T
Figure 26. Capacitive Current Spike at Light Load
Condition
.
SRCOND
Capacitive Current Spike Detection
As a result, SR mis-trigger is prevented. To exit the SR
current inversion detection mode, seven consecutive
switching cycles without capacitive current spike are
required.
At heavy load condition, the body diode of SR MOSFET
in LLC resonant converter starts conducting right after the
primary side switching transition takes place. However,
when the resonance capacitor voltage amplitude is not large
enough at light load condition, the voltage across the
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12
FAN6248HC/HD/LC/LD
Virtual VTH_OFF
VTH_OFF2
Light Load Detection (LLD)
To guarantee stable operation under light load condition,
FAN6248 adopts a light load detection function. The
Heavy
Load
VTH_OFF2−ROFFSET x IOFFSET_STEP1
VTH_OFF2−ROFFSET x IOFFSET_STEP2
modulation current I
is mainly used for the adaptive
OFFSET
VTH_OFF2
Range
dead time control. When the output load is heavy,
declines due to large di/dt in the secondary
I
OFFSET_STEP
VTH_OFF2−ROFFSET x IOFFSET_STEP13
side current to maintain 280 ns of t
in FAN6248HC(D).
increases at light load
DEAD
VTH_OFF1
VTH_OFF2−ROFFSET x IOFFSET_STEP15
VTH_OFF1−ROFFSET x IOFFSET_STEP2
On the contrary, I
OFFSET_STEP
condition by small di/dt of SR current. FAN6248 can detect
light load condition by using this I as shown in
VTH_OFF1
Range
OFFSET_STEP
Figure 27. When SR turn-off threshold voltage is V
and the modulation current is higher than I
VTH_OFF1−ROFFSET x IOFFSET_STEP8
LDD Trigger
TH_OFF1
, the
OFFEST_STEP8
light load detection is triggered. In this mode, dead time
target becomes to 320 ns of in
Light
Load
VTH_OFF1−ROFFSET x IOFFSET_STEP14
VTH_OFF1−ROFFSET x IOFFSET_STEP15
t
DEAD_LIGHT
FAN6248HC(D) and 360 ns in FAN6248LC(D) version.
Figure 27. Light Load Detection
Green Mode
When the power supply system operates at very light load
condition, FAN6248 disables SR operation and enters into
green mode operation. Once FAN6248 is in the green mode,
all the major blocks are disabled to minimize the operating
VGATE1
Green Exit
h
= 7 Cycles
CSW_EXT
current. When V
has no switching operation longer
DS_SR
than t
during the burst mode of the primary side
GRN_ENT
VDS_SR1
LLC controller, the green mode is enabled after
of debounce time. After then, FAN6248
t
GRN_ENT_DBNC
exits the green mode when the non−switching time in the
burst mode is less than t or 7 consecutive
switching cycles are detected as shown in Figure 28.
GRN_EXT_H
ISD_SR1
Figure 28. Green Mode Exit
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
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SOIC8
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