FAN6390D [ONSEMI]
Highly Integrated Secondary-Side Adaptive USB Type-C Charging Controller with USB-PD with SR Embedded;
| 型号： | FAN6390D |
| 厂家： | 
ONSEMI |
| 描述： | Highly Integrated Secondary-Side Adaptive USB Type-C Charging Controller with USB-PD with SR Embedded 光电二极管 |
| 文件： | 总25页 (文件大小：635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Highly Integrated Secondary-
Side Adaptive USB Type-C
Charging Controller with
USB-PD with SR Embedded
FAN6390MPX
www.onsemi.com
The FAN6390MPX is a highly integrated, secondary−side power
adaptor controller supporting USB Type−C and USB Power Delivery
2.0/3.0. It includes a fully autonomous USB PD state machine which
is fully compliant with the latest USB PD 3.0 specification,
minimizing design time and cost. Support for the latest Programmable
Power Supply (PPS) rules allows for control of voltages from 3.3 V to
21 V and current limits from 1 A to 3 A to meet a wide range of
applications and power levels.
WQFN24
MLP, QUAD
CASE 510BE
To minimize BOM count, the FAN6390MPX includes internal
synchronous rectifier control, an NMOS gate driver for VBUS load
switch control, as well as Constant Voltage (CV) and Constant Current
(CC) control blocks with adjustable internal references. To ensure
proper operation of the adaptor, various protections are integrated into
the controller including output over−voltage protection, under−
voltage protection, external over−temperature protection via NTC,
internal over−temperature protection, CC over voltage protection and
Cable Fault Protection.
PIN CONNECTIONS
1
CSP
GND
NC
NC
LPC
GND
LGATE
CC1
CC2
GND
BLD
NC
Features
• USB Type−C Rev 1.3 Compatible
• Support 60 W Output Profile
• (PDO: 5 V, 9 V, 15 V, 20 V. APDO: 9 V, 15 V, 20 V)
NC
• Constant Voltage (CV) and Constant Current (CC) Regulation with
Two Operational Amplifiers of Open−Drain Type for Dual−Loop
CV/CC Control
(Bottom View)
• Charge Pump Circuit to Enhance SR Driving Voltage for High
Efficiency
MARKING DIAGRAM
• Small Current Sensing Resistor (5 mW) for High Efficiency
1
6390
• N−Channel Back to Back MOSFET Control as a Load Switch
• Built−in Output Capacitor Bleeding Function for Fast Discharging
FFFB
ALYWG
G
• Precise Voltage & Current Control for Minimum Step Size via 10−bit
6390FFFB = Specific Device Code
DAC’s
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• 10−bit ADC for Monitoring Voltage, Current and Temperature
• Auto Re−start Protection Mode Option to Disable Load Switch for 2
seconds
• Support Protections; Output Over−Voltage Protection, Under−Voltage
Protection, External Over Temperature Protection via NTC, Internal
Over Temperature Protection, Cable Fault Protection, and CC Lines
Over Voltage Protection
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Typical Applications
• Battery Chargers for Smart Phones, Feature Phones, and Tablet PCs
• AC−DC Adapters for Portable Devices that Require CV/CC Control
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
November, 2019 − Rev. 1
FAN6390/D
FAN6390MPX
Transformer
COUT
VBUS
USB Type−C
RSENSE
GND
GND
RX1+
RX1−
VBUS
SBU2
D−
SR
TX1+
TX1−
VBUS
CC1
D+
1
2
4
3
5
6
7
MOSFET
RBLD
9
10
8
VBUS
CC1
VBUS
VIN
GATE
NC
NC
NC LGATE BLD
CSN
RLPC−H
CP
CP
CSP
VREF
IREF
NC
D−
D+
SBU1
VBUS
RX2−
RX2+
GND
CC2
VBUS
TX2−
TX2+
GND
Primary block
CC2
VDD
LPC
NC
FAN6390
QFN4x4
CVDD
VBUS
VBUS
RLPC−L
GND
SFB
GND
GND
NC
CC1
CC2
NTC
Secondary block
Figure 1. Application Schematic
VDD
VIN
LGATE
BLD Block
EN_BLD
VDD
Load switch
driver
RVIN−
BLD
VOUT
IOUT
VIN.INT
LGATE_EN Protection
VCS.AMP
Bleeding Function
Block
ADC
DAC
EXT_TEMP
VIN−ON / VIN−OFF
VNTC.EXT
VDD/LGATE Block
Protection Block
VREF
CC1
CC2
Mode_change VUVP VOVPVCOMR
OVP/UVP/OCP
VCS.AMP
RESET
FAULT
Protection
Trigger_BLD
VCVR
9R
R
IREF
KUVP
VIN.INT
VCCR
Type−C & PD
State machines
VOVP
VUVP
VCDC
KOVP
KCDC
VDD
INTC
Protection
Prt_states
Protections
processing
block
Cable fault
Prt_mode
FAULT
VNTC.EXT
NTC
FAULT
RESET
LGATE_EN
Mode_change
Trigger_BLD
CC_state
CV/CC Control Block
CC_gate
CV_gate
CV_CC_mode
CV_CC_mode
AC_OFF
IREF
Prt_states
Digital Block
VDD
CSN
CSP
CC_gate
X AVCCR
SR Block
VLPC−
EN
Calculate
VLPC−
EN
LGATE_EN
Green Mode
SR GATE
Driver
VCCR
VDD
S
R
Q
PWM
CV_gate
Block
VREF
LPC
VCT
VLPC−
TH
Line
Detection
Function
VCVR
Enable
iCHR
VIN
VRES
iDISCHR
En_RBLD−
Protection
BUS
EN_BLD
AC_OFF
CT
RatioLPC
RatioRES
(1μA/V)
(0.4μA/V)
Cable Fault
Detection
Cable fault
Charge Pump block
CC_state
GND
GND
CP
GATE
SFB
BLD
Figure 2. Block Diagram
ORDERING INFORMATION
†
Part Number
Operating Temperature Range
Package
Packing Method
FAN6390MPXMPX
−40°C to +125°C
24−Lead, MLP, QUAD, JEDEC MO−220,
4 mm × 4 mm, 0.5 mm Pitch, Single DAP
Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
2
FAN6390MPX
1
CSP
GND
NC
NC
LPC
GND
LGATE
CC1
CC2
GND
BLD
NC
NC
Figure 3. Pin Connections (Bottom View)
Table 1. PIN FUNCTION DESCRIPTION(MLP44)
Pin #
Pin Name
NC
Description
1
2
No connection
LPC
SR control input signal. This pin is used to detect the voltage on the secondary winding during the on time
period of the primary MOSFET
3
4
5
GND
LGATE
CC1
Ground
Load switch gate drive signal. This pin is tied to the gate of the load switch
Configuration Channel 1. This pin is used to detect USB Type−C devices and communicate over USB PD
when applicable.
6
7
CC2
VIN
Configuration Channel 2. This pin is used to detect USB Type−C devices and communicate over USB PD
when applicable.
Output voltage (Input voltage to the FAN6390MPX). This pin is tied to the output of the adapter to monitor
its output voltage and supply internal bias.
8
NC
VDD
GATE
CP
No connection
9
Internal supply voltage. This pin is connected to an external capacitor.
10
11
12
13
14
15
16
17
18
Gate drive output. Totem−pole output to drive the external SR MOSFET.
SR gate charge pump
GND
NC
Ground
No connection
NC
No connection
BLD
NC
Bleeder pin. This pin is tied to VBUS after the load switch to discharge VBUS.
No connection
Ground
GND
CSP
Current sensing amplifier positive terminal. Connect this pin directly to the positive end of the current sense
resistor with a short PCB trace.
19
CSN
Current sensing amplifier negative terminal. Connect this pin directly to the negative end of the current
sense resistor with a short PCB trace.
20
21
NTC
SFB
This pin is used for external temperature detection and protection
Secondary Feedback. Common output of the dual OTA open drain operation amplifiers. Typically an opto−
coupler is connected to this pin to provide feedback signal to the primary side PWM controller
22
23
24
IREF
VREF
NC
Constant Current Amplifying Signal. The voltage level on this point is the amplified current sense signal. This
pin is tied to the internal CC loop amplifier’s non−inverting input terminal
Output Voltage Sensing Voltage. This pin is used for CV regulation, and it is tied to the internal CV loop am-
plifier non−inverting input terminal. It is tied to the output voltage resistor divider.
No connection
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3
FAN6390MPX
Table 2. MAXIMUM RATINGS (Notes 1, 2)
Rating
Symbol
Value
−0.3 to 26
−0.3 to 26
−0.3 to 26
−0.3 to 31
−0.3 to 6
−0.3 to 6
−0.3 to 6
−0.3 to 6
−0.3 to 6
−0.3 to 6.5
−0.3 to 6.5
−0.3 to 6
−0.3 to 6
−0.3 to 6
−0.3 to 6.5
0.8644
Unit
V
VIN Pin Input Voltage
SFB Pin Input Voltage
BLD Pin Input Voltage
LGATE Pin Input Voltage
VDD Pin Input Voltage
IREF Pin Input Voltage
VREF Pin Input Voltage
CSP Pin Input Voltage
CSN Pin Input Voltage
LPC pin Input Voltage
GATE Pin Input Voltage
NTC Pin Input Voltage
CC1 Pin Input Voltage
CC2 Pin Input Voltage
CP Pin Input Voltage
V
IN
V
SFB
V
BLD
V
V
V
LGATE
V
V
DD
V
V
IREF
V
V
VREF
V
V
CSP
V
V
CSN
V
V
LPC
V
V
GATE
V
V
V
NTC
CC1
CC2
V
V
V
V
V
CP
V
Power Dissipation (T = 25°C)
P
D
W
°C
°C
°C
kV
kV
A
Operating Junction Temperature
T
J
−40 to 150
−40 to 150
260
Storage Temperature Range
T
STG
Lead Temperature, (Soldering, 10 Seconds)
Human Body Model, ANSI/ESDA/JEDEC JS−001−2012 (Note 3)
Charged Device Model, JESD22−C101 (Note 3)
TL
ESD
2
HBM
CDM
ESD
0.5
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All voltage values, except differential voltages, are given with respect to the GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. Meets JEDEC standards JS−001−2012 and JESD 22−C101.
Table 3. THERMAL CHARACTERISTICS (Note 4)
Rating
Symbol
Value
Unit
Thermal Characteristics,
°C/W
Thermal Resistance, Junction−to−Air
Thermal Reference, Junction−to−Top
R
122
5
q
JA
JT
R
q
4. T = 25°C unless otherwise specified.
A
Table 4. RECOMMENDED OPERATING RANGES
Rating
Symbol
Min
Max
20
5
Unit
V
Input Voltage
V
in
Output Current
I
A
out
Adjustable Output Voltage (Adjustable Version Only)
Ambient Temperature
V
20
80
V
out
T
°C
A
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
FAN6390MPX
Table 5. ELECTRICAL CHARACTERISTICS
V
IN
= 5 V, LPC = 1.25 V, LPC width = 2 ms at T = −40~125°C, F
= 100 kHz, unless otherwise specified.
J
LPC
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VDD SECTION
Turn−On Valid Threshold Voltage
VIN Operating Voltage at 20V
VDD Source Current
VIN SECTION
V
2.6
4.750
10
V
V
DD−valid
V
V
= 20 V, I
= 0 mA
V
DD
5.125
5.500
IN
VDD
= 3.3 V, V = 2.9 V
I
mA
IN
DD
DD
Continuous Operating Voltage
(Note 5)
V
22.5
10
V
IN−OP
Operating Supply Current at 5 V
V
V
= 5 V, V = −25 mV, Rcs = 5 mW
I
IN−OP−5V
mA
mA
IN
CS
Operating Supply Current at 20 V
(Note 5)
= 20 V, V = −25 mV, Rcs = 5 mW
I
8
IN
CS
IN−OP−20V
Turn−On Threshold Voltage
V
V
V
Increases
V
2.9
3.2
3.4
3.005
1.3
V
IN
IN
IN
IN−ON
Turn−Off Threshold Voltage
Decreases after V = V
V
2.805
2.875
V
IN
IN−ON
IN−OFF
Green Mode Operating Supply Current
= 5.2 V (default), V = 0 mV
I
mA
CS
IN−Green
excluding I
and I
P−CC1
P−CC2
VIN−UVP SECTION
Ratio V Under−Voltage−Protection to Whole output mode, V = 0 mV
IN
K
IN−UVP
65
70
75
%
IN
CS
V
CC Mode UVP Debounce Time
t
45
60
75
ms
ms
D−VIN−UVP
UVP Blanking Time during Mode
Change from Lower Vout to Higher
Vout
Whenever does mode change from
lower Vout to higher Vout
t
160
200
240
BNK−UVP
VIN−OVP SECTION
Ratio V Over−Voltage−Protection to Whole output mode, V = 0 mV
IN
K
IN−OVP
116.0
23.5
19
121.5
24.5
127.0
25.5
43
%
V
IN
CS
V
V
IN
Maximum
V
IN−OVP−MAX
Over−Voltage−Protection
OVP Debounce Time
t
31
7
ms
D−OVP
OVP Blanking Time during Mode
Change from Higher Vout to Lower
Vout (Note 5)
Vstep v 0.5 V, Vbus w 13
Disabling OVP & SR Gate.
t
t
t
t
ms
BNK−OVP
BNK−OVP
BNK−OVP
BNK−OVP
OVP Blanking Time during Mode
Change from Higher Vout to Lower
Vout (Note 5)
Vstep v 0.5 V, Vbus < 13
Disabling OVP & SR Gate.
19
56
ms
ms
ms
OVP Blanking Time during Mode
Change from Higher Vout to Lower
Vout (Note 5)
Disabling OVP & SR Gate.
Vstep > 0.5 V, Vbus w 13
OVP Blanking Time during Mode
Change from Higher Vout to Lower
Vout
Disabling OVP & SR Gate.
Vstep > 0.5 V, Vbus < 13
200
CONSTANT CURRENT SENSING SECTION (100% CC)
Current−Sense Amplifier Gain
R
= 5 mW
A
40
V/V
A
CS
V−CCR
(Note 5)
Current threshold on sensing resistor
between CSP and CSN at
VIN = 3.3 V, 5 V, 20 V
I
0.86
1.00
1.14
CS−1.00A
I
= 1.00 A
OUT.CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by Design
www.onsemi.com
5
FAN6390MPX
Table 5. ELECTRICAL CHARACTERISTICS (continued)
= 5 V, LPC = 1.25 V, LPC width = 2 ms at T = −40~125°C, F
V
IN
= 100 kHz, unless otherwise specified.
J
LPC
Parameter
Test Conditions
Symbol
CS−3.00A
CS−STEP
Min
Typ
Max
Unit
CONSTANT CURRENT SENSING SECTION (100% CC)
Current threshold on sensing resistor
between CSP and CSN at
VIN = 3.3 V, 5 V, 20 V
I
I
2.88
3.00
3.12
A
I
= 3.00 A
OUT.CC
Current threshold on sensing resistor
between CSP and CSN at
DI
OTYP
= 50 mA
48
50
52
mA
DI
= 50 mA (Note 5)
OUT.CC
CONSTANT CURRENT SENSING SECTION (107% CC)
Current−Sense Amplifier Gain (Note 5)
R
= 5 mW
A
40
V/V
A
CS
V−CCR
Current threshold on sensing resistor
between CSP and CSN at
VIN = 5 V
I
3.09
3.21
3.33
3.72
CS−3.00A
I
= 3.21 A
OUT.CC
CONSTANT CURRENT SENSING SECTION (120% OCP)
Current−Sense Amplifier Gain (Note 5)
R
= 5 mW
A
40
V/V
A
CS
V−CCR
Current threshold on sensing resistor
between CSP and CSN at
VIN = 3.3 V, 5 V, 20 V
I
3.48
50
3.60
CS−3.0A
I
= 3.60 A
OUT.CC
OCP Debounce Time
T
60
70
ms
OCP−Debounce
OUTPUT CURRENT SENSING SECTION
Current threshold on sensing resistor
between CSP and CSN for enabling
bleeding during mode change
I
450
mA
CS−EN−BLD
Debounce time for enabling bleeding
during mode change
T
1.0
ms
CS−EN−BLD
CONSTANT VOLTAGE SENSING SECTION
Reference Voltage at 3.3 V
V
= 3.3 V, V = 0 V
V
V
0.320
0.485
0.330
0.500
0.340
0.515
V
V
IN
IN
CS
CVR−3.3V
Reference Voltage at 5.0 V
(Power−on reset, default)
V
= 5.0 V, V = 0 V
CS
CVR−5.0V
Reference Voltage at 9 V
V
V
V
= 9 V, V = 0 V
V
0.873
1.455
1.940
1.940
0.900
1.500
2.000
2.000
0.927
1.545
2.060
2.060
V
V
IN
IN
IN
CS
CVR−9V
CVR−15V
CVR−20V
Reference Voltage at 15 V
Reference Voltage at 20 V
Reference Voltage of 20 mV step
= 15 V, V = 0 V
V
V
CS
= 20 V, V = 0 V
V
CS
DV = 20 mV, V = 0 V
V
CVR−STEP−20mV
mV
IN
CS
CABLE DROP COMPENSATION SECTION
Cable Compensation Voltage on V
R
= 5 mW, V = −5 mV
V
COMR−CDC
13.5
2
15.0
16.5
mV
mA
CVR
CS
CS
for V
= 150 mV/A
or R = 10 mW, V = −10 mV
OUT
CS
CS
FEEDBACK SECTION
SFB Pin Maximum Sink Current
BLEEDER SECTION
I
SFB−Sink−MAX
VBUS Leakage Impedance (Note 5)
R
100
300
171
242
kW
BLD−BUS
VIN Pin Sink Current when Bleeding
(Note 5)
Bleeding current on VIN at VIN = 20 V
Bleeding current on BLD at VIN = 20 V
I
mA
VIN –Sink
BLD Pin Sink Current when Bleeding
(Note 5)
I
250
mA
ms
BLD –Sink
Enable Bleeder Time (Note 5)
Disabling OVP & SR Gate.
Vstep ≤ 0.5 V, Vbus ≥ 13
t
7
BLD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by Design
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6
FAN6390MPX
Table 5. ELECTRICAL CHARACTERISTICS (continued)
= 5 V, LPC = 1.25 V, LPC width = 2 ms at T = −40~125°C, F
V
IN
= 100 kHz, unless otherwise specified.
J
LPC
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
BLEEDER SECTION
Enable Bleeder Time (Note 5)
Disabling OVP & SR Gate.
t
t
t
19
56
ms
ms
ms
BLD
BLD
BLD
Vstep ≤ 0.5 V, Vbus < 13
Enable Bleeder Time (Note 5)
Enable Bleeder Time
Disabling OVP & SR Gate.
Vstep > 0.5 V, Vbus ≥ 13
Disabling OVP & SR Gate.
Vstep > 0.5 V, Vbus < 13
160
55
200
240
65
OVER TEMPERATURE PROTECTION SECTION
Current Source on NTC pin
R
= 3.293 kW
I
60
mA
par_110
NTC
Debounce Time for Over Temperature
Protection (Note 5)
T
77.5
ms
NTC−Debounce
CABLE PROTECTION SECTION
Delay Time Enabling Pollution
t
9
10
11
ms
POL−EN−Delay
Detection after Rd is Detached or after
Load Switch is Disabled (Note 5)
Debounce Time for Pollution Detection
(Note 5)
V
> V
t
45
9
50
10
55
11
ms
ms
mA
V
BLD
POL−TH
POL−Debounce
Bleeder Enable Time for Pollution
Detection (Note 5)
t
BLD−POL
Pollution Detection Current on BLD
Pin (Note 5)
I
350
0.67
0.50
390
0.74
0.60
450
0.80
0.65
2
POL−DET
Supply Voltage of Pollution Detection
Current (Note 5)
V
SUP−POL−DET
Pollution Detection Threshold Level
(Note 5)
During t
BLD
with open−circuited on
V
V
POL−EN
POL−TH
Guaranteed Pollution Impedance
(Note 5)
R
kW
POL
PROTECTION OPERATION SPECIFICATION SECTION
Output Voltage Releasing Latch Mode
(Note 5)
V
IN
< V , at −5°C and 85°C
LATCH−OFF
V
1.55
V
s
LATCH−OFF
Time Duration Disabling Load Switch
(Note 5)
t
2
TwoSecondAR.
TYPE−C SECTION
330 mA Source Current on CC1 Pin
330 mA Source Current on CC2 Pin
Input Impedance on CC1 Pin
Input Impedance on CC2 Pin
V
V
V
V
V
= 5 V, V
= 5 V, V
= 0 V
I
I
302
302
126
126
2.45
330
330
358
358
mA
mA
kW
kW
V
IN
IN
IN
IN
IN
CC1
P−CC1−330
= 0 V
CC2
P−CC2−330
= 0 V, Sourcing 330 mA on CC1
= 0 V, Sourcing 330 mA on CC2
Z
Z
OPEN−CC1
OPEN−CC2
Rd Impedance Detection Threshold on
CC1 Pin
= 5 V, V
= 0 V, Increasing V
= 0 V, Increasing V
= 0 V, Increasing V
V
2.60
2.60
150
2.75
2.75
200
CC2
CC1
CC2
CC1
CC2
CC1
RD−CC1
RD−CC2
Rd Impedance Detection Threshold on
CC2 Pin
V
IN
= 5 V, V
V
2.45
V
UFP Attachment Debounce Time
Gate High Voltage at 3.3 V
Gate High Voltage at 20 V
V
IN
V
IN
V
IN
V
IN
= 5 V, V
= 3.3 V
= 20 V
t
100
5.3
ms
V
CCDebounce
V
LGATE−3.3V
V
23.5
V
LGATE-20V
LGATE−OVP−Max
Gate High Voltage at V
= V
V
31
V
IN−OVP−Max
IN−OVP−Max
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by Design
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7
FAN6390MPX
Table 5. ELECTRICAL CHARACTERISTICS (continued)
V
IN
= 5 V, LPC = 1.25 V, LPC width = 2 ms at T = −40~125°C, F
= 100 kHz, unless otherwise specified.
J
LPC
Parameter
TYPE−C SECTION
CC Pin Over−Voltage Protection
Test Conditions
Symbol
Min
Typ
Max
Unit
V
5.5
5.5
5.75
5.75
6
6
V
V
1
CC1−OVP
V
CC2−OVP
CC Pin Over−Voltage Protection
2
CC /CC OVP Debounce Time
t
CC-OVP−Debounce
100
0.80
ms
V
1
2
Safe Operating Voltage at 0 V
OUTPUT DRIVER SECTION
Output Voltage Low
V
safe0V
0.66
4.0
0.73
V
V
= 5 V, I
= 100 mA
V
OL
0.25
V
V
V
IN
GATE
Output Voltage High
= 3.3 V, C = 4.7 nF, C = 4.7 nF
V
OH
IN
iss
p
VIN Threshold to Enable Charge
Pump (Note 5)
V
4.2
63
63
44
30
1.4
CP−EN
Rising Time (Note 5)
V
IN
= 5 V, C = 4.7 nF, C = 4.7 nF
t
R
ns
ns
ns
ns
ms
iss
p
GATE = 1 V ~ 4 V
Falling Time (Note 5)
V
IN
= 5 V, C = 4.7 nF, C = 4.7 nF
t
F
iss
p
GATE = 4 V~ 1 V
Propagation Delay to OUT High
(LPC Trigger (Note 5)
V
=5 V, GATE=1 V
t
PD−HIGH−LPC
IN
IN
Propagation Delay to OUT Low
(LPC Trigger (Note 5)
V
= 5 V, GATE = 4 V
t
PD−LOW−LPC
Gate Inhibit Time (Note 5)
INTERNAL RES SECTION
Internal RES Ratio (Note 5)
t
INHIBIT
V
IN
= V
~20 V (N = 6.5~7.5)
K
RES
0.110
70
V/V
%
IN−OFF
VIN Dropping Protection Ratio with
Two Cycle
LPC Width = 5 ms, V =5 V to 3.5 V
K
60
1
80
3
IN
VIN−DROP
Debounce time for noise immunity on
VIN (Note 5)
t
2
ms
VIN−Debounce
Debounce Time for Disable SR when
VIN Dropping Protection
t
0
6.5
13
ms
SR_OFF
LPC SECTION
Linear Operation Range of LPC Pin
Voltage (Note 5)
V
< V v 5 V
V
LPC
0.4
3.6
V
IN –OFF
IN
SR Enabled Threshold Voltage
V
V
=
V
0.942
1.061
1.245
1.397
0.442
0.561
0.741
1.069
1.196
1.433
1.554
0.496
0.584
0.817
1.197
1.332
1.541
1.712
0.550
0.685
0.893
LPC−HIGH−H−5V
LPC−TH−H−5V
LPC−HIGH−H−5V
V
LPC−HIGH−H−9V
V
V
V
V
V
V
V
@High−Line
/ 0.875
SR Enabled Threshold Voltage
@High−Line
V
V
=
LPC−HIGH−H−9V
LPC−TH−H−9V
/ 0.875
SR Enabled Threshold Voltage
@High−Line
V
= V
= V
V
V
LPC−HIGH−H−15V
LPC−TH−
LPC−HIGH−H−15V
LPC−HIGH−H−20V
/ 0.875
H−15V
SR Enabled Threshold Voltage
@High−Line
V
LPC−HIGH−H−20V
LPC−TH−
/ 0.875
H−20V
SR Enabled Threshold Voltage @
Low−Line
V
= V
= V
V
LPC−HIGH−L−5V
LPC−TH−
LPC−HIGH−L−5V
LPC−HIGH−L−9V
V
LPC−HIGH−L−15V
/ 0.875
L−5V
SR Enabled Threshold Voltage @
Low−Line
V
V
LPC−HIGH−L−9V
LPC−TH−
/ 0.875
L−9V
SR Enabled Threshold Voltage @
Low−Line
V
= V
LPC−HIGH−L−15V
LPC−TH−
/ 0.875
L−15V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by Design
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8
FAN6390MPX
Table 5. ELECTRICAL CHARACTERISTICS (continued)
V
IN
= 5 V, LPC = 1.25 V, LPC width = 2 ms at T = −40~125°C, F
= 100 kHz, unless otherwise specified.
J
LPC
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
LPC SECTION
SR Enabled Threshold Voltage @
V
L−12V
= V
V
0.897
1.46
1.37
0.981
1.60
1.50
0.1
1.065
1.74
1.63
LPC−HIGH−L−12V
LPC−TH−
LPC−HIGH−L−20V
V
V
Low−Line
/ 0.875
Low−to−High Line Threshold Voltage
on LPC Pin
Spec. = (0.70 + 0.02 * V ) * 2,
V
LINE−H−5V
IN
V
IN
= 5 V
High−to−Low Line Threshold Voltage
on LPC Pin
Spec. = (0.65 + 0.02 * V ) * 2,
V
LINE−L−5V
IN
V
V
V
IN
= 5 V
Line Change Threshold Hysteresis
(Note 5)
V
V
=
– V
V
LINE−HYS−5V
LINE−HYS−5V
LINE−H−5V
LINE−L−5V
Low−to−High Line Threshold Voltage
Spec. = (0.70 + 0.02 * V ) * 2,
IN
V
1.62
1.53
1.76
1.66
0.1
1.90
1.79
V
V
V
V
V
V
V
V
V
IN
LINE−H−9V
V
LINE−L−9V
on LPC Pin
V
= 9 V
High−to−Low Line Threshold Voltage
on LPC Pin
Spec. = (0.65 + 0.02 * V ) * 2,
IN
V
IN
= 9 V
Line Change Threshold Hysteresis
(Note 5)
V
V
=
V
LINE−HYS−9V
LINE−HYS−9V
LINE−H−9V
– V
LINE−L−9V
Low–to−High Line Threshold Voltage
on LPC Pin
Spec. = (0.70 + 0.02 * V ) * 2,
V
1.85
1.76
2.00
1.90
0.1
2.15
2.04
IN
LINE−H−15V
V
IN
= 15 V
High−to−Low Line Threshold Voltage
on LPC Pin
Spec. = (0.65 + 0.02 * V ) * 2,
V
LINE−L−15V
IN
V
IN
= 15 V
Line Change Threshold Hysteresis
(Note 5)
V
V
=
V
LINE−HYS−15V
LINE−HYS−15V
LINE−H−15V
– V
LINE−L−15V
Low–to−High Line Threshold Voltage
on LPC Pin
Spec. = (0.70 + 0.02 * V ) * 2,
V
2.06
1.97
2.20
2.10
0.1
2.34
2.23
IN
LINE−H−20V
V
IN
= 20 V
High−to−Low Line Threshold Voltage
on LPC Pin
Spec. = (0.65 + 0.02 * V ) * 2,
V
LINE−L−20V
IN
V
IN
= 20 V
Line Change Threshold Hysteresis
(Note 5)
V
V
=
V
V
LINE−HYS−12V
LINE−H−20V
LINE−HYS−20V
– V
LINE−L−20V
Higher Clamp Voltage
5.4
6.2
7.0
29
V
V
LPC−CLAMP−H
LPC Threshold Voltage to Disable SR
Gate Switching
V
IN
= 5 V. LPC = 3 V°
V
V
–
LPC−DIS
IN
0.6
Line Change Debounce Time from
Low−Line to High−Line
Counts for LPC falling < V
t
t
13
21
15
ms
LPC−TH−L−5V
LPC−LH−debounce
−time
Line Change Debounce from
High−Line to Low−Line (Note 5)
ms
LPC−HL−debounce
INTERNAL TIMING SECTION
Ratio between V
& V
V
= 5 V, F
= 50 kHz, K
= 0.11
Ratio
5.40
210
5.68
285
5.96
360
LPC
RES
IN
LPC
RES
LPC−RES
Minimum LPC Time to Enable the SR
Gate @ High−Line
V
= 2.5 V
t
ns
ns
LPC
LPC−EN−H
Minimum LPC Time to Enable the SR
Gate @ Low−Line
V
LPC
= 1.25 V
t
540
705
870
LPC−EN−L
REVERSE CURRENT MODE SECTION
Reverse Current Mode Entry
Debounce Time
V
V
= 5 V, V
= 5 V, V
= 0 V
= 0 V
T
270
400
530
2.4
ms
IN
LPC
reverse−debounce
Operating Current during Reverse
Current Mode
I
mA
IN
LPC
OP.reverse
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by Design
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9
FAN6390MPX
Table 5. ELECTRICAL CHARACTERISTICS (continued)
= 5 V, LPC = 1.25 V, LPC width = 2 ms at T = −40~125°C, F
V
IN
= 100 kHz, unless otherwise specified.
J
LPC
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
BMC TRANSMITTER NORMATIVE REQUIREMENTS
Unit Internal
1/fBitRate
t
3.03
300
300
33
3.33
500
500
3.70
700
700
75
ms
ns
ns
W
UI
t
Rise−TX
Rise Time
C
C
= 4.7 F
VDD
VDD
Fall Time
= 4.7 mF
t
Fall−TX
Transmitter Output Impedance
Transmitter output impedance at
Niquist frequency of USB2.0 low speed
(750 kHz) while Source driving the CC
line
zDriver
Transitions for Signal Detect
n
3
TransitionCount
Time Window for Detecting Non−idle
t
12
20
ms
TransitionWindow
Rx bandwidth Limiting Filter
(Digital or Analog)
t
100
ns
RxFilter
Receiver Input Impedance
zBmcRx
1
MW
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by Design
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10
FAN6390MPX
TYPICAL CHARACTERISTICS
Figure 4. VCVR−3.3V vs. Temperature
Figure 5. VCVR−5V vs. Temperature
Figure 7. VCVR−15V vs. Temperature
Figure 9. VCVR−STEP−20mV vs. Temperature
Figure 6. VCVR−9V vs. Temperature
Figure 8. VCVR−20V vs. Temperature
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11
FAN6390MPX
TYPICAL CHARACTERISTICS (Continued)
Figure 10. IIN−OP−5V vs. Temperature
Figure 11. VIN−OFF vs. Temperature
Figure 13. KIN−UVP vs. Temperature
Figure 15. VIN−OVP−MAX vs. Temperature
Figure 12. IIN−Green vs. Temperature
Figure 14. KIN−OVP vs. Temperature
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12
FAN6390MPX
TYPICAL CHARACTERISTICS (Continued)
Figure 16. VDD vs. Temperature
Figure 17. VLGATE−3.3V vs. Temperature
Figure 18. ICS−1.00A at VIN = 20 V vs.
Temperature
Figure 19. ICS−3.00A at VIN = 20 V vs.
Temperature
Figure 20. ICS−1.00A at VIN = 3.3 V vs.
Temperature
Figure 21. ICS−3.00A at VIN = 3.3 V vs.
Temperature
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13
FAN6390MPX
TYPICAL CHARACTERISTICS (Continued)
Figure 22. VCC1−OVP vs. Temperature
Figure 23. VCC2−OVP vs. Temperature
Figure 24. tCC−OVP−Debounce vs. Temperature
Figure 25. Vsafe0V vs. Temperature
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14
FAN6390MPX
APPLICATIONS INFORMATION
FAN6390MPX state machine based offers several kinds of trim option to enhance design flexibility as Table 6 shows.
Table 6. SUMMARY TABLE OF ALL KINDS OF TRIM FUNCTION
Function
All Trims
FAN6390MPXMPX Trim
Cable Fault (Note 6)
0: Disabled
1: Enabled
“1” is selected.
“0” is for compliance box test.
Internal RES
ratio= 1/Ratio
00: 0.14 (for N /N = 7.5~10)
P S
“10” is selected.
01: 0.18 (for N /N = 9.5~13)
RRES
P S
10: 0.11 (for N /N = 6.5~7.5)
P
S
11: 0.10 (for N /N = 5~6.5)
P
S
Note: N and N are primary and
P
S
secondary transformer turns
Cable Compensation
for PDO
00: 150 mV/A
01: 50 mV/A
10: 100 mV/A
11: Disabled
“00” is selected.
“11” is used for PD compliance box test that additional cable
compensation on DFP is no need.
Current Sensing
1: 10 mW
0: 5 mW
“0” is selected. (Smaller current sensing resistor has better
efficiency but could be more expensive. In order to trade off
cost and efficiency for flexible design, two kinds of popular
current sensing resistors are provided. )
Support PD2.0 or 3.0
Default 5 V Adjustment
0: Enable PD2.0
1: Enable PD3.0
“1” is selected. (FAN6390MPX series support only PDO
power profile via PD2.0 trim and PDO plus APDO(PPS)
power profile via PD3.0 trim.)
0: 5.0 V
1: 5.2 V
“0” is selected. (Two kinds of default 5 V adjustment for
flexible design)
Adjustable Output
Profile
8 kinds of output power profile can be se-
lectable as list1.
“000” is selected.
“0” is selected.
“00” is selected.
Protection Modes
(Note 6)
0: Auto−restart after 2sec
1: Latch protection. System re−start up
Output OVP
PDO case and PPS case
00: 120%
01: 125%
10: 130%
11: 115%
Output UVP (Note 7)
PDO case:
00: 65%
“10” is selected.
01: 60%
10: 70%
11: Disable
PPS case:
disable
PDO Current Mode
(Note 8)
00: 5 V (107% CC), 9/15/20 V (120 % CC)
01: 5/9/15/20 V (107% CC)
10: 5/9/15/20 V (120% CC)
“00” is selected.
“10” is used for PD compliance box test.
Output Power
Output power range from 15 W~60 W
“111111” is selected.
000000: 15 W
000001: 16 W
...
111111: 60 W
6. Function explanation refers to FAN6390MPX application note.
7. Based on compliance spec PPS case is current limit. Output voltage could be lower than the requested PPS voltage command during current
limit. In order to operate at current limit region, FAN6390MPX series disable UVP and operates until V
8. Except of PDO, all APDO power profiles are 100% CC.
.
IN−OFF
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15
FAN6390MPX
Table 7. UP TO 8 KINDS OF OUTPUT POWER PROFILES SELECTED BY TRIM
Output Profile Trim
15 W 3 P 3 27 W
27 W < P 3 45 W
45 W < P 3 60 W
Power Profile Trim
000
• 5 V
• 9 V
• 5 V
• 9 V
• 5 V
• 9 V
• 12 V (Note 9)
If PD3.0 trim activated
• PPS 5 V
• 12 V
• 15 V
If PD3.0 trim activated
• PPS 5 V
• 15 V
• 20 V
If PD3.0 trim activated
• PPS 9 V
• PPS 9 V
• PPS 9 V
• PPS 15 V
• PPS 15 V
• PPS 20 V
001
010
• 5 V
• 5 V
• 5 V
• 5.5 V
• 6.0 V
• 7.0 V
• 8.0 V
• 9 V
• 5.5 V
• 6.0 V
• 7.0 V
• 8.0 V
• 9 V
• 5.5 V
• 6.0 V
• 7.0 V
• 9 V
• 15 V
• 20 V
• 10.0 V
• 15 V
• 5 V
• 5 V
• 5 V
• 6.0 V
• 7.0 V
• 8.0 V
• 9 V
• 6.0 V
• 7.0 V
• 9 V
• 6.0 V
• 9 V
• 15 V
• 20 V
• 15 V
If PD3.0 trim activated
• PPS 5 V
• PPS 9 V
If PD3.0 trim activated
• PPS 9 V
• PPS 15 V
If PD3.0 trim activated
• PPS 15 V
• PPS 20 V
011
100
• 5 V
• 5 V
• 5 V
• 5.5 V
• 6.0 V
• 6.5 V
• 7.0 V
• 8.0 V
• 9 V
• 5.5 V
• 6.0 V
• 6.5 V
• 7.0 V
• 9 V
• 5.5 V
• 6.0 V
• 6.5 V
• 9 V
• 15 V
• 20 V
• 15 V
• 5 V
• 5 V
• 5 V
• 5.6 V
• 9 V
• 11 V
• 5.6 V
• 9 V
• 11 V
• 15 V
• 5.6 V
• 9 V
• 11 V
• 15 V
• 20 V
101
110
111
• 5 V
• 9 V
• 14.5 V
• 5 V
• 9 V
• 14.5 V
• 15 V
• 5 V
• 9 V
• 14.5 V
• 15 V
• 20 V
• 5 V
• 9 V
• 11 V
• 5 V
• 9 V
• 11 V
• 15 V
• 5 V
• 9 V
• 11 V
• 15 V
• 20 V
• 5 V
• 9 V
• 15 V
• 20 V
9. 12 V can be possible to enable or disable by trim.
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16
FAN6390MPX
USB Type−C Support
The USB Type−C specification defines CC lines (CC1
and CC2) to detect the orientation and roles of a USB Port
pair (Source and Sink roles). A source device will provide
pull−up currents on the CC lines and the sink will provide a
pull−down resistance in order to allow detection of the other
when the two are attached. When there is no device attached
to either the source or sink device, VBUS must not be
powered and should be under 0.8 V (Max). The
FAN6390MPX operates as a source−only device and
provides control of an NMOS load switch to isolate VIN
from VBUS to ensure that VBUS can be discharged
completely when required.
Load switch
USB Type−C cable
VBUS
Sink device
VBUS
DC power
VIN
BLD
LGATE
VDD
VDD
Sink cotroller
ICC 1
CC1
CC2
CC1
CC2
CC1
CC2
CC1
Type−C & PD
State machines
Rd
Rd
Sink CC detection
ICC 2
CC2
Source cotroller
GND
GND
Figure 26. Source Only Device Connecting to Sink Device through Type C Cable
IP−CC1 & IP−CC2
Figure 26 shows a USB Source connected to a USB Sink
with a USB Type−C cable. Since there is only one CC signal
in a standard USB Type−C cable, one of pull−ups in the USB
t
t
t
t
t
t
CC1
VDD
VRd
FAN 6390 attaches to
sink via typeC cable
Source (I
and I
) will be terminated with the Rd
p−CC1
p−CC2
to ground in the USB Sink, causing a fixed voltage to be
developed across the 5.1 kW pull−down. The
FAN6390MPX monitors the CC line voltages to decide if a
Sink is attached or not and the orientation of the USB
CC2
VDD
VRd
Type−C cable. If the V voltage is within the attach
Rd
LGATE
threshold for t
according to the thresholds
CCDebounce
tCCDebounce
defined in Table 8, the load switch will be enabled to provide
vSafe5V on VBUS. The FAN6390MPX advertises support
for 3 A current at the vSafe5V output voltage level.
VBUS
5V
0V
VIN
Table 8. CC VOLTAGES ON SOURCE SIDE –
3.0 A @ 5 V
5V
Detection
Min Voltage
0.85 V
Max Voltage
Threshold
Figure 27. Attach to Sink Device via USB Type−C
Sink (vRd)
2.45 V
2.60 V
Cable
No Connect
(vOPEN)
2.75 V
USB PD Support
USB Power Delivery (PD) provides a way for a Source
and Sink device to negotiate output power settings, allowing
for increased power delivery up to 100W. USB PD uses the
CC signal that is passed through the USB cable to provide
the link between a Source device and a Sink device. In order
to communicate properly over the CC signal, all USB
PD−capable devices include four major communication
components, the Physical Layer, Protocol Layer, Policy
Engine and Device Policy Manager as shown in Figure 28.
Figure 27 shows the signal levels and timing for a typical
USB Type−C attach on CC1. The Source pull−up currents
are enabled on both CC1 and CC2 and the USB cable
connects the Rd resistor on the CC1 signal in the Sink device
which pulls down the CC1 voltage into the vRd range. Once
the FAN6390MPX detects the voltage on CC1 within the
vRd range for t
, the load switch is enabled and
CCDebounce
vSafe5V is applied on VBUS.
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17
FAN6390MPX
Source
Sink
be programmatically adjusted over the advertised voltage
Device Policy
Device Policy
Manager
range (Programmable Power Supply or PPS). A Source can
advertise a combination of PDO’s and APDO’s, up to
a maximum of 7 total Data Objects. In order to provide
a consistent experience across Source devices with the same
power rating (PDP), a set of Power Rules was introduced
into the USB PD 3.0 specification. The Power Rules provide
a set of minimum requirements (PDO’s and APDO’s) that
must be met for a Source device based on the advertised
PDP.
Manager
Policy Engine
Policy Engine
Protocol Layer
Physical Layer
Protocol Layer
Physical Layer
The FAN6390MPX can be configured to meet a variety of
different USB PD Power Profiles, depending on the
application requirements. The default power profile option
for the FAN6390MPX is the standard 60W option as shown
in Table 9.
CC Signal
Figure 28. USB PD Communications Stack
The Physical Layer handles the transmission and
reception of the bits on the CC signal. All data is first
encoded using a 4b5b line code and then transmitted across
the CC signal using Biphase Mark Coding (BMC). A 32−bit
CRC is also used to protect the data integrity of the data
payload.
The Protocol Layer defines how USB PD messages are
constructed and used between a Source device and a Sink
device. All USB PD messages must follow a strict packet
definition and may also include timing requirements based
on the type of message. The Protocol Layer is responsible
for verifying the timing parameters and handling any
communication errors as they arise.
Table 9. FAN6390MPX DEFAULT POWER PROFILE
Max
Data
Output
Current
Current
Object
Voltage
Mode
w/3 A Cable
PDO1
PDO2
PDO3
PDO4
APDO1
5 V
9 V
3.21 A
3.6 A
3.6 A
3.6 A
3 A
OC
OCP
OCP
OCP
CC
15 V
20 V
9 V
(3.3~11 V)
The Policy Engine is responsible for executing the device
Local Policy to control its power delivery behavior. The
Policy Engine defines a set of message sequences that must
be followed for proper operation. All power negotiations are
handled by the Policy Engine.
APDO2
APDO3
15 V
3 A
3 A
CC
CC
(3.3~16 V)
20 V
(3.3~21 V)
The Device Policy Manager is responsible for overseeing
the power supply and managing changes to the Local Policy,
including handling of alert and fault conditions. It is also
responsible for the Discover Identity messaging to
determine the full capabilities of the cabling.
The FAN6390MPX implements all four components of
the Source communication stack in hardware to provide
a USB PD 3.0 fully−compliant solution without the need for
firmware interaction. Control of the Constant Voltage and
Constant Current DAC’s is integrated into the Policy Engine
to provide seamless power transitions between different
contracts.
Constant Voltage Control
In order to regulate adaptive output voltages, the constant
voltage control (CV) is implemented. The output voltage is
sensed through an external resistor divider. The sensed
output voltage is connected to the VREF pin, and it is input
the non−inverting input terminal of the internal operational
amplifier. The inverting input terminal is connected to the
internal voltage reference (V
) which can be adjusted
CVR
according to the requested output voltage. The amplifier and
an internal switch operate as a shunt regulator, and the output
of the shunt regulator is connected to the external
opto−coupler via SFB pin. To compensate output voltage
regulation, typically, two capacitors and one resistor are
connected between SFB and VREF pins as Figure 29. The
output voltage can be derived as calculated by the
Equation 1, and the ratio of the resistor divider is 10. The
reference (VCVR) for the output voltage is generated by
a 10−bit DAC. The minimum resolution is 20 mV to meet
PD3.0 compliance spec.
USB PD Power Profiles
The USB PD 3.0 specification defines Power Data
Objects (PDO) and Augmented Power Data Objects
(APDO) as a way for the Source device to advertise its’
power capabilities. Power Data Objects are used to describe
well−regulated fixed voltage supplies, poorly regulated
power supplies and battery supplies that can be directly
connected to VBUS. Augmented Power Data Objects are
used to describe a power supply whose output voltage can
R
F1 ) RF2
V
O + VCVR
@
(eq. 1)
RF2
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18
FAN6390MPX
Output Over−Current Protection
+
Over−Current Protection (OCP) is enabled during USB
PD contracts. When OCP mode is enabled the supply will
regulate the output voltage until the load current exceeds the
OCP threshold, at which point it will cause a fault condition
and disable the output voltage as shown in Figure 31. Same
as Constant Current Limit Mode, the FAN6390MPX detects
Vbus
RCS
−
CSN
CSP
FB
0
1
PDO or APDO
LGATE
IREF
the output current via the current−sense resistor R , with
CS
0:OCP/ 1:CC
the difference being the output of the CC amplifier
disconnected from the SFB signal. When the load current
SFB
exceeds the OCP threshold for longer than t
Over−Current Protection is triggered and the
, Output
D−OCP
VCCR
RF1
VREF
FAN6390MPX enters Auto Restart Mode.
RF2
OCP
debounce
VCVR
VBUS
ß
OCP “HIGH”
Figure 29. Voltage and Current Sensing Circuits
à
Point A
OCP
PDO
Voltage
Constant Current Control
Constant current (CC) control is enabled during USB PD
contracts. When CC mode is enabled, the supply will
foldback the output voltage as the load increases in order to
maintain a fixed output current as shown in Figure 30.
Output current is sensed via a current−sense resistor RCS,
which is connected between the CSP and CSN pins. The
sensed signal is internally amplified, and this amplified
voltage is connected to the non−inverting input of the
internal operational amplifier. Similar to the constant
voltage amplifier circuit, it also plays a role as a shunt
regulator to regulate the constant output current. In order to
compensate output current regulation, one capacitor and one
resistor are connected between the IREF and SFB pins as
shown in Figure 29. The constant output current can be
calculated using Equation 2. 5mW is typically used for the
sense resistor.
I
IA = 120% Max PDO Current
Figure 31. PDO OCP Operation Example
Green Mode Operation
The FAN6390MPX implements green mode operation in
order to reduce power consumption during light−load
conditions. Green Mode is enabled when there is no valid
Sink attached to the Type−C port. During Green Mode
operation the Synchronous Rectifier and other block are
disabled, reducing the operating current to I
. Green
IN−Green
Mode operation is disabled when there is valid Type−C Sink
device attached.
VCCR
RCS
1
AV*CCR
IO_CC
+
(eq. 2)
Since the voltage across the CSP and CSN pins is small,
the sensing resistor should be positioned as close as possible
to the pins. An RC filter can be added to the pins to reduce
the noise seen on the circuit.
VBUS
APDO
Voltage
à
Point A Enter CC
à
Point B UVP
VIN−OFF
I
IA=100% APDO Current
Figure 30. APDO CC Operation
www.onsemi.com
19
FAN6390MPX
Device Protections and Auto Restart Operation
Normal Operation
The FAN6390MPX provides Output Over−Voltage
Protection, Under−Voltage Protection, Output Over Current
Protection, External Over Temperature Protection via NTC,
internal Over Temperature Protection, Cable Fault
Protection and CC line Over Voltage Protection. When
a protection mode is triggered, the load switch is disabled
and the VIN and BLD bleeder circuits are enabled to protect
the Sink device. During this time, the CC pull−up currents
N
Cable
detached
Y
(I
and I
) are disabled to indicate to the Sink
p−cc1−330
p−cc2−330
device that the Source is not ready to provide power. The
functionality described is shown in Figure 33. Once the fault
conditions are removed, the FAN6390MPX will re−enable
the VIN bleeder circuit and begin the auto−restart timer
Enter Green Mode
Cable
attached
N
Y
(t
). After the auto−restart timer expires, the CC
TwoSecondAR
pull−up currents will be enabled to allow a Sink device to
attach as shown in Figure 34.
Exist Green Mode
Figure 32. Green Mode Operation
Bleeder Functionality
COUT
Cbus
VBUS
RCS
Bleeder circuits are implemented on the VIN and BLD
pins to discharge the output capacitors quickly during mode
transitions and to fully discharge VBUS when required. The
bleeder circuits in the FAN6390MPX are sized to meet the
timing requirements in the USB PD 3.0 specification. Since
the output load can discharge the load sufficiently during
heavy loads, the bleeder circuits are only enabled during
BLD
LGATE
VIN
VDD
Ip−cc1
CC1
CC2
VDD
Ip−cc2
Protection
control
block
light load conditions (I < I
), The operation of
OVP/UVP/OTP/NTC/OCP/CCOVP/CFP
CS
CS-EN-BLD
the bleeder circuits is shown in Tables 10, 11 and 12.
Figure 33. Protection Block Diagram
Table 10. MODE TRANSITION BLEEDER OPERATION
Step
Size
New
VBUS
t
BLD
VIN
BLD
Protection
(typ)
Bleeder Bleeder
LGATE
Trigger
Release
≤0.5V
≥13V
<13V
≥13V
<13V
7ms
Enabled Disabled Enabled
Load
SW
tCCDebounce
19ms
56ms
224ms
>0.5V
IP−CC1&IP−CC2
Bleeder
@VBUS
tTwoSecondAR
Table 11. DETACH & HARD RESET BLEEDER
OPERATION
tBLD
tBLD
Bleeder
@VIN
tBLD
tBLD
While
VBUS
Final
VBUS
t
BLD
bleed
VIN
bleed
BLD
(typ)
LGATE
time
Figure 34. Auto Restart Mode Operation
>vSafe5V vSafe5V 224ms Enabled Disabled Enabled
≤vSafe5V vSafe0V Enabled Disabled
Output Over−Voltage Protection
Over Voltage Protection (OVP) protects the system of any
unexpected high voltage on the VBUS terminals. An OVP
fault is triggered when the output voltage exceeds the OVP
Table 12. PROTECTION MODE BLEEDER OPERATION
Final
t
BLD
VIN
BLD
VBUS
(typ)
bleed
bleed
Condition
LGATE
threshold for longer than t . Since the output voltage
D−OVP
can change with different USB PD requests, the OVP
thresholds will move with the selected contact as shown in
Standard vSafe0V 224ms Enabled Enabled Disabled
Protection
www.onsemi.com
20
FAN6390MPX
VBUS short and keep
short
VBUS
Table 13. In order to avoid mis−triggering an OVP condition
during voltage transitions, the OVP circuitry is blanked for
VIN
VVIN_UVP
VIN_OFF
t
V
. The maximum OVP threshold is limited to
regardless of the settings in the table to
BLK−OVP
VLATCH _OFF
LoadSW
IN−OVP−MAX
ensure the voltages stay within the operating range of the
FAN6390MPX.
tCCDebounce
ICC1 or ICC2
Bleeder
@VBUS
Table 13. OVER−VOLTAGE PROTECTION
THRESHOLD
Bleeder
@VIN
Protocol
PD2.0
PDO or APDO
All PDOs
OVP Threshold
VIN bleeding until touch
Pri V DD
to V LATCH
_OFF
VDD_OFF
VDD_HV_ON
K
*PDO
IN−OVP
After
2 times repeat
PD3.0
All APDOs
K
*APDO
Pri
switching
IN−OVP
Trigger UVP @ primary
time
Figure 36. Under Voltage Lockout(UVLO)
External Over Temperature Protection
CVIN
Cbus
VBUS
RCS
Higher current charging schemes require hot spot
monitoring of the adapter and the Type−C connector
temperature. The FAN6390MPX includes an NTC pin to
measure the temperature with an external NTC resistor
strategically placed on the PCB. Using only a single pin, the
FAN6390MPX outputs a known current onto the NTC pin
which is terminated to ground through an NTC resistor in
parallel with a standard 20kW resistor as shown in Figure
37. The resulting voltage on the NTC pin is then converted
to a temperature using the internal ADC and is used to report
the current temperature via USB PD messaging as well as
compare the temperature against an over−temperature
warning and fault thresholds. When the temperature exceeds
the Warning threshold, a USB PD Alert message will be sent
to the Sink to indicate that the temperature is close to causing
a fault as shown in Figure 38. If the temperature exceeds the
Primary
FB
LGATE
BLD
VIN
VDD
Ip−
cc1
CC1
VDD
Ip−
cc2
Protection
control
OVP
block
CC2
SFB
OVP Detection Circuit
9RVIN
Debounce
time
RVIN
OVP
tBLK−OVP
OVP Threshold
VIN−
OVP−MAX
Fault threshold for longer than T
, a USB PD
NTC−Debounce
Figure 35. Output Over Voltage Sense Block
Alert message will be sent indicating a Fault and the device
will enter Auto Restart Mode. Table 14 shows the warning
and protection thresholds which may vary slightly according
Under Voltage Lockout Protection
Under Voltage Lockout (UVLO) protects the system
when the output is short−circuited with small impedance.
to tolerance of R , R
and I
.
p
NTC
NTC
When VIN falls below
V
IN−OFF
threshold, the
FAN6390MPX will enter UVLO protection by disabling the
load switch, enabling the VIN bleeder and pulling SFB low
VDD
INTC
NTC
until VIN falls below V . Figure 36 illustrates the
LATCH−OFF
ADC
Converter
operation during a UVLO event. The primary side controller
restarts switching once VIN falls below V , but
LATCH−OFF
Rp
RNTC
the operation causes a restart due to the voltage being too
low on the VS pin on the primary side controller.
Figure 37. NTC Circuit Diagram
www.onsemi.com
21
FAN6390MPX
VNTC pin
GND
TX1+
TX1−
VBUS
CC1
GND
RX1+
RX1−
VBUS
SBU 2
D−
Warning
Fault
Zpollute −CC
D+
D−
D+
SBU1
VBUS
RX2−
RX2+
GND
CC2
VBUS
TX2−
TX2+
GND
℃
℃
100
110
Tempature
VBUS
Zpollute −CC
Figure 38. NTC vs. Temperature
Table 14. EXTERNAL OVER TEMPERATURE
PROTECTION THRESHOLD
USB Type −C
Message
Threshold
Setting
Figure 39. CC1/CC2 Short−circuited with Impedance
Warning
100°C
R =20k W@25°C
p
R
=100k W 1%@25°C
25/50
NTC
(B
Fault
110°C
=4300 k 1%)
CVIN
Cbus
VBUS
RCS
Internal Over Temperature Protection
The FAN6390MPX also implements internal over
temperature protection through an internal temperature
sensing circuit. Once the internal temperature exceeds the
fault protection threshold of 140℃, the FAN6390MPX
sends an Alert indicating an Fault and the device will enter
Auto Restart Mode.
Primary
FB
BLD
LGATE
VIN
VDD
Ip−
cc 1
CC1
Cable Fault Protection
In order to avoid the cable line melting caused by the
pollution such as low impedance across ground to BUS.
FAN6390MPX implements USB BUS line impedance
VDD
Ip−
cc2
Protection
control
block
CC −OVP
CC 2
SFB
detection. Before t
which is debonce time
CCDebounce
detecting cable attach status, load switch is not turned on and
FAN6390MPX start Bus line impedance detecting. If output
is low impedance under 2 kW, FAN6390MPX will enter
Auto Restart Mode so the load switch will not turn on. No
power deliver to output ensure system safety.
CC −lines OVP Sense Block
VCC1−
OVP
tCC−
OVP
CC −OVP
CC Signal Over−Voltage Protection
VCC2−
OVP
The USB Type−C CC pins are located physically close to
VBUS on the connector and could be shorted to VBUS via
conductive materials as shown in Figure 39. This not only
impacts PD protocol communication, but possibly damages
the CC pins because of high VBUS voltages. The
FAN6390MPX attempts to protect against damaging the CC
pins by implementing Over−Voltage−Protection on the CC
pins. The voltage on the CC1 and CC2 pins is continuously
Figure 40. CC OVP Sensing Block Diagram
Charge Pump for Synchronous Rectifier (SR)
Generally, TA SR driving voltage is powered from V
DD
derived from system V
which drives internal circuits and
BUS
SR MOSFET through GATE pin. The GATE driving voltage
can’t be higher than V . In order to achieve adapter
BUS
monitored, if the voltage increases above V
or
charging high efficiency at low output voltage and high
output current application, a new way to boosting GATE pin
voltage for Low Side SR is as .
CC1−OVP
V
for longer than V
, the CC
CC2−OVP
CC−OVP−Debounce
Over−Voltage Protection is triggered and the device enters
Auto Restart Mode.
www.onsemi.com
22
FAN6390MPX
Charge Pump
Control Circuit
system efficiency. This capacitance value should be less
than 10 nF and should be adjusted depending on the
MOSFET input capacitance which is needed to considered
as well. The design guideline can be refer to FAN6390MPX
application note.
switch
VDD
CP
CP
Low side SR
MOSFET
SR Driving
Circuit
GATE
GATE
Cgate
driver signal
t
Figure 41. Charge Pump Control Circuit
V
OH
While V < 4.2 V (typ.), FAN6390MPX enable charge
IN
Gate clamp level
pump circuit to have higher driving voltage V
for
OH
efficiency. During t
the switch in side Charge Pump
BNK
Control Circuit will switch to GND in order to have CP be
charged via SR Driving Circuit. After blanking time, the
Blanking time
switch will connect to V to boost V
The V will be
DD
OH.
OH
t
clamped to ensure the voltage no higher than pin maximum
rating to ensure driving circuit safe operation as Figure 42.
Basically, proper CP capacitance is needed to achieve better
Figure 42. Timing Flow of Charge Pump
Protections Threshold Summary
Table 15 gives an overview of the available protections.
Table 15. OVERVIEW OF PROTECTIONS
Protection
PDO Threshold
APDO Threshold
Under Voltage Lockout(UVLO)
V
IN−OFF
Output Over−Voltage Protection(OVP)
Output Under−Voltage Protection(UVP)
Output Over−Current Protection(OCP)
CC Lines Over−Voltage Protection(CC−OVP)
External Over Temperature Protection
120% (typ.)
70% (typ.)
V
IN−OFF
120% (typ.)
Non (Note 10)
5.75 V (typ.)
Warning:100°C (typ.) (Note 11)
Fault:110°C (typ.) (Note 11)
Internal Over Temperature Protection
10.APDO always works in CC mode
Fault:140°C (typ.) (Note 11)
11. Based on the external components R = 20 kW @ 25°C and R
= 100 kW 1% @ 25°C (B
= 4300 k 1%) and I
= 60 mA (typ.)
p
NTC
25/50
NTC
www.onsemi.com
23
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WQFN24, 4x4, 0.5P
CASE 510BE
ISSUE O
DATE 02 OCT 2013
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM THE TERMINAL TIP.
A
B
A3
D
EXPOSED Cu
MOLD CMPD
PIN ONE
REFERENCE
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
A1
E
DETAIL B
MILLIMETERS
ALTERNATE
DIM MIN
MAX
0.80
0.05
CONSTRUCTIONS
2X
0.10
C
A
A1
A3
b
0.70
0.00
2X
0.10
C
0.20 REF
TOP VIEW
0.20
0.30
L
L
D
4.00 BSC
D2
E
2.60
2.80
(A3)
DETAIL B
4.00 BSC
A
L1
E2
e
2.60
2.80
0.10
0.08
C
0.50 BSC
L
0.35
0.00
0.45
0.15
DETAIL A
L1
C
ALTERNATE
CONSTRUCTIONS
SEATING
PLANE
NOTE 4
A1
GENERIC
C
SIDE VIEW
MARKING DIAGRAM*
1
D2
DETAIL A
XXXXXX
24X L
XXXXXX
ALYWG
G
7
13
E2
XXXXXX= Specific Device Code
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
24
24X b
e
e/2
0.10 C A B
0.05
C
NOTE 3
BOTTOM VIEW
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
4.30
24X
0.57
2.82
2.82
1
4.30
PKG
OUTLINE
24X
0.32
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON78470F
WQFN24, 4X4, 0.5P
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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