FAN6605MX [ONSEMI]
用于反激转换器的 mWSaver™ PWM 控制器，65KHz，线路 OVP，过电压/欠电压保护;
| 型号： | FAN6605MX |
| 厂家： | 
ONSEMI |
| 描述： | 用于反激转换器的 mWSaver™ PWM 控制器，65KHz，线路 OVP，过电压/欠电压保护 控制器 信息通信管理 开关 光电二极管 转换器 |
| 文件： | 总18页 (文件大小：1090K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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January 2015
FAN6605
mWSaver™ PWM Controller
Features
Description
.
mWSaver™ Technology Provides Industry’s Best-in-
Class Standby Power
This highly integrated PWM controller provides several
features to enhance the performance of flyback
converters.
<100 mW at 25-mW Load for LCDM Adaptor
Internal High-Voltage JFET Startup
Low Operating Current: Under 2 mA
To minimize standby power consumption, a proprietary
adaptive green-mode function reduces switching
frequency at light-load condition. To avoid acoustic-
noise problems, the minimum PWM frequency is set
above 23 kHz. This green-mode function enables the
power supply to meet international power conservation
requirements, such as Energy Star®. With the internal
high-voltage startup circuitry, the power loss caused by
bleeding resistors is also eliminated. To further reduce
power consumption, FAN6605 uses the BiCMOS
process, which allows an operating current of only
2 mA. The standby power consumption can be under
100 mW for most of LCD monitor power supply designs.
Adaptively Decrease PWM Frequency with
Cycle Skipping to 23 kHz at Light-Load
Condition for Better Efficiency
Feedback Impedance Switching During
Minimum Load or No Load
.
Proprietary Asynchronous Frequency Hopping
Technique that Reduces EMI
.
.
.
.
Fixed PWM Frequency: 65 kHz
Internal Leading-Edge Blanking
FAN6605 integrates a frequency-hopping function that
reduces EMI emission of a power supply with minimum
Built-in Synchronized Slope Compensation
Auto-Restart Protection: Feedback Open-Loop
Protection (OLP), VDD Over-Voltage Protection
(OVP), Over-Temperature Protection (OTP), and
Line Over-Voltage Protection
line
filters.
The
built-in
synchronized
slope
compensation achieves a stable peak-current-mode
control and improves noise immunity. The proprietary
line compensation ensures constant output power limit
over a wide AC input voltage range from 90 VAC to
.
.
.
Soft Gate Drive with Clamped Output Voltage: 18 V
VDD Under-Voltage Lockout (UVLO)
264 VAC
.
FAN6605 provides many protection functions. The
internal feedback open-loop protection circuit protects
the power supply from open-feedback-loop condition or
output-short condition. It also has line under-voltage
protection (brownout protection) and over-voltage
protection using an input voltage sensing pin (VIN).
Programmable Constant Power Limit
(Full AC Input Range)
.
.
.
Internal OTP Sensor with Hysteresis
Build-in 5-ms Soft-Start Function
Input Voltage Sensing (VIN Pin) for Brown-In/Out
Protection with Hysteresis and Line Over-Voltage
Protection
FAN6605 is available in a 7-pin SOP package.
Applications
General-purpose switched-mode power supplies and
flyback power converters, including:
.
.
LCD Monitor Power Supply
Open-Frame SMPS
ENERGY STAR® is a registered trademark of the U.S. Department of Energy and the U.S. Environmental Protection Agency.
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
Ordering Information
Operating
Part Number Temperature
Range
PWM
Frequency
Packing
Method
Package
7-Lead, Small Outline Integrated Circuit
FAN6605MX
-40 to +105°C (SOIC), Depopulated JEDEC MS-112, .150
Inch Body
65 kHz
Reel & Tape
Application Diagram
N
EMI
Filter
Vo+
Vo-
+
+
L
1
VIN
7
6
VDD
HV
+
5
GATE
2
FB
3
SENSE
4
FAN6605
Figure 1.
Typical Application
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
2
Internal Block Diagram
HV
7
OTP
Re-start
Protection
OVP
OLP
VIN-OVP
VDD
Brownout Protection
Soft
Driver
5
GATE
VPWM
Cycle
Skipping
S
R
Q
VDD
6
Internal
BIAS
UVLO
VRESET
OSC
Soft-Start
Comparator
Pattern
Generator
Circuit
Blanking
SENSE
Soft-Start
VLimit
3
…
Current Limit
Comparator
VRESET
OVP
Debounce
Green
Mode
PWM
Comparator
VDD-OVP
5.3V
Max.
Duty
VPWM
VIN-ON / VIN-OFF
Slope
Compensation
3R
Brownout Protection
VLimit
2
FB
VIN
1
High/Low
Line Compensation
R
OLP
Delay
OLP
VIN-OVP
Debounce
VFB-OLP
OLP
Comparator
VIN-Protect
4
GND
Figure 2.
Internal Block Diagram
Marking Information
7
Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M: SOP)
M: Manufacture Flow Code
ZXYTT
6605
TM
Figure 3. Top Mark
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
3
Pin Configuration
SOP-7
VIN
FB
1
2
3
4
7
HV
SENSE
6
5
VDD
GND
GATE
Figure 4.
Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
Line-voltage detection. The line-voltage detection is used for brownout protection with hysteresis.
Constant output power limit over universal AC input range is also achieved using this VIN pin. It
is suggested to add a low-pass filter to filter out line ripple on the bulk capacitor. Pulling VIN
HIGH also triggers auto-restart protection.
1
VIN
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal on this pin and the current-sense signal on the SENSE pin.
2
3
FB
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
SENSE
GND
4
5
Ground
GATE The totem-pole output driver. Soft-driving waveform is implemented for improved EMI.
Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
6
7
VDD
HV
For startup, this pin is connected to the line input or bulk capacitor in series with resistors.
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VVDD
VFB
DC Supply Voltage(1, 2)
FB Pin Input Voltage
30
6.0
6.0
6.0
700
400
V
V
-0.3
-0.3
-0.3
VSENSE
VVIN
VHV
SENSE Pin Input Voltage
VIN Pin Input Voltage
V
V
HV Pin Input Voltage
V
Power Dissipation (TA＜50°C)
PD
mW
Thermal Resistance (Junction-to-Air)
Operating Junction Temperature
153
JA
TJ
C/W
C
-40
-55
+125
+150
+260
TSTG
TL
Storage Temperature Range
C
Lead Temperature (Wave Soldering or IR, 10 Seconds)
C
Human Body Model,
All Pins Except HV Pin
JEDEC: JESD22-A114
5.5
2.0
ESD
kV
Charged Device Model,
All Pins Except HV Pin
JEDEC: JESD22-C101
Notes:
1. All voltage values, except differential voltages, are given with respect to the network ground terminal.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD with HV pin: CDM=2000 V and HBM=3500 V.
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
5
Electrical Characteristics
VDD=11~24 V and TA=-40~105C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VDD Section
VOP
Continuously Operating Voltage
Full Load
22
17
11
8.8
30
2
V
V
VDD-ON Start Threshold Voltage
VDD-OFF Protection Mode
15
9
16
10
V
UVLO
IDD-ST
Normal Mode
6.8
7.8
V
Startup Current
VDD-ON – 0.16 V
µA
mA
µA
IDD-OP
IDD-OLP
Operating Supply Current
Internal Sink Current
VDD=15 V, GATE Open
VDD-OLP+0.1 V
30
6.5
25
75
60
7.5
26
90
Threshold Voltage on VDD for HV
JFET Turn-On
VDD-OLP
8.0
27
V
V
VDD-OVP VDD Over-Voltage Protection
VDD Over-Voltage Protection
tD-VDDOVP
125
200
µs
Debounce Time
HV Section
VDC=120 V, VDD=10 µF,
VDD=0 V
IHV
Supply Current Drawn from HV Pin
Leakage Current after Startup
mA
µA
2.0
3.5
1
5.0
20
HV=700 V, VDD=VDD-
OFF+1 V
IHV-LC
VDD
VDD
VDD-ON
VDD-ON
VDD-OFF
UVLO
VDD-OLP
t
t
Normal Mode
Protection Mode
Figure 5.
VDD Behavior
Continued on the following page…
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
6
Electrical Characteristics
VDD=11~24 V and TA=-40~105C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Oscillator Section
62
±4.5
20
65
±5.2
23
68
±5.9
26
Center Frequency
Hopping Range
fOSC
Frequency in Normal Mode
kHz
fOSC-G
tHOP
tSKIP-N
tSKIP-G
Green-Mode Frequency
Hopping Period
kHz
ms
ms
ms
10
12
14
Pulse-Skipping Period(4)
Pulse-Skipping Period(4)
VFB-SKIP<VFB<VFB-N
VFB-G<VFB<VFB-SKIP
180
90
200
220
Frequency Variation vs. VDD
Deviation
fDV
fDT
VDD=11 V to 22 V
5
5
%
%
Frequency Variation vs.
Temperature Deviation
TA=TJ =-40 to 105C
VIN Section
PWM Turn-Off (Brownout)
VIN-OFF
VIN-ON
VIN-Protect
tVIN-Protect
0.66
0.70
0.74
V
V
Threshold Voltage
VIN-OFF
0.17
+
VIN-OFF
0.20
+
VIN-OFF
0.23
+
PWM Turn-On (Brown-in)
Threshold Voltage
Threshold Voltage of VIN Over-
Voltage Protection
5.1
60
5.3
5.5
V
Debounce Time of VIN Over-
Voltage Protection
100
140
µs
Current-Sense Section
VLIMIT at
VIN=1 V
Threshold Voltage for Current Limit VIN=1 V
Threshold Voltage for Current Limit VIN=3 V
0.80
0.67
0.83
0.70
0.86
0.73
V
V
VLIMIT at
VIN=3 V
tPD
tLEB
tSS
Delay to Output
100
290
5.5
200
340
7.0
ns
ns
Leading-Edge Blanking Time
Period During Soft-Start Time
Steady State
Startup Time
240
4.0
ms
VLimit
=0.92V
=5.3V
VIN-Protect
VIN-OFF
VSENSE =0.83V
VSENSE =0.7V
VIN
VIN=1V
VIN=3V
Figure 6.
VIN vs. VSENSE
Continued on the following page…
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
7
Electrical Characteristics
VDD=11~24 V and TA=-40~105C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Feedback Input Section
AV
Internal FB Voltage Attenuation
Input Impedance
1/4.5
10
1/4.0
15
1/3.5
19
V/V
kΩ
V
ZFB
VFB=4 V
VFB-OPEN The Maximum Clamp of FB Voltage
FB Pin Open
5.1
5.3
5.5
FB Open-Loop Protection Triggering
VFB-OLP
Level
4.4
4.6
4.8
V
TA=25C
Delay Time of FB Pin Open-loop
Protection
tD-OLP
45.0
2.8
62.5
70.0
3.2
ms
VFB-N
VFB-G
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
3.0
V
V
VFB-N - 0.6
FB Threshold Voltage for Changing
Pulse-Skipping Period(4)
VFB-SKIP
2.5
2.7
2.9
V
FB Threshold Voltage for Zero-Duty
Recovery
VFB-ZDCR
1.6
1.4
1.8
1.6
2.0
1.8
V
V
VFB-ZDC FB Threshold Voltage for Zero-Duty
VFB-ZDCR -
ZDC Hysteresis
VFB-ZDC
0.12
0.15
0.19
V
PWM Frequency
fOSC
with cycle skipping
fOSC-G
VFB-ZDC VFB-ZDCR
VFB-SKIP
VFB-G
VFB-N
VFB
Figure 7.
Cycle Skipping vs. VFB
Continued on the following page…
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
8
Electrical Characteristics
VDD=11~24 V and TA=-40~105C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
GATE Section
DCYMAX Maximum Duty Cycle
VGATE-L Gate Low Voltage
VGATE-H Gate High Voltage
60
8
75
90
%
V
VDD=15 V, IO=50 mA
VDD=12 V, IO=50 mA
VDD=15 V, CL=1 nF
VDD=15 V, CL=1 nF
1.5
V
Gate Rising Time
Gate Falling Time
tr
tf
ns
ns
100
30
IGATE-
SOURCE
mA
V
Gate Source Current
VDD=15 V, GATE=6 V
VDD=22 V
700
VGATE-
CLAMP
Gate Output Clamping Voltage
18
Over-Temperature Protection Section (OTP)
TOTP
TRestart
Notes:
Protection Junction Temperature(5,7)
Restart Junction Temperature(6,7)
125
°C
°C
TOTP-25
4. Guarantee by design.
5. When OTP is activated, the PWM switching is shut down.
6. When junction temperature is lower than this level, IC resumes PWM switching.
7. These parameters are guaranteed by design.
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
9
Typical Performance Characteristics
Figure 9. Operation Supply Current (IDD-OP
)
Figure 8. Startup Current (IDD-ST) vs. Temperature
vs. Temperature
Figure 10.Start Threshold Voltage (VDD-ON
)
Figure 11.Minimum Operating Voltage (VDD-OFF
vs. Temperature
)
vs. Temperature
Figure 12.Supply Current Drawn from HV Pin (IHV
)
Figure 13.HV Pin Leakage Current After Startup
(IHV-LC) vs. Temperature
vs. Temperature
Figure 14.Frequency in Normal Mode (fOSC
)
Figure 15.Maximum Duty Cycle (DCYMAX
)
vs. Temperature
vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FAN6605 • Rev. 1.0
www.fairchildsemi.com
10
Typical Performance Characteristics
Figure 16.FB Open-Loop Trigger Level (VFB-OLP
)
Figure 17.Delay Time of FB Pin Open-Loop Protection
(tD-OLP) vs. Temperature
vs. Temperature
Figure 18.PWM Turn-Off Threshold Voltage
(VIN-OFF & VIN-ON) vs. Temperature
Figure 19.VDD Over-Voltage Protection (VDD-OVP
)
vs. Temperature
Figure 20.VIN vs. VLIMIT
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
11
Functional Description
Startup Current
Gate Output / Soft Driving
For startup, the HV pin is connected to the line input or
bulk capacitor in series with diodes and/or resistors. If HV
pin is connected to the line input, a 1-kV/ 1-A diode and a
100 kΩ resistor are recommended. If HV pin is connected
to the bulk capacitor, only the resistor is required. Startup
current drawn from pin HV (typically 3.5 mA) charges the
hold-up capacitor through the diode and resistor. When
the VDD capacitor level reaches VDD-ON, the startup current
switches off. At this moment, only the VDD capacitor
supplies the FAN6605 to maintain VDD before the
auxiliary winding of the main transformer to provide the
operating current.
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18 V Zener diode to protect power MOSFET transistors
against undesirable gate over-voltage. A soft-driving
circuit is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 5.5 ms soft-start
circuit significantly reduces the startup current spike and
output voltage overshoot.
Operating Current
Operating current is below 2 mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
FAN6605 inserts a synchronized positive-going ramp at
every switching cycle as slope compensation.
Green-Mode Operation
The proprietary green-mode function provides an off-
time modulation to reduce the switching frequency in
light-load and no-load conditions. The on time is limited
for better abnormal or brownout protection. VFB, which is
derived from the voltage feedback loop, is taken as the
reference. Once VFB is lower than the threshold voltage,
switching frequency is continuously decreased with
cycle skipping to the minimum green-mode frequency of
around 23 kHz.
Constant Output Power Limit
For constant output power limit over universal input-
voltage range, the peak-current threshold is adjusted by
the voltage of the VIN pin. Since the VIN pin is
connected to the rectified AC input line voltage through
the resistive divider, a higher line voltage generates a
higher VIN voltage. The threshold voltage decreases as
VIN increases, making the maximum output power at
high-line input voltage equal to that at low-line input.
The value of R-C network should not be so large that it
affects the power limit (shown in Figure 21). R and C
should be less than 100 and 470 pF, respectively.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switching current is detected by the current-sensing
resistor of SENSE pin. The PWM duty cycle is
determined by this current sense signal and VFB, the
feedback voltage. When the voltage on the SENSE pin
reaches around VCOMP=(VFB–0.6)/4, the PWM switching
turns off immediately.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
FAN6605
GATE
R
Blanking
SENSE
Circuit
C
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16 V and 7.8 V in normal mode. During startup, the
hold-up capacitor must be charged to 16 V through the
startup resistor to enable the IC. The hold-up capacitor
continues to supply VDD before the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 7.8 V during startup. This
UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply VDD during startup.
Figure 21. Current-Sense R-C Filter
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
12
and turns off most of the internal circuitry. The thermal
sensor turns internal circuitry on again after the IC’s
junction temperature drops by 25C. Thermal overload
protection is designed to protect the FAN6605 in the
event of a fault condition. For continual operation, the
controller should not exceed the absolute maximum
junction temperature of TJ = +140C.
VDD Over-Voltage Protection
VDD over-voltage protection prevents damage due to
abnormal conditions. Once the VDD voltage is over the
over-voltage protection voltage (VDD-OVP), and lasts for tD-
VDDOVP, the PWM pulses are disabled. When the VDD
voltage drops below the UVLO, the internal startup circuit
turns on, and VDD is charged to VDD-ON to restart IC.
Limited Power Control
Feedback Impedance Switching
The FB voltage is saturated HIGH when the power
supply output voltage drops below its nominal value and
shunt regulator (KA431) does not draw current through
the opto-coupler. This occurs when the output feedback
loop is open or output is short circuited. If the FB voltage
FAN6605 actively varies FB-pin impedance (ZFB) to
reduce no-load power consumption. This technique
can further reduce operating current of the controller
when FB-pin voltage drops below VFB-ZDC
.
is higher than a built-in threshold for longer than tD-OLP
,
Brownout Protection
PWM output is turned off. As PWM output is turned off,
VDD begins decreasing since no more energy is
delivered from the auxiliary winding.
Since the VIN pin is connected through a resistive
divider to the rectified AC input line voltage, it can also
be used for brownout protection. If VIN is less than 0.7 V,
the PWM output is shut off. When VIN reaches over
0.9 V, the PWM output is turned on again. The
hysteresis window for ON/OFF is around 0.2 V. The
brownout voltage setting is determined by the potential
divider formed with RUpper and RLower. Equations to
calculate the resistors are shown below:
As the protection is triggered, VDD enters into UVLO
mode. This protection feature continues as long as the
over loading condition persists. This prevents the power
supply from overheating due to overloading conditions.
Noise Immunity
Noise on the current sense or control signal may cause
significant pulse-width jitter, particularly in continuous-
conduction mode. Slope compensation helps alleviate
this problem. Good placement and layout practices
should be followed. Avoiding long PCB traces and
component leads, locating compensation and filter
components near the FAN6605, and increasing the gate
resistor from GATE pin to MOSFET improve
performance.
RLower
V
VAC 2,(unit V)
IN
(1)
RLower RUpper
Thermal Overload Protection
Thermal overload protection limits total power
dissipation. When the junction temperature exceeds TJ=
+140C, the thermal sensor signals the shutdown logic
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
13
Typical Application Circuit
R6
R7
12V 1
1
12V
P1
C7
N18
L2
2
12V
C5
1
3
R8
C10
C8
C9
+
+
F1
2
N1
N1A
R1
N2
BD 1
C1
C2
CN 1
TX 1
L
L1
4
1
N4
4
12
11
N17 D1
M1
1
2
3
C3
N28
R4
R5
N21
ZD 1
VIN
C4
R3
C6
AC IN
R2
8
N20
7
5V 1
1
5V
P2
L3
2
5V
N
N3
N5 N6
6
1
C11
+
1
3
D3
R14
2
N7
10
9
R17
2
D4
C15
C13
C14
+
+
C12
R13
D5
R9
N8
P3
SG ND
Q1
N30
R10
R16
N10
D2
1 N9
R11
R12
N29
R15
HV
VIN
U1
VIN
1
2
3
4
7
HV
R20
FB
VD D
FB
5V 1
R22
R19
6
5
N12
N13
SEN SE
VD D
U2
GA TE
GN D
GA TE
12V
5V
C16
C18
C19
FAN6605MX
+
R28
C17
SEN SE
R23
R24
R25
C20
R21
R
N14
N15
U3
N16
R18
R26
R27
Figure 22. 44 W Flyback 12 V/2 A, 5 V/4 A Application Circuit
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
14
Bill of Materials
Designator
Part Type
BD 4 A/600 V
Designator
Part Type
MOS 9 A/600 V
BD1
C1
Q1
R1
R2
R3
R 1.5 M 1/4 W
R 1.5 M 1/4 W
R 10 M 1/4 W
R 47 1/4 W
NC
YC 2200 pF/Y1
YC 2200 pF/Y1
XC 0.33 µF/300 V
NC
C2
C3
C4
R4, R5, R6, R7
C5
R8, R17, R25, R27
YC 2200 pF/Y1
CC 2200 pF/100 V
CC 1000 pF/100 V
EC 1000 µF/25 V
EC 470 µF/25 V
CC 100 pF/50 V
EC 100 µF/400 V
C 1 µF/50 V
C6
R9
R 50 K 1/4 W
R 50 K 1/4 W
R 0 1/8 W
C7
R10
R11
R12
R13
R14
R15
R16
R18
R19
R20
R21
R22
R23
R24
R26
R28
TX1
U1
C8
C9
R 47 1/8 W
R 100 K 1/8 W
R 0 1/4 W
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
R 10 K 1/8 W
R 1 1/8 W
EC 1000 µF/10 V
EC 470 µF/10 V
CC 100 pF/50 V
C 1 nF/50 V
R 0 1/8 W
R 100 1/8 W
R 1 K 1/8 W
R 4.7 K 1/8 W
R 7.5 K 1/8 W
R 120 K 1/8 W
R 15 K 1/8 W
R 10 K 1/8 W
R 0.43 2 W
800 µH(ERL-28)
IC FAN6605
C 470 pF/50 V
EC 47 µF/50 V
C 0.01 µF/50 V
C 0.1 µF/50 V
FYP1010
D2
1N4148
D3
FR107
D4
FR103
D5
U2
IC PC817
FYP1010
ZD1
F1
P6KE150A
U3
IC TL431
FUSE 4A/250 V
VZ 9G
M1
L1
13 mH
Inductor (2 µH)
Inductor (2 µH)
L2
L3
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6605 • Rev. 1.0
15
5.00
4.80
A
3.81
3.81
0.65TYP
1.75TYP
6
5
7
B
6.20
5.80
4.00
3.80
3.85 7.35
3
2
1
4
PIN #1
(0.33)
1.27
0.25
C B A
1.27
TOP VIEW
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.19
0.25
0.10
C
OPTION A - BEVEL EDGE
1.75 MAX
0.10 C
0.51
0.33
FRONT VIEW
OPTION B - NO BEVEL EDGE
0.50
0.25
ꢂ[ꢂꢃꢄ
NOTES:
R0.23
R0.23
GAGE PLANE
A) THIS PACKAGE DOES NOT FULLY
CONFORMS TO JEDEC MS-012,
VARIATION AA, ISSUE C.
0.36
ꢀ
ꢁ
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
0.90
0.406
(1.04)
DETAIL A
D) DRAWING FILENAME : M07Arev4.
SCALE: 2:1
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